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Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/0716-drm-amd-display-Move-OPP-to-stream_res.patch')
-rw-r--r--common/recipes-kernel/linux/linux-yocto-4.14.71/0716-drm-amd-display-Move-OPP-to-stream_res.patch269
1 files changed, 269 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/0716-drm-amd-display-Move-OPP-to-stream_res.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/0716-drm-amd-display-Move-OPP-to-stream_res.patch
new file mode 100644
index 00000000..07bf5ecf
--- /dev/null
+++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/0716-drm-amd-display-Move-OPP-to-stream_res.patch
@@ -0,0 +1,269 @@
+From b2432e3fa12ccff53d41432a1d6aa3af4f1ab17c Mon Sep 17 00:00:00 2001
+From: Harry Wentland <harry.wentland@amd.com>
+Date: Sun, 30 Jul 2017 13:55:28 -0400
+Subject: [PATCH 0716/4131] drm/amd/display: Move OPP to stream_res
+
+find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \
+-o -name "*.cpp" -o -name "*.hpp" | \
+xargs sed -i 's/pipes->opp/pipes->stream_res\.opp/g'
+
+find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \
+-o -name "*.cpp" -o -name "*.hpp" | \
+xargs sed -i 's/ctx->opp->/ctx->stream_res\.opp->/g'
+
+find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \
+-o -name "*.cpp" -o -name "*.hpp" | \
+xargs sed -i 's/pipe->opp/pipe->stream_res\.opp/g'
+
+find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \
+-o -name "*.cpp" -o -name "*.hpp" | \
+xargs sed -i 's/pipe_ctx->opp/pipe_ctx->stream_res\.opp/g'
+
+Signed-off-by: Harry Wentland <harry.wentland@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Harry Wentland <Harry.Wentland@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc.c | 4 ++--
+ drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 8 ++++----
+ drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 6 +++---
+ .../amd/display/dc/dce110/dce110_hw_sequencer.c | 12 +++++------
+ .../drm/amd/display/dc/dce110/dce110_resource.c | 2 +-
+ .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 24 +++++++++++-----------
+ .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 2 +-
+ drivers/gpu/drm/amd/display/dc/inc/core_types.h | 3 +--
+ 8 files changed, 30 insertions(+), 31 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index ffc9c05..507732e 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -365,8 +365,8 @@ void set_dither_option(struct dc_stream_state *stream,
+ resource_build_bit_depth_reduction_params(stream,
+ &params);
+ stream->bit_depth_params = params;
+- pipes->opp->funcs->
+- opp_program_bit_depth_reduction(pipes->opp, &params);
++ pipes->stream_res.opp->funcs->
++ opp_program_bit_depth_reduction(pipes->stream_res.opp, &params);
+ }
+
+ static void allocate_dc_stream_funcs(struct core_dc *core_dc)
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+index 231cade..0c90060 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+@@ -2372,8 +2372,8 @@ static void set_crtc_test_pattern(struct dc_link *link,
+ {
+ /* disable bit depth reduction */
+ pipe_ctx->stream->bit_depth_params = params;
+- pipe_ctx->opp->funcs->
+- opp_program_bit_depth_reduction(pipe_ctx->opp, &params);
++ pipe_ctx->stream_res.opp->funcs->
++ opp_program_bit_depth_reduction(pipe_ctx->stream_res.opp, &params);
+
+ pipe_ctx->tg->funcs->set_test_pattern(pipe_ctx->tg,
+ controller_test_pattern, color_depth);
+@@ -2385,8 +2385,8 @@ static void set_crtc_test_pattern(struct dc_link *link,
+ resource_build_bit_depth_reduction_params(pipe_ctx->stream,
+ &params);
+ pipe_ctx->stream->bit_depth_params = params;
+- pipe_ctx->opp->funcs->
+- opp_program_bit_depth_reduction(pipe_ctx->opp, &params);
++ pipe_ctx->stream_res.opp->funcs->
++ opp_program_bit_depth_reduction(pipe_ctx->stream_res.opp, &params);
+
+ pipe_ctx->tg->funcs->set_test_pattern(pipe_ctx->tg,
+ CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+index 77ca5dd..95278ac 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+@@ -1015,7 +1015,7 @@ static int acquire_first_split_pipe(
+ pipe_ctx->plane_res.mi = pool->mis[i];
+ pipe_ctx->plane_res.ipp = pool->ipps[i];
+ pipe_ctx->plane_res.xfm = pool->transforms[i];
+- pipe_ctx->opp = pool->opps[i];
++ pipe_ctx->stream_res.opp = pool->opps[i];
+ pipe_ctx->dis_clk = pool->display_clock;
+ pipe_ctx->pipe_idx = i;
+
+@@ -1095,7 +1095,7 @@ bool resource_attach_surfaces_to_context(
+
+ if (tail_pipe) {
+ free_pipe->tg = tail_pipe->tg;
+- free_pipe->opp = tail_pipe->opp;
++ free_pipe->stream_res.opp = tail_pipe->stream_res.opp;
+ free_pipe->stream_enc = tail_pipe->stream_enc;
+ free_pipe->audio = tail_pipe->audio;
+ free_pipe->clock_source = tail_pipe->clock_source;
+@@ -1245,7 +1245,7 @@ static int acquire_first_free_pipe(
+ pipe_ctx->plane_res.mi = pool->mis[i];
+ pipe_ctx->plane_res.ipp = pool->ipps[i];
+ pipe_ctx->plane_res.xfm = pool->transforms[i];
+- pipe_ctx->opp = pool->opps[i];
++ pipe_ctx->stream_res.opp = pool->opps[i];
+ pipe_ctx->dis_clk = pool->display_clock;
+ pipe_ctx->pipe_idx = i;
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+index 1586dc9..0601105 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+@@ -1044,16 +1044,16 @@ static enum dc_status apply_single_controller_ctx_to_hw(
+ /* */
+ dc->hwss.prog_pixclk_crtc_otg(pipe_ctx, context, dc);
+
+- pipe_ctx->opp->funcs->opp_set_dyn_expansion(
+- pipe_ctx->opp,
++ pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(
++ pipe_ctx->stream_res.opp,
+ COLOR_SPACE_YCBCR601,
+ stream->timing.display_color_depth,
+ pipe_ctx->stream->signal);
+
+ /* FPGA does not program backend */
+ if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+- pipe_ctx->opp->funcs->opp_program_fmt(
+- pipe_ctx->opp,
++ pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
++ pipe_ctx->stream_res.opp,
+ &stream->bit_depth_params,
+ &stream->clamping);
+ return DC_OK;
+@@ -1078,8 +1078,8 @@ static enum dc_status apply_single_controller_ctx_to_hw(
+
+
+ /*vbios crtc_source_selection and encoder_setup will override fmt_C*/
+- pipe_ctx->opp->funcs->opp_program_fmt(
+- pipe_ctx->opp,
++ pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
++ pipe_ctx->stream_res.opp,
+ &stream->bit_depth_params,
+ &stream->clamping);
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+index 04a50823..4b7bce2 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+@@ -1020,7 +1020,7 @@ static struct pipe_ctx *dce110_acquire_underlay(
+ pipe_ctx->plane_res.mi = pool->mis[underlay_idx];
+ /*pipe_ctx->plane_res.ipp = res_ctx->pool->ipps[underlay_idx];*/
+ pipe_ctx->plane_res.xfm = pool->transforms[underlay_idx];
+- pipe_ctx->opp = pool->opps[underlay_idx];
++ pipe_ctx->stream_res.opp = pool->opps[underlay_idx];
+ pipe_ctx->dis_clk = pool->display_clock;
+ pipe_ctx->pipe_idx = underlay_idx;
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+index 1cf672d..2db6b46 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+@@ -720,8 +720,8 @@ static enum dc_status dcn10_prog_pixclk_crtc_otg(
+ &stream->timing,
+ true);
+
+- pipe_ctx->opp->funcs->opp_set_stereo_polarity(
+- pipe_ctx->opp,
++ pipe_ctx->stream_res.opp->funcs->opp_set_stereo_polarity(
++ pipe_ctx->stream_res.opp,
+ enableStereo,
+ rightEyePolarity);
+
+@@ -731,8 +731,8 @@ static enum dc_status dcn10_prog_pixclk_crtc_otg(
+
+ inst_offset = reg_offsets[pipe_ctx->tg->inst].fmt;
+
+- pipe_ctx->opp->funcs->opp_program_fmt(
+- pipe_ctx->opp,
++ pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
++ pipe_ctx->stream_res.opp,
+ &stream->bit_depth_params,
+ &stream->clamping);
+ #endif
+@@ -1946,7 +1946,7 @@ static void update_dchubp_dpp(
+ IPP_OUTPUT_FORMAT_12_BIT_FIX);
+
+ mpcc_cfg.mi = mi;
+- mpcc_cfg.opp = pipe_ctx->opp;
++ mpcc_cfg.opp = pipe_ctx->stream_res.opp;
+ for (top_pipe = pipe_ctx->top_pipe; top_pipe; top_pipe = top_pipe->top_pipe)
+ mpcc_cfg.z_index++;
+ if (dc->public.debug.surface_visual_confirm)
+@@ -2122,9 +2122,9 @@ static void dcn10_apply_ctx_for_surface(
+ /* reset mpc */
+ dc->res_pool->mpc->funcs->remove(
+ dc->res_pool->mpc,
+- old_pipe_ctx->opp,
++ old_pipe_ctx->stream_res.opp,
+ old_pipe_ctx->pipe_idx);
+- old_pipe_ctx->opp->mpcc_disconnect_pending[old_pipe_ctx->plane_res.mi->mpcc_id] = true;
++ old_pipe_ctx->stream_res.opp->mpcc_disconnect_pending[old_pipe_ctx->plane_res.mi->mpcc_id] = true;
+
+ /*dm_logger_write(dc->ctx->logger, LOG_ERROR,
+ "[debug_mpo: apply_ctx disconnect pending on mpcc %d]\n",
+@@ -2364,8 +2364,8 @@ static void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct core_dc *dc)
+
+ dcn10_config_stereo_parameters(stream, &flags);
+
+- pipe_ctx->opp->funcs->opp_set_stereo_polarity(
+- pipe_ctx->opp,
++ pipe_ctx->stream_res.opp->funcs->opp_set_stereo_polarity(
++ pipe_ctx->stream_res.opp,
+ flags.PROGRAM_STEREO == 1 ? true:false,
+ stream->timing.flags.RIGHT_EYE_3D_POLARITY == 1 ? true:false);
+
+@@ -2441,13 +2441,13 @@ static void dcn10_wait_for_mpcc_disconnect(
+ {
+ int i;
+
+- if (!pipe_ctx->opp)
++ if (!pipe_ctx->stream_res.opp)
+ return;
+
+ for (i = 0; i < MAX_PIPES; i++) {
+- if (pipe_ctx->opp->mpcc_disconnect_pending[i]) {
++ if (pipe_ctx->stream_res.opp->mpcc_disconnect_pending[i]) {
+ res_pool->mpc->funcs->wait_for_idle(res_pool->mpc, i);
+- pipe_ctx->opp->mpcc_disconnect_pending[i] = false;
++ pipe_ctx->stream_res.opp->mpcc_disconnect_pending[i] = false;
+ res_pool->mis[i]->funcs->set_blank(res_pool->mis[i], true);
+ /*dm_logger_write(dc->ctx->logger, LOG_ERROR,
+ "[debug_mpo: wait_for_mpcc finished waiting on mpcc %d]\n",
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+index 710e514..e15eec3 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+@@ -961,7 +961,7 @@ static struct pipe_ctx *dcn10_acquire_idle_pipe_for_layer(
+
+ idle_pipe->stream = head_pipe->stream;
+ idle_pipe->tg = head_pipe->tg;
+- idle_pipe->opp = head_pipe->opp;
++ idle_pipe->stream_res.opp = head_pipe->stream_res.opp;
+
+ idle_pipe->plane_res.mi = pool->mis[idle_pipe->pipe_idx];
+ idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx];
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+index 4640c43..24a5254 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+@@ -153,7 +153,7 @@ struct resource_pool {
+ };
+
+ struct stream_resource {
+- int stub;
++ struct output_pixel_processor *opp;
+ };
+
+ struct plane_resource {
+@@ -171,7 +171,6 @@ struct pipe_ctx {
+ struct plane_resource plane_res;
+ struct stream_resource stream_res;
+
+- struct output_pixel_processor *opp;
+ struct timing_generator *tg;
+
+ struct stream_encoder *stream_enc;
+--
+2.7.4
+