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Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/0707-drm-amd-display-move-regamma-from-opp-to-dpp-for-dce.patch')
-rw-r--r--common/recipes-kernel/linux/linux-yocto-4.14.71/0707-drm-amd-display-move-regamma-from-opp-to-dpp-for-dce.patch1327
1 files changed, 1327 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/0707-drm-amd-display-move-regamma-from-opp-to-dpp-for-dce.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/0707-drm-amd-display-move-regamma-from-opp-to-dpp-for-dce.patch
new file mode 100644
index 00000000..7a6a0ae1
--- /dev/null
+++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/0707-drm-amd-display-move-regamma-from-opp-to-dpp-for-dce.patch
@@ -0,0 +1,1327 @@
+From 52abe4d72e928985e8f14830561f9c7dc8454c09 Mon Sep 17 00:00:00 2001
+From: Yue Hin Lau <Yuehin.Lau@amd.com>
+Date: Fri, 28 Jul 2017 13:08:03 -0400
+Subject: [PATCH 0707/4131] drm/amd/display: move regamma from opp to dpp for
+ dce
+
+Signed-off-by: Yue Hin Lau <Yuehin.Lau@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Harry Wentland <Harry.Wentland@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dce/dce_opp.c | 237 --------------------
+ drivers/gpu/drm/amd/display/dc/dce/dce_opp.h | 113 +---------
+ drivers/gpu/drm/amd/display/dc/dce/dce_transform.c | 240 +++++++++++++++++++++
+ drivers/gpu/drm/amd/display/dc/dce/dce_transform.h | 88 ++++++++
+ .../amd/display/dc/dce110/dce110_hw_sequencer.c | 18 +-
+ .../amd/display/dc/dce110/dce110_opp_regamma_v.c | 88 ++++----
+ .../gpu/drm/amd/display/dc/dce110/dce110_opp_v.c | 3 -
+ .../gpu/drm/amd/display/dc/dce110/dce110_opp_v.h | 11 -
+ .../drm/amd/display/dc/dce110/dce110_transform_v.c | 3 +
+ .../drm/amd/display/dc/dce110/dce110_transform_v.h | 14 ++
+ drivers/gpu/drm/amd/display/dc/inc/hw/opp.h | 17 --
+ 11 files changed, 399 insertions(+), 433 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c
+index 7abf252..348e4b7 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c
+@@ -92,242 +92,8 @@ enum {
+ *
+ *****************************************************************************
+ */
+-static void regamma_config_regions_and_segments(
+- struct dce110_opp *opp110,
+- const struct pwl_params *params)
+-{
+- const struct gamma_curve *curve;
+-
+- {
+- REG_SET_2(REGAMMA_CNTLA_START_CNTL, 0,
+- REGAMMA_CNTLA_EXP_REGION_START, params->arr_points[0].custom_float_x,
+- REGAMMA_CNTLA_EXP_REGION_START_SEGMENT, 0);
+- }
+- {
+- REG_SET(REGAMMA_CNTLA_SLOPE_CNTL, 0,
+- REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE, params->arr_points[0].custom_float_slope);
+-
+- }
+- {
+- REG_SET(REGAMMA_CNTLA_END_CNTL1, 0,
+- REGAMMA_CNTLA_EXP_REGION_END, params->arr_points[1].custom_float_x);
+- }
+- {
+- REG_SET_2(REGAMMA_CNTLA_END_CNTL2, 0,
+- REGAMMA_CNTLA_EXP_REGION_END_BASE, params->arr_points[1].custom_float_y,
+- REGAMMA_CNTLA_EXP_REGION_END_SLOPE, params->arr_points[2].custom_float_slope);
+- }
+-
+- curve = params->arr_curve_points;
+-
+- {
+- REG_SET_4(REGAMMA_CNTLA_REGION_0_1, 0,
+- REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+- REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+- REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+- REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
+- }
+-
+- curve += 2;
+-
+- {
+- REG_SET_4(REGAMMA_CNTLA_REGION_2_3, 0,
+- REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+- REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+- REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+- REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
+-
+- }
+-
+- curve += 2;
+-
+- {
+- REG_SET_4(REGAMMA_CNTLA_REGION_4_5, 0,
+- REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+- REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+- REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+- REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
+-
+- }
+-
+- curve += 2;
+
+- {
+- REG_SET_4(REGAMMA_CNTLA_REGION_6_7, 0,
+- REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+- REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+- REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+- REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
+
+- }
+-
+- curve += 2;
+-
+- {
+- REG_SET_4(REGAMMA_CNTLA_REGION_8_9, 0,
+- REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+- REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+- REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+- REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
+-
+- }
+-
+- curve += 2;
+-
+- {
+- REG_SET_4(REGAMMA_CNTLA_REGION_10_11, 0,
+- REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+- REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+- REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+- REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
+-
+- }
+-
+- curve += 2;
+-
+- {
+- REG_SET_4(REGAMMA_CNTLA_REGION_12_13, 0,
+- REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+- REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+- REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+- REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
+-
+- }
+-
+- curve += 2;
+-
+- {
+- REG_SET_4(REGAMMA_CNTLA_REGION_14_15, 0,
+- REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+- REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+- REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+- REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
+- }
+-}
+-
+-static void program_pwl(
+- struct dce110_opp *opp110,
+- const struct pwl_params *params)
+-{
+- uint32_t value;
+- int retval;
+-
+- {
+- uint8_t max_tries = 10;
+- uint8_t counter = 0;
+-
+- /* Power on LUT memory */
+- if (REG(DCFE_MEM_PWR_CTRL))
+- REG_UPDATE(DCFE_MEM_PWR_CTRL,
+- DCP_REGAMMA_MEM_PWR_DIS, 1);
+- else
+- REG_UPDATE(DCFE_MEM_LIGHT_SLEEP_CNTL,
+- REGAMMA_LUT_LIGHT_SLEEP_DIS, 1);
+-
+- while (counter < max_tries) {
+- if (REG(DCFE_MEM_PWR_STATUS)) {
+- value = REG_READ(DCFE_MEM_PWR_STATUS);
+- REG_GET(DCFE_MEM_PWR_STATUS,
+- DCP_REGAMMA_MEM_PWR_STATE,
+- &retval);
+-
+- if (retval == 0)
+- break;
+- ++counter;
+- } else {
+- value = REG_READ(DCFE_MEM_LIGHT_SLEEP_CNTL);
+- REG_GET(DCFE_MEM_LIGHT_SLEEP_CNTL,
+- REGAMMA_LUT_MEM_PWR_STATE,
+- &retval);
+-
+- if (retval == 0)
+- break;
+- ++counter;
+- }
+- }
+-
+- if (counter == max_tries) {
+- dm_logger_write(opp110->base.ctx->logger, LOG_WARNING,
+- "%s: regamma lut was not powered on "
+- "in a timely manner,"
+- " programming still proceeds\n",
+- __func__);
+- }
+- }
+-
+- REG_UPDATE(REGAMMA_LUT_WRITE_EN_MASK,
+- REGAMMA_LUT_WRITE_EN_MASK, 7);
+-
+- REG_WRITE(REGAMMA_LUT_INDEX, 0);
+-
+- /* Program REGAMMA_LUT_DATA */
+- {
+- uint32_t i = 0;
+- const struct pwl_result_data *rgb = params->rgb_resulted;
+-
+- while (i != params->hw_points_num) {
+-
+- REG_WRITE(REGAMMA_LUT_DATA, rgb->red_reg);
+- REG_WRITE(REGAMMA_LUT_DATA, rgb->green_reg);
+- REG_WRITE(REGAMMA_LUT_DATA, rgb->blue_reg);
+- REG_WRITE(REGAMMA_LUT_DATA, rgb->delta_red_reg);
+- REG_WRITE(REGAMMA_LUT_DATA, rgb->delta_green_reg);
+- REG_WRITE(REGAMMA_LUT_DATA, rgb->delta_blue_reg);
+-
+- ++rgb;
+- ++i;
+- }
+- }
+-
+- /* we are done with DCP LUT memory; re-enable low power mode */
+- if (REG(DCFE_MEM_PWR_CTRL))
+- REG_UPDATE(DCFE_MEM_PWR_CTRL,
+- DCP_REGAMMA_MEM_PWR_DIS, 0);
+- else
+- REG_UPDATE(DCFE_MEM_LIGHT_SLEEP_CNTL,
+- REGAMMA_LUT_LIGHT_SLEEP_DIS, 0);
+-}
+-
+-bool dce110_opp_program_regamma_pwl(
+- struct output_pixel_processor *opp,
+- const struct pwl_params *params)
+-{
+- struct dce110_opp *opp110 = TO_DCE110_OPP(opp);
+-
+- /* Setup regions */
+- regamma_config_regions_and_segments(opp110, params);
+-
+- /* Program PWL */
+- program_pwl(opp110, params);
+-
+- return true;
+-}
+-
+-void dce110_opp_power_on_regamma_lut(
+- struct output_pixel_processor *opp,
+- bool power_on)
+-{
+- struct dce110_opp *opp110 = TO_DCE110_OPP(opp);
+-
+- if (REG(DCFE_MEM_PWR_CTRL))
+- REG_UPDATE_2(DCFE_MEM_PWR_CTRL,
+- DCP_REGAMMA_MEM_PWR_DIS, power_on,
+- DCP_LUT_MEM_PWR_DIS, power_on);
+- else
+- REG_UPDATE_2(DCFE_MEM_LIGHT_SLEEP_CNTL,
+- REGAMMA_LUT_LIGHT_SLEEP_DIS, power_on,
+- DCP_LUT_LIGHT_SLEEP_DIS, power_on);
+-
+-}
+-
+-void dce110_opp_set_regamma_mode(struct output_pixel_processor *opp,
+- enum opp_regamma mode)
+-{
+- struct dce110_opp *opp110 = TO_DCE110_OPP(opp);
+-
+- REG_SET(REGAMMA_CONTROL, 0,
+- GRPH_REGAMMA_MODE, mode);
+-}
+
+ /**
+ * set_truncation
+@@ -768,10 +534,7 @@ void dce110_opp_program_fmt(
+ /*****************************************/
+
+ static const struct opp_funcs funcs = {
+- .opp_power_on_regamma_lut = dce110_opp_power_on_regamma_lut,
+ .opp_set_dyn_expansion = dce110_opp_set_dyn_expansion,
+- .opp_program_regamma_pwl = dce110_opp_program_regamma_pwl,
+- .opp_set_regamma_mode = dce110_opp_set_regamma_mode,
+ .opp_destroy = dce110_opp_destroy,
+ .opp_program_fmt = dce110_opp_program_fmt,
+ .opp_program_bit_depth_reduction = dce110_opp_program_bit_depth_reduction
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h
+index ca09f52..0874c22 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h
+@@ -41,22 +41,6 @@ enum dce110_opp_reg_type {
+ };
+
+ #define OPP_COMMON_REG_LIST_BASE(id) \
+- SRI(REGAMMA_CNTLA_START_CNTL, DCP, id), \
+- SRI(REGAMMA_CNTLA_SLOPE_CNTL, DCP, id), \
+- SRI(REGAMMA_CNTLA_END_CNTL1, DCP, id), \
+- SRI(REGAMMA_CNTLA_END_CNTL2, DCP, id), \
+- SRI(REGAMMA_CNTLA_REGION_0_1, DCP, id), \
+- SRI(REGAMMA_CNTLA_REGION_2_3, DCP, id), \
+- SRI(REGAMMA_CNTLA_REGION_4_5, DCP, id), \
+- SRI(REGAMMA_CNTLA_REGION_6_7, DCP, id), \
+- SRI(REGAMMA_CNTLA_REGION_8_9, DCP, id), \
+- SRI(REGAMMA_CNTLA_REGION_10_11, DCP, id), \
+- SRI(REGAMMA_CNTLA_REGION_12_13, DCP, id), \
+- SRI(REGAMMA_CNTLA_REGION_14_15, DCP, id), \
+- SRI(REGAMMA_LUT_WRITE_EN_MASK, DCP, id), \
+- SRI(REGAMMA_LUT_INDEX, DCP, id), \
+- SRI(REGAMMA_LUT_DATA, DCP, id), \
+- SRI(REGAMMA_CONTROL, DCP, id), \
+ SRI(FMT_DYNAMIC_EXP_CNTL, FMT, id), \
+ SRI(FMT_BIT_DEPTH_CONTROL, FMT, id), \
+ SRI(FMT_CONTROL, FMT, id), \
+@@ -70,31 +54,24 @@ enum dce110_opp_reg_type {
+
+ #define OPP_DCE_80_REG_LIST(id) \
+ OPP_COMMON_REG_LIST_BASE(id), \
+- SRI(DCFE_MEM_LIGHT_SLEEP_CNTL, CRTC, id), \
+ SRI(FMT_TEMPORAL_DITHER_PATTERN_CONTROL, FMT, id), \
+ SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX, FMT, id), \
+ SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX, FMT, id)
+
+ #define OPP_DCE_100_REG_LIST(id) \
+ OPP_COMMON_REG_LIST_BASE(id), \
+- SRI(DCFE_MEM_PWR_CTRL, CRTC, id), \
+- SRI(DCFE_MEM_PWR_STATUS, CRTC, id), \
+ SRI(FMT_TEMPORAL_DITHER_PATTERN_CONTROL, FMT, id), \
+ SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX, FMT, id), \
+ SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX, FMT, id)
+
+ #define OPP_DCE_110_REG_LIST(id) \
+ OPP_COMMON_REG_LIST_BASE(id), \
+- SRI(DCFE_MEM_PWR_CTRL, DCFE, id), \
+- SRI(DCFE_MEM_PWR_STATUS, DCFE, id), \
+ SRI(FMT_TEMPORAL_DITHER_PATTERN_CONTROL, FMT, id), \
+ SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX, FMT, id), \
+ SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX, FMT, id)
+
+ #define OPP_DCE_112_REG_LIST(id) \
+ OPP_COMMON_REG_LIST_BASE(id), \
+- SRI(DCFE_MEM_PWR_CTRL, DCFE, id), \
+- SRI(DCFE_MEM_PWR_STATUS, DCFE, id), \
+ SRI(FMT_TEMPORAL_DITHER_PATTERN_CONTROL, FMT, id), \
+ SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX, FMT, id), \
+ SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX, FMT, id), \
+@@ -102,26 +79,12 @@ enum dce110_opp_reg_type {
+
+ #define OPP_DCE_120_REG_LIST(id) \
+ OPP_COMMON_REG_LIST_BASE(id), \
+- SRI(DCFE_MEM_PWR_CTRL, DCFE, id), \
+- SRI(DCFE_MEM_PWR_STATUS, DCFE, id), \
+ SRI(CONTROL, FMT_MEMORY, id)
+
+ #define OPP_SF(reg_name, field_name, post_fix)\
+ .field_name = reg_name ## __ ## field_name ## post_fix
+
+ #define OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh)\
+- OPP_SF(REGAMMA_CNTLA_START_CNTL, REGAMMA_CNTLA_EXP_REGION_START, mask_sh),\
+- OPP_SF(REGAMMA_CNTLA_START_CNTL, REGAMMA_CNTLA_EXP_REGION_START_SEGMENT, mask_sh),\
+- OPP_SF(REGAMMA_CNTLA_SLOPE_CNTL, REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE, mask_sh),\
+- OPP_SF(REGAMMA_CNTLA_END_CNTL1, REGAMMA_CNTLA_EXP_REGION_END, mask_sh),\
+- OPP_SF(REGAMMA_CNTLA_END_CNTL2, REGAMMA_CNTLA_EXP_REGION_END_BASE, mask_sh),\
+- OPP_SF(REGAMMA_CNTLA_END_CNTL2, REGAMMA_CNTLA_EXP_REGION_END_SLOPE, mask_sh),\
+- OPP_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, mask_sh),\
+- OPP_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\
+- OPP_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, mask_sh),\
+- OPP_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\
+- OPP_SF(REGAMMA_LUT_WRITE_EN_MASK, REGAMMA_LUT_WRITE_EN_MASK, mask_sh),\
+- OPP_SF(REGAMMA_CONTROL, GRPH_REGAMMA_MODE, mask_sh),\
+ OPP_SF(FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_EN, mask_sh),\
+ OPP_SF(FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_MODE, mask_sh),\
+ OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, mask_sh),\
+@@ -160,27 +123,18 @@ enum dce110_opp_reg_type {
+
+ #define OPP_COMMON_MASK_SH_LIST_DCE_110(mask_sh)\
+ OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh),\
+- OPP_SF(DCFE_MEM_PWR_CTRL, DCP_REGAMMA_MEM_PWR_DIS, mask_sh),\
+- OPP_SF(DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh),\
+- OPP_SF(DCFE_MEM_PWR_STATUS, DCP_REGAMMA_MEM_PWR_STATE, mask_sh),\
+ OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh),\
+ OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh),\
+ OPP_SF(FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh)
+
+ #define OPP_COMMON_MASK_SH_LIST_DCE_100(mask_sh)\
+ OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh),\
+- OPP_SF(DCFE_MEM_PWR_CTRL, DCP_REGAMMA_MEM_PWR_DIS, mask_sh),\
+- OPP_SF(DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh),\
+- OPP_SF(DCFE_MEM_PWR_STATUS, DCP_REGAMMA_MEM_PWR_STATE, mask_sh),\
+ OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh),\
+ OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh),\
+ OPP_SF(FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh)
+
+ #define OPP_COMMON_MASK_SH_LIST_DCE_112(mask_sh)\
+ OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh),\
+- OPP_SF(DCFE_MEM_PWR_CTRL, DCP_REGAMMA_MEM_PWR_DIS, mask_sh),\
+- OPP_SF(DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh),\
+- OPP_SF(DCFE_MEM_PWR_STATUS, DCP_REGAMMA_MEM_PWR_STATE, mask_sh),\
+ OPP_SF(FMT_MEMORY0_CONTROL, FMT420_MEM0_SOURCE_SEL, mask_sh),\
+ OPP_SF(FMT_MEMORY0_CONTROL, FMT420_MEM0_PWR_FORCE, mask_sh),\
+ OPP_SF(FMT_CONTROL, FMT_420_PIXEL_PHASE_LOCKED_CLEAR, mask_sh),\
+@@ -191,27 +145,9 @@ enum dce110_opp_reg_type {
+ OPP_SF(FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh)
+
+ #define OPP_COMMON_MASK_SH_LIST_DCE_80(mask_sh)\
+- OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh),\
+- OPP_SF(DCFE_MEM_LIGHT_SLEEP_CNTL, REGAMMA_LUT_LIGHT_SLEEP_DIS, mask_sh),\
+- OPP_SF(DCFE_MEM_LIGHT_SLEEP_CNTL, DCP_LUT_LIGHT_SLEEP_DIS, mask_sh),\
+- OPP_SF(DCFE_MEM_LIGHT_SLEEP_CNTL, REGAMMA_LUT_MEM_PWR_STATE, mask_sh)
++ OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh)
+
+ #define OPP_COMMON_MASK_SH_LIST_DCE_120(mask_sh)\
+- OPP_SF(DCFE0_DCFE_MEM_PWR_CTRL, DCP_REGAMMA_MEM_PWR_DIS, mask_sh),\
+- OPP_SF(DCFE0_DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh),\
+- OPP_SF(DCP0_REGAMMA_CNTLA_START_CNTL, REGAMMA_CNTLA_EXP_REGION_START, mask_sh),\
+- OPP_SF(DCP0_REGAMMA_CNTLA_START_CNTL, REGAMMA_CNTLA_EXP_REGION_START_SEGMENT, mask_sh),\
+- OPP_SF(DCP0_REGAMMA_CNTLA_SLOPE_CNTL, REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE, mask_sh),\
+- OPP_SF(DCP0_REGAMMA_CNTLA_END_CNTL1, REGAMMA_CNTLA_EXP_REGION_END, mask_sh),\
+- OPP_SF(DCP0_REGAMMA_CNTLA_END_CNTL2, REGAMMA_CNTLA_EXP_REGION_END_BASE, mask_sh),\
+- OPP_SF(DCP0_REGAMMA_CNTLA_END_CNTL2, REGAMMA_CNTLA_EXP_REGION_END_SLOPE, mask_sh),\
+- OPP_SF(DCP0_REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, mask_sh),\
+- OPP_SF(DCP0_REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\
+- OPP_SF(DCP0_REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, mask_sh),\
+- OPP_SF(DCP0_REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\
+- OPP_SF(DCFE0_DCFE_MEM_PWR_STATUS, DCP_REGAMMA_MEM_PWR_STATE, mask_sh),\
+- OPP_SF(DCP0_REGAMMA_LUT_WRITE_EN_MASK, REGAMMA_LUT_WRITE_EN_MASK, mask_sh),\
+- OPP_SF(DCP0_REGAMMA_CONTROL, GRPH_REGAMMA_MODE, mask_sh),\
+ OPP_SF(FMT0_FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_EN, mask_sh),\
+ OPP_SF(FMT0_FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_MODE, mask_sh),\
+ OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, mask_sh),\
+@@ -257,24 +193,6 @@ enum dce110_opp_reg_type {
+ OPP_SF(FMT0_FMT_CONTROL, FMT_CBCR_BIT_REDUCTION_BYPASS, mask_sh)
+
+ #define OPP_REG_FIELD_LIST(type) \
+- type DCP_REGAMMA_MEM_PWR_DIS; \
+- type DCP_LUT_MEM_PWR_DIS; \
+- type REGAMMA_LUT_LIGHT_SLEEP_DIS; \
+- type DCP_LUT_LIGHT_SLEEP_DIS; \
+- type REGAMMA_CNTLA_EXP_REGION_START; \
+- type REGAMMA_CNTLA_EXP_REGION_START_SEGMENT; \
+- type REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE; \
+- type REGAMMA_CNTLA_EXP_REGION_END; \
+- type REGAMMA_CNTLA_EXP_REGION_END_BASE; \
+- type REGAMMA_CNTLA_EXP_REGION_END_SLOPE; \
+- type REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET; \
+- type REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS; \
+- type REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET; \
+- type REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS; \
+- type DCP_REGAMMA_MEM_PWR_STATE; \
+- type REGAMMA_LUT_MEM_PWR_STATE; \
+- type REGAMMA_LUT_WRITE_EN_MASK; \
+- type GRPH_REGAMMA_MODE; \
+ type FMT_DYNAMIC_EXP_EN; \
+ type FMT_DYNAMIC_EXP_MODE; \
+ type FMT_TRUNCATE_EN; \
+@@ -327,25 +245,6 @@ struct dce_opp_mask {
+ };
+
+ struct dce_opp_registers {
+- uint32_t DCFE_MEM_PWR_CTRL;
+- uint32_t DCFE_MEM_LIGHT_SLEEP_CNTL;
+- uint32_t REGAMMA_CNTLA_START_CNTL;
+- uint32_t REGAMMA_CNTLA_SLOPE_CNTL;
+- uint32_t REGAMMA_CNTLA_END_CNTL1;
+- uint32_t REGAMMA_CNTLA_END_CNTL2;
+- uint32_t REGAMMA_CNTLA_REGION_0_1;
+- uint32_t REGAMMA_CNTLA_REGION_2_3;
+- uint32_t REGAMMA_CNTLA_REGION_4_5;
+- uint32_t REGAMMA_CNTLA_REGION_6_7;
+- uint32_t REGAMMA_CNTLA_REGION_8_9;
+- uint32_t REGAMMA_CNTLA_REGION_10_11;
+- uint32_t REGAMMA_CNTLA_REGION_12_13;
+- uint32_t REGAMMA_CNTLA_REGION_14_15;
+- uint32_t REGAMMA_LUT_WRITE_EN_MASK;
+- uint32_t REGAMMA_LUT_INDEX;
+- uint32_t DCFE_MEM_PWR_STATUS;
+- uint32_t REGAMMA_LUT_DATA;
+- uint32_t REGAMMA_CONTROL;
+ uint32_t FMT_DYNAMIC_EXP_CNTL;
+ uint32_t FMT_BIT_DEPTH_CONTROL;
+ uint32_t FMT_CONTROL;
+@@ -382,17 +281,7 @@ bool dce110_opp_construct(struct dce110_opp *opp110,
+
+ void dce110_opp_destroy(struct output_pixel_processor **opp);
+
+-/* REGAMMA RELATED */
+-void dce110_opp_power_on_regamma_lut(
+- struct output_pixel_processor *opp,
+- bool power_on);
+-
+-bool dce110_opp_program_regamma_pwl(
+- struct output_pixel_processor *opp,
+- const struct pwl_params *params);
+
+-void dce110_opp_set_regamma_mode(struct output_pixel_processor *opp,
+- enum opp_regamma mode);
+
+ /* FORMATTER RELATED */
+ void dce110_opp_program_bit_depth_reduction(
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
+index fb64dca4..0e36602 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
+@@ -1177,7 +1177,244 @@ void dce110_opp_set_csc_default(
+ default_adjust->out_color_space);
+ }
+
++static void program_pwl(
++ struct dce_transform *xfm_dce,
++ const struct pwl_params *params)
++{
++ uint32_t value;
++ int retval;
++
++ {
++ uint8_t max_tries = 10;
++ uint8_t counter = 0;
++
++ /* Power on LUT memory */
++ if (REG(DCFE_MEM_PWR_CTRL))
++ REG_UPDATE(DCFE_MEM_PWR_CTRL,
++ DCP_REGAMMA_MEM_PWR_DIS, 1);
++ else
++ REG_UPDATE(DCFE_MEM_LIGHT_SLEEP_CNTL,
++ REGAMMA_LUT_LIGHT_SLEEP_DIS, 1);
++
++ while (counter < max_tries) {
++ if (REG(DCFE_MEM_PWR_STATUS)) {
++ value = REG_READ(DCFE_MEM_PWR_STATUS);
++ REG_GET(DCFE_MEM_PWR_STATUS,
++ DCP_REGAMMA_MEM_PWR_STATE,
++ &retval);
++
++ if (retval == 0)
++ break;
++ ++counter;
++ } else {
++ value = REG_READ(DCFE_MEM_LIGHT_SLEEP_CNTL);
++ REG_GET(DCFE_MEM_LIGHT_SLEEP_CNTL,
++ REGAMMA_LUT_MEM_PWR_STATE,
++ &retval);
++
++ if (retval == 0)
++ break;
++ ++counter;
++ }
++ }
++
++ if (counter == max_tries) {
++ dm_logger_write(xfm_dce->base.ctx->logger, LOG_WARNING,
++ "%s: regamma lut was not powered on "
++ "in a timely manner,"
++ " programming still proceeds\n",
++ __func__);
++ }
++ }
++
++ REG_UPDATE(REGAMMA_LUT_WRITE_EN_MASK,
++ REGAMMA_LUT_WRITE_EN_MASK, 7);
++
++ REG_WRITE(REGAMMA_LUT_INDEX, 0);
++
++ /* Program REGAMMA_LUT_DATA */
++ {
++ uint32_t i = 0;
++ const struct pwl_result_data *rgb = params->rgb_resulted;
++
++ while (i != params->hw_points_num) {
++
++ REG_WRITE(REGAMMA_LUT_DATA, rgb->red_reg);
++ REG_WRITE(REGAMMA_LUT_DATA, rgb->green_reg);
++ REG_WRITE(REGAMMA_LUT_DATA, rgb->blue_reg);
++ REG_WRITE(REGAMMA_LUT_DATA, rgb->delta_red_reg);
++ REG_WRITE(REGAMMA_LUT_DATA, rgb->delta_green_reg);
++ REG_WRITE(REGAMMA_LUT_DATA, rgb->delta_blue_reg);
++
++ ++rgb;
++ ++i;
++ }
++ }
++
++ /* we are done with DCP LUT memory; re-enable low power mode */
++ if (REG(DCFE_MEM_PWR_CTRL))
++ REG_UPDATE(DCFE_MEM_PWR_CTRL,
++ DCP_REGAMMA_MEM_PWR_DIS, 0);
++ else
++ REG_UPDATE(DCFE_MEM_LIGHT_SLEEP_CNTL,
++ REGAMMA_LUT_LIGHT_SLEEP_DIS, 0);
++}
++
++static void regamma_config_regions_and_segments(
++ struct dce_transform *xfm_dce,
++ const struct pwl_params *params)
++{
++ const struct gamma_curve *curve;
++
++ {
++ REG_SET_2(REGAMMA_CNTLA_START_CNTL, 0,
++ REGAMMA_CNTLA_EXP_REGION_START, params->arr_points[0].custom_float_x,
++ REGAMMA_CNTLA_EXP_REGION_START_SEGMENT, 0);
++ }
++ {
++ REG_SET(REGAMMA_CNTLA_SLOPE_CNTL, 0,
++ REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE, params->arr_points[0].custom_float_slope);
++
++ }
++ {
++ REG_SET(REGAMMA_CNTLA_END_CNTL1, 0,
++ REGAMMA_CNTLA_EXP_REGION_END, params->arr_points[1].custom_float_x);
++ }
++ {
++ REG_SET_2(REGAMMA_CNTLA_END_CNTL2, 0,
++ REGAMMA_CNTLA_EXP_REGION_END_BASE, params->arr_points[1].custom_float_y,
++ REGAMMA_CNTLA_EXP_REGION_END_SLOPE, params->arr_points[2].custom_float_slope);
++ }
++
++ curve = params->arr_curve_points;
++
++ {
++ REG_SET_4(REGAMMA_CNTLA_REGION_0_1, 0,
++ REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
++ REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
++ REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
++ REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
++ }
++
++ curve += 2;
++
++ {
++ REG_SET_4(REGAMMA_CNTLA_REGION_2_3, 0,
++ REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
++ REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
++ REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
++ REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
++
++ }
++
++ curve += 2;
++
++ {
++ REG_SET_4(REGAMMA_CNTLA_REGION_4_5, 0,
++ REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
++ REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
++ REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
++ REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
++
++ }
++
++ curve += 2;
++
++ {
++ REG_SET_4(REGAMMA_CNTLA_REGION_6_7, 0,
++ REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
++ REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
++ REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
++ REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
++
++ }
++
++ curve += 2;
++
++ {
++ REG_SET_4(REGAMMA_CNTLA_REGION_8_9, 0,
++ REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
++ REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
++ REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
++ REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
++
++ }
++
++ curve += 2;
++
++ {
++ REG_SET_4(REGAMMA_CNTLA_REGION_10_11, 0,
++ REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
++ REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
++ REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
++ REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
++
++ }
++
++ curve += 2;
++
++ {
++ REG_SET_4(REGAMMA_CNTLA_REGION_12_13, 0,
++ REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
++ REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
++ REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
++ REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
++
++ }
++
++ curve += 2;
++
++ {
++ REG_SET_4(REGAMMA_CNTLA_REGION_14_15, 0,
++ REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
++ REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
++ REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
++ REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
++ }
++}
++
++
++
++bool dce110_opp_program_regamma_pwl(
++ struct transform *xfm,
++ const struct pwl_params *params)
++{
++ struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm);
+
++ /* Setup regions */
++ regamma_config_regions_and_segments(xfm_dce, params);
++
++ /* Program PWL */
++ program_pwl(xfm_dce, params);
++
++ return true;
++}
++
++void dce110_opp_power_on_regamma_lut(
++ struct transform *xfm,
++ bool power_on)
++{
++ struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm);
++
++ if (REG(DCFE_MEM_PWR_CTRL))
++ REG_UPDATE_2(DCFE_MEM_PWR_CTRL,
++ DCP_REGAMMA_MEM_PWR_DIS, power_on,
++ DCP_LUT_MEM_PWR_DIS, power_on);
++ else
++ REG_UPDATE_2(DCFE_MEM_LIGHT_SLEEP_CNTL,
++ REGAMMA_LUT_LIGHT_SLEEP_DIS, power_on,
++ DCP_LUT_LIGHT_SLEEP_DIS, power_on);
++
++}
++
++void dce110_opp_set_regamma_mode(struct transform *xfm,
++ enum opp_regamma mode)
++{
++ struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm);
++
++ REG_SET(REGAMMA_CONTROL, 0,
++ GRPH_REGAMMA_MODE, mode);
++}
+
+ static const struct transform_funcs dce_transform_funcs = {
+ .transform_reset = dce_transform_reset,
+@@ -1187,6 +1424,9 @@ static const struct transform_funcs dce_transform_funcs = {
+ dce_transform_set_gamut_remap,
+ .opp_set_csc_adjustment = dce110_opp_set_csc_adjustment,
+ .opp_set_csc_default = dce110_opp_set_csc_default,
++ .opp_power_on_regamma_lut = dce110_opp_power_on_regamma_lut,
++ .opp_program_regamma_pwl = dce110_opp_program_regamma_pwl,
++ .opp_set_regamma_mode = dce110_opp_set_regamma_mode,
+ .transform_set_pixel_storage_depth =
+ dce_transform_set_pixel_storage_depth,
+ .transform_get_optimal_number_of_taps =
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h
+index 8632d8f..f9622ff 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h
+@@ -51,6 +51,22 @@
+ SRI(OUTPUT_CSC_C31_C32, DCP, id), \
+ SRI(OUTPUT_CSC_C33_C34, DCP, id), \
+ SRI(OUTPUT_CSC_CONTROL, DCP, id), \
++ SRI(REGAMMA_CNTLA_START_CNTL, DCP, id), \
++ SRI(REGAMMA_CNTLA_SLOPE_CNTL, DCP, id), \
++ SRI(REGAMMA_CNTLA_END_CNTL1, DCP, id), \
++ SRI(REGAMMA_CNTLA_END_CNTL2, DCP, id), \
++ SRI(REGAMMA_CNTLA_REGION_0_1, DCP, id), \
++ SRI(REGAMMA_CNTLA_REGION_2_3, DCP, id), \
++ SRI(REGAMMA_CNTLA_REGION_4_5, DCP, id), \
++ SRI(REGAMMA_CNTLA_REGION_6_7, DCP, id), \
++ SRI(REGAMMA_CNTLA_REGION_8_9, DCP, id), \
++ SRI(REGAMMA_CNTLA_REGION_10_11, DCP, id), \
++ SRI(REGAMMA_CNTLA_REGION_12_13, DCP, id), \
++ SRI(REGAMMA_CNTLA_REGION_14_15, DCP, id), \
++ SRI(REGAMMA_LUT_WRITE_EN_MASK, DCP, id), \
++ SRI(REGAMMA_LUT_INDEX, DCP, id), \
++ SRI(REGAMMA_LUT_DATA, DCP, id), \
++ SRI(REGAMMA_CONTROL, DCP, id), \
+ SRI(DENORM_CONTROL, DCP, id), \
+ SRI(DCP_SPATIAL_DITHER_CNTL, DCP, id), \
+ SRI(OUT_ROUND_CONTROL, DCP, id), \
+@@ -124,6 +140,18 @@
+ XFM_SF(OUTPUT_CSC_C11_C12, OUTPUT_CSC_C11, mask_sh),\
+ XFM_SF(OUTPUT_CSC_C11_C12, OUTPUT_CSC_C12, mask_sh),\
+ XFM_SF(OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, mask_sh),\
++ XFM_SF(REGAMMA_CNTLA_START_CNTL, REGAMMA_CNTLA_EXP_REGION_START, mask_sh),\
++ XFM_SF(REGAMMA_CNTLA_START_CNTL, REGAMMA_CNTLA_EXP_REGION_START_SEGMENT, mask_sh),\
++ XFM_SF(REGAMMA_CNTLA_SLOPE_CNTL, REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE, mask_sh),\
++ XFM_SF(REGAMMA_CNTLA_END_CNTL1, REGAMMA_CNTLA_EXP_REGION_END, mask_sh),\
++ XFM_SF(REGAMMA_CNTLA_END_CNTL2, REGAMMA_CNTLA_EXP_REGION_END_BASE, mask_sh),\
++ XFM_SF(REGAMMA_CNTLA_END_CNTL2, REGAMMA_CNTLA_EXP_REGION_END_SLOPE, mask_sh),\
++ XFM_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, mask_sh),\
++ XFM_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\
++ XFM_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, mask_sh),\
++ XFM_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\
++ XFM_SF(REGAMMA_LUT_WRITE_EN_MASK, REGAMMA_LUT_WRITE_EN_MASK, mask_sh),\
++ XFM_SF(REGAMMA_CONTROL, GRPH_REGAMMA_MODE, mask_sh),\
+ XFM_SF(SCL_MODE, SCL_MODE, mask_sh), \
+ XFM_SF(SCL_TAP_CONTROL, SCL_H_NUM_OF_TAPS, mask_sh), \
+ XFM_SF(SCL_TAP_CONTROL, SCL_V_NUM_OF_TAPS, mask_sh), \
+@@ -161,6 +189,9 @@
+ XFM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \
+ XFM_SF(DCFE_MEM_PWR_CTRL, SCL_COEFF_MEM_PWR_DIS, mask_sh), \
+ XFM_SF(DCFE_MEM_PWR_STATUS, SCL_COEFF_MEM_PWR_STATE, mask_sh), \
++ XFM_SF(DCFE_MEM_PWR_CTRL, DCP_REGAMMA_MEM_PWR_DIS, mask_sh),\
++ XFM_SF(DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh),\
++ XFM_SF(DCFE_MEM_PWR_STATUS, DCP_REGAMMA_MEM_PWR_STATE, mask_sh),\
+ XFM_SF(SCL_MODE, SCL_PSCL_EN, mask_sh)
+
+ #define XFM_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh) \
+@@ -196,6 +227,16 @@
+ XFM_SF(DCP0_OUTPUT_CSC_C11_C12, OUTPUT_CSC_C11, mask_sh),\
+ XFM_SF(DCP0_OUTPUT_CSC_C11_C12, OUTPUT_CSC_C12, mask_sh),\
+ XFM_SF(DCP0_OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, mask_sh),\
++ XFM_SF(DCP0_REGAMMA_CNTLA_START_CNTL, REGAMMA_CNTLA_EXP_REGION_START, mask_sh),\
++ XFM_SF(DCP0_REGAMMA_CNTLA_START_CNTL, REGAMMA_CNTLA_EXP_REGION_START_SEGMENT, mask_sh),\
++ XFM_SF(DCP0_REGAMMA_CNTLA_SLOPE_CNTL, REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE, mask_sh),\
++ XFM_SF(DCP0_REGAMMA_CNTLA_END_CNTL1, REGAMMA_CNTLA_EXP_REGION_END, mask_sh),\
++ XFM_SF(DCP0_REGAMMA_CNTLA_END_CNTL2, REGAMMA_CNTLA_EXP_REGION_END_BASE, mask_sh),\
++ XFM_SF(DCP0_REGAMMA_CNTLA_END_CNTL2, REGAMMA_CNTLA_EXP_REGION_END_SLOPE, mask_sh),\
++ XFM_SF(DCP0_REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, mask_sh),\
++ XFM_SF(DCP0_REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\
++ XFM_SF(DCP0_REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, mask_sh),\
++ XFM_SF(DCP0_REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\
+ XFM_SF(SCL0_SCL_MODE, SCL_MODE, mask_sh), \
+ XFM_SF(SCL0_SCL_TAP_CONTROL, SCL_H_NUM_OF_TAPS, mask_sh), \
+ XFM_SF(SCL0_SCL_TAP_CONTROL, SCL_V_NUM_OF_TAPS, mask_sh), \
+@@ -265,6 +306,24 @@
+ type OUTPUT_CSC_C11; \
+ type OUTPUT_CSC_C12; \
+ type OUTPUT_CSC_GRPH_MODE; \
++ type DCP_REGAMMA_MEM_PWR_DIS; \
++ type DCP_LUT_MEM_PWR_DIS; \
++ type REGAMMA_LUT_LIGHT_SLEEP_DIS; \
++ type DCP_LUT_LIGHT_SLEEP_DIS; \
++ type REGAMMA_CNTLA_EXP_REGION_START; \
++ type REGAMMA_CNTLA_EXP_REGION_START_SEGMENT; \
++ type REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE; \
++ type REGAMMA_CNTLA_EXP_REGION_END; \
++ type REGAMMA_CNTLA_EXP_REGION_END_BASE; \
++ type REGAMMA_CNTLA_EXP_REGION_END_SLOPE; \
++ type REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET; \
++ type REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS; \
++ type REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET; \
++ type REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS; \
++ type DCP_REGAMMA_MEM_PWR_STATE; \
++ type REGAMMA_LUT_MEM_PWR_STATE; \
++ type REGAMMA_LUT_WRITE_EN_MASK; \
++ type GRPH_REGAMMA_MODE; \
+ type SCL_MODE; \
+ type SCL_BYPASS_MODE; \
+ type SCL_PSCL_EN; \
+@@ -325,6 +384,23 @@ struct dce_transform_registers {
+ uint32_t OUTPUT_CSC_C31_C32;
+ uint32_t OUTPUT_CSC_C33_C34;
+ uint32_t OUTPUT_CSC_CONTROL;
++ uint32_t DCFE_MEM_LIGHT_SLEEP_CNTL;
++ uint32_t REGAMMA_CNTLA_START_CNTL;
++ uint32_t REGAMMA_CNTLA_SLOPE_CNTL;
++ uint32_t REGAMMA_CNTLA_END_CNTL1;
++ uint32_t REGAMMA_CNTLA_END_CNTL2;
++ uint32_t REGAMMA_CNTLA_REGION_0_1;
++ uint32_t REGAMMA_CNTLA_REGION_2_3;
++ uint32_t REGAMMA_CNTLA_REGION_4_5;
++ uint32_t REGAMMA_CNTLA_REGION_6_7;
++ uint32_t REGAMMA_CNTLA_REGION_8_9;
++ uint32_t REGAMMA_CNTLA_REGION_10_11;
++ uint32_t REGAMMA_CNTLA_REGION_12_13;
++ uint32_t REGAMMA_CNTLA_REGION_14_15;
++ uint32_t REGAMMA_LUT_WRITE_EN_MASK;
++ uint32_t REGAMMA_LUT_INDEX;
++ uint32_t REGAMMA_LUT_DATA;
++ uint32_t REGAMMA_CONTROL;
+ uint32_t DENORM_CONTROL;
+ uint32_t DCP_SPATIAL_DITHER_CNTL;
+ uint32_t OUT_ROUND_CONTROL;
+@@ -412,4 +488,16 @@ void dce110_opp_set_csc_default(
+ struct transform *xfm,
+ const struct default_adjustment *default_adjust);
+
++/* REGAMMA RELATED */
++void dce110_opp_power_on_regamma_lut(
++ struct transform *xfm,
++ bool power_on);
++
++bool dce110_opp_program_regamma_pwl(
++ struct transform *xfm,
++ const struct pwl_params *params);
++
++void dce110_opp_set_regamma_mode(struct transform *xfm,
++ enum opp_regamma mode);
++
+ #endif /* _DCE_DCE_TRANSFORM_H_ */
+diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+index b62a761..1f18fcf 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+@@ -625,26 +625,26 @@ static bool dce110_set_output_transfer_func(
+ struct pipe_ctx *pipe_ctx,
+ const struct dc_stream *stream)
+ {
+- struct output_pixel_processor *opp = pipe_ctx->opp;
++ struct transform *xfm = pipe_ctx->xfm;
+
+- opp->funcs->opp_power_on_regamma_lut(opp, true);
+- opp->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM;
++ xfm->funcs->opp_power_on_regamma_lut(xfm, true);
++ xfm->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM;
+
+ if (stream->out_transfer_func &&
+ stream->out_transfer_func->type ==
+ TF_TYPE_PREDEFINED &&
+ stream->out_transfer_func->tf ==
+ TRANSFER_FUNCTION_SRGB) {
+- opp->funcs->opp_set_regamma_mode(opp, OPP_REGAMMA_SRGB);
++ xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_SRGB);
+ } else if (dce110_translate_regamma_to_hw_format(
+- stream->out_transfer_func, &opp->regamma_params)) {
+- opp->funcs->opp_program_regamma_pwl(opp, &opp->regamma_params);
+- opp->funcs->opp_set_regamma_mode(opp, OPP_REGAMMA_USER);
++ stream->out_transfer_func, &xfm->regamma_params)) {
++ xfm->funcs->opp_program_regamma_pwl(xfm, &xfm->regamma_params);
++ xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_USER);
+ } else {
+- opp->funcs->opp_set_regamma_mode(opp, OPP_REGAMMA_BYPASS);
++ xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_BYPASS);
+ }
+
+- opp->funcs->opp_power_on_regamma_lut(opp, false);
++ xfm->funcs->opp_power_on_regamma_lut(xfm, false);
+
+ return true;
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c
+index 876445f..c86105b 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c
++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c
+@@ -29,12 +29,12 @@
+ #include "dce/dce_11_0_d.h"
+ #include "dce/dce_11_0_sh_mask.h"
+
+-#include "dce/dce_opp.h"
++#include "dce110_transform_v.h"
+
+-static void power_on_lut(struct output_pixel_processor *opp,
++static void power_on_lut(struct transform *xfm,
+ bool power_on, bool inputgamma, bool regamma)
+ {
+- uint32_t value = dm_read_reg(opp->ctx, mmDCFEV_MEM_PWR_CTRL);
++ uint32_t value = dm_read_reg(xfm->ctx, mmDCFEV_MEM_PWR_CTRL);
+ int i;
+
+ if (power_on) {
+@@ -65,10 +65,10 @@ static void power_on_lut(struct output_pixel_processor *opp,
+ COL_MAN_GAMMA_CORR_MEM_PWR_DIS);
+ }
+
+- dm_write_reg(opp->ctx, mmDCFEV_MEM_PWR_CTRL, value);
++ dm_write_reg(xfm->ctx, mmDCFEV_MEM_PWR_CTRL, value);
+
+ for (i = 0; i < 3; i++) {
+- value = dm_read_reg(opp->ctx, mmDCFEV_MEM_PWR_CTRL);
++ value = dm_read_reg(xfm->ctx, mmDCFEV_MEM_PWR_CTRL);
+ if (get_reg_field_value(value,
+ DCFEV_MEM_PWR_CTRL,
+ COL_MAN_INPUT_GAMMA_MEM_PWR_DIS) &&
+@@ -81,11 +81,11 @@ static void power_on_lut(struct output_pixel_processor *opp,
+ }
+ }
+
+-static void set_bypass_input_gamma(struct dce110_opp *opp110)
++static void set_bypass_input_gamma(struct dce_transform *xfm_dce)
+ {
+ uint32_t value;
+
+- value = dm_read_reg(opp110->base.ctx,
++ value = dm_read_reg(xfm_dce->base.ctx,
+ mmCOL_MAN_INPUT_GAMMA_CONTROL1);
+
+ set_reg_field_value(
+@@ -94,11 +94,11 @@ static void set_bypass_input_gamma(struct dce110_opp *opp110)
+ COL_MAN_INPUT_GAMMA_CONTROL1,
+ INPUT_GAMMA_MODE);
+
+- dm_write_reg(opp110->base.ctx,
++ dm_write_reg(xfm_dce->base.ctx,
+ mmCOL_MAN_INPUT_GAMMA_CONTROL1, value);
+ }
+
+-static void configure_regamma_mode(struct dce110_opp *opp110, uint32_t mode)
++static void configure_regamma_mode(struct dce_transform *xfm_dce, uint32_t mode)
+ {
+ uint32_t value = 0;
+
+@@ -108,7 +108,7 @@ static void configure_regamma_mode(struct dce110_opp *opp110, uint32_t mode)
+ GAMMA_CORR_CONTROL,
+ GAMMA_CORR_MODE);
+
+- dm_write_reg(opp110->base.ctx, mmGAMMA_CORR_CONTROL, 0);
++ dm_write_reg(xfm_dce->base.ctx, mmGAMMA_CORR_CONTROL, 0);
+ }
+
+ /*
+@@ -128,7 +128,7 @@ static void configure_regamma_mode(struct dce110_opp *opp110, uint32_t mode)
+ *****************************************************************************
+ */
+ static void regamma_config_regions_and_segments(
+- struct dce110_opp *opp110, const struct pwl_params *params)
++ struct dce_transform *xfm_dce, const struct pwl_params *params)
+ {
+ const struct gamma_curve *curve;
+ uint32_t value = 0;
+@@ -146,7 +146,7 @@ static void regamma_config_regions_and_segments(
+ GAMMA_CORR_CNTLA_START_CNTL,
+ GAMMA_CORR_CNTLA_EXP_REGION_START_SEGMENT);
+
+- dm_write_reg(opp110->base.ctx, mmGAMMA_CORR_CNTLA_START_CNTL,
++ dm_write_reg(xfm_dce->base.ctx, mmGAMMA_CORR_CNTLA_START_CNTL,
+ value);
+ }
+ {
+@@ -157,7 +157,7 @@ static void regamma_config_regions_and_segments(
+ GAMMA_CORR_CNTLA_SLOPE_CNTL,
+ GAMMA_CORR_CNTLA_EXP_REGION_LINEAR_SLOPE);
+
+- dm_write_reg(opp110->base.ctx,
++ dm_write_reg(xfm_dce->base.ctx,
+ mmGAMMA_CORR_CNTLA_SLOPE_CNTL, value);
+ }
+ {
+@@ -168,7 +168,7 @@ static void regamma_config_regions_and_segments(
+ GAMMA_CORR_CNTLA_END_CNTL1,
+ GAMMA_CORR_CNTLA_EXP_REGION_END);
+
+- dm_write_reg(opp110->base.ctx,
++ dm_write_reg(xfm_dce->base.ctx,
+ mmGAMMA_CORR_CNTLA_END_CNTL1, value);
+ }
+ {
+@@ -185,7 +185,7 @@ static void regamma_config_regions_and_segments(
+ GAMMA_CORR_CNTLA_END_CNTL2,
+ GAMMA_CORR_CNTLA_EXP_REGION_END_SLOPE);
+
+- dm_write_reg(opp110->base.ctx,
++ dm_write_reg(xfm_dce->base.ctx,
+ mmGAMMA_CORR_CNTLA_END_CNTL2, value);
+ }
+
+@@ -218,7 +218,7 @@ static void regamma_config_regions_and_segments(
+ GAMMA_CORR_CNTLA_EXP_REGION1_NUM_SEGMENTS);
+
+ dm_write_reg(
+- opp110->base.ctx,
++ xfm_dce->base.ctx,
+ mmGAMMA_CORR_CNTLA_REGION_0_1,
+ value);
+ }
+@@ -250,7 +250,7 @@ static void regamma_config_regions_and_segments(
+ GAMMA_CORR_CNTLA_REGION_2_3,
+ GAMMA_CORR_CNTLA_EXP_REGION3_NUM_SEGMENTS);
+
+- dm_write_reg(opp110->base.ctx,
++ dm_write_reg(xfm_dce->base.ctx,
+ mmGAMMA_CORR_CNTLA_REGION_2_3,
+ value);
+ }
+@@ -282,7 +282,7 @@ static void regamma_config_regions_and_segments(
+ GAMMA_CORR_CNTLA_REGION_4_5,
+ GAMMA_CORR_CNTLA_EXP_REGION5_NUM_SEGMENTS);
+
+- dm_write_reg(opp110->base.ctx,
++ dm_write_reg(xfm_dce->base.ctx,
+ mmGAMMA_CORR_CNTLA_REGION_4_5,
+ value);
+ }
+@@ -314,7 +314,7 @@ static void regamma_config_regions_and_segments(
+ GAMMA_CORR_CNTLA_REGION_6_7,
+ GAMMA_CORR_CNTLA_EXP_REGION7_NUM_SEGMENTS);
+
+- dm_write_reg(opp110->base.ctx,
++ dm_write_reg(xfm_dce->base.ctx,
+ mmGAMMA_CORR_CNTLA_REGION_6_7,
+ value);
+ }
+@@ -346,7 +346,7 @@ static void regamma_config_regions_and_segments(
+ GAMMA_CORR_CNTLA_REGION_8_9,
+ GAMMA_CORR_CNTLA_EXP_REGION9_NUM_SEGMENTS);
+
+- dm_write_reg(opp110->base.ctx,
++ dm_write_reg(xfm_dce->base.ctx,
+ mmGAMMA_CORR_CNTLA_REGION_8_9,
+ value);
+ }
+@@ -378,7 +378,7 @@ static void regamma_config_regions_and_segments(
+ GAMMA_CORR_CNTLA_REGION_10_11,
+ GAMMA_CORR_CNTLA_EXP_REGION11_NUM_SEGMENTS);
+
+- dm_write_reg(opp110->base.ctx,
++ dm_write_reg(xfm_dce->base.ctx,
+ mmGAMMA_CORR_CNTLA_REGION_10_11,
+ value);
+ }
+@@ -410,7 +410,7 @@ static void regamma_config_regions_and_segments(
+ GAMMA_CORR_CNTLA_REGION_12_13,
+ GAMMA_CORR_CNTLA_EXP_REGION13_NUM_SEGMENTS);
+
+- dm_write_reg(opp110->base.ctx,
++ dm_write_reg(xfm_dce->base.ctx,
+ mmGAMMA_CORR_CNTLA_REGION_12_13,
+ value);
+ }
+@@ -442,13 +442,13 @@ static void regamma_config_regions_and_segments(
+ GAMMA_CORR_CNTLA_REGION_14_15,
+ GAMMA_CORR_CNTLA_EXP_REGION15_NUM_SEGMENTS);
+
+- dm_write_reg(opp110->base.ctx,
++ dm_write_reg(xfm_dce->base.ctx,
+ mmGAMMA_CORR_CNTLA_REGION_14_15,
+ value);
+ }
+ }
+
+-static void program_pwl(struct dce110_opp *opp110,
++static void program_pwl(struct dce_transform *xfm_dce,
+ const struct pwl_params *params)
+ {
+ uint32_t value = 0;
+@@ -459,10 +459,10 @@ static void program_pwl(struct dce110_opp *opp110,
+ GAMMA_CORR_LUT_WRITE_EN_MASK,
+ GAMMA_CORR_LUT_WRITE_EN_MASK);
+
+- dm_write_reg(opp110->base.ctx,
++ dm_write_reg(xfm_dce->base.ctx,
+ mmGAMMA_CORR_LUT_WRITE_EN_MASK, value);
+
+- dm_write_reg(opp110->base.ctx,
++ dm_write_reg(xfm_dce->base.ctx,
+ mmGAMMA_CORR_LUT_INDEX, 0);
+
+ /* Program REGAMMA_LUT_DATA */
+@@ -473,15 +473,15 @@ static void program_pwl(struct dce110_opp *opp110,
+ params->rgb_resulted;
+
+ while (i != params->hw_points_num) {
+- dm_write_reg(opp110->base.ctx, addr, rgb->red_reg);
+- dm_write_reg(opp110->base.ctx, addr, rgb->green_reg);
+- dm_write_reg(opp110->base.ctx, addr, rgb->blue_reg);
++ dm_write_reg(xfm_dce->base.ctx, addr, rgb->red_reg);
++ dm_write_reg(xfm_dce->base.ctx, addr, rgb->green_reg);
++ dm_write_reg(xfm_dce->base.ctx, addr, rgb->blue_reg);
+
+- dm_write_reg(opp110->base.ctx, addr,
++ dm_write_reg(xfm_dce->base.ctx, addr,
+ rgb->delta_red_reg);
+- dm_write_reg(opp110->base.ctx, addr,
++ dm_write_reg(xfm_dce->base.ctx, addr,
+ rgb->delta_green_reg);
+- dm_write_reg(opp110->base.ctx, addr,
++ dm_write_reg(xfm_dce->base.ctx, addr,
+ rgb->delta_blue_reg);
+
+ ++rgb;
+@@ -491,36 +491,36 @@ static void program_pwl(struct dce110_opp *opp110,
+ }
+
+ bool dce110_opp_program_regamma_pwl_v(
+- struct output_pixel_processor *opp,
++ struct transform *xfm,
+ const struct pwl_params *params)
+ {
+- struct dce110_opp *opp110 = TO_DCE110_OPP(opp);
++ struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm);
+
+ /* Setup regions */
+- regamma_config_regions_and_segments(opp110, params);
++ regamma_config_regions_and_segments(xfm_dce, params);
+
+- set_bypass_input_gamma(opp110);
++ set_bypass_input_gamma(xfm_dce);
+
+ /* Power on gamma LUT memory */
+- power_on_lut(opp, true, false, true);
++ power_on_lut(xfm, true, false, true);
+
+ /* Program PWL */
+- program_pwl(opp110, params);
++ program_pwl(xfm_dce, params);
+
+ /* program regamma config */
+- configure_regamma_mode(opp110, 1);
++ configure_regamma_mode(xfm_dce, 1);
+
+ /* Power return to auto back */
+- power_on_lut(opp, false, false, true);
++ power_on_lut(xfm, false, false, true);
+
+ return true;
+ }
+
+ void dce110_opp_power_on_regamma_lut_v(
+- struct output_pixel_processor *opp,
++ struct transform *xfm,
+ bool power_on)
+ {
+- uint32_t value = dm_read_reg(opp->ctx, mmDCFEV_MEM_PWR_CTRL);
++ uint32_t value = dm_read_reg(xfm->ctx, mmDCFEV_MEM_PWR_CTRL);
+
+ set_reg_field_value(
+ value,
+@@ -546,11 +546,11 @@ void dce110_opp_power_on_regamma_lut_v(
+ DCFEV_MEM_PWR_CTRL,
+ COL_MAN_INPUT_GAMMA_MEM_PWR_DIS);
+
+- dm_write_reg(opp->ctx, mmDCFEV_MEM_PWR_CTRL, value);
++ dm_write_reg(xfm->ctx, mmDCFEV_MEM_PWR_CTRL, value);
+ }
+
+ void dce110_opp_set_regamma_mode_v(
+- struct output_pixel_processor *opp,
++ struct transform *xfm,
+ enum opp_regamma mode)
+ {
+ // TODO: need to implement the function
+diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.c
+index 24d9032f..69d6a11 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.c
++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.c
+@@ -37,10 +37,7 @@
+ /*****************************************/
+
+ static const struct opp_funcs funcs = {
+- .opp_power_on_regamma_lut = dce110_opp_power_on_regamma_lut_v,
+- .opp_program_regamma_pwl = dce110_opp_program_regamma_pwl_v,
+ .opp_set_dyn_expansion = dce110_opp_set_dyn_expansion,
+- .opp_set_regamma_mode = dce110_opp_set_regamma_mode_v,
+ .opp_destroy = dce110_opp_destroy,
+ .opp_program_fmt = dce110_opp_program_fmt,
+ .opp_program_bit_depth_reduction =
+diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.h
+index 7deaa4f..269c1a8 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.h
++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.h
+@@ -35,16 +35,5 @@ bool dce110_opp_v_construct(struct dce110_opp *opp110,
+ /* underlay callbacks */
+
+
+-bool dce110_opp_program_regamma_pwl_v(
+- struct output_pixel_processor *opp,
+- const struct pwl_params *params);
+-
+-void dce110_opp_power_on_regamma_lut_v(
+- struct output_pixel_processor *opp,
+- bool power_on);
+-
+-void dce110_opp_set_regamma_mode_v(
+- struct output_pixel_processor *opp,
+- enum opp_regamma mode);
+
+ #endif /* __DC_OPP_DCE110_V_H__ */
+diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c
+index f655145..c84823a 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c
++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c
+@@ -683,6 +683,9 @@ static const struct transform_funcs dce110_xfmv_funcs = {
+ dce110_xfmv_set_gamut_remap,
+ .opp_set_csc_default = dce110_opp_v_set_csc_default,
+ .opp_set_csc_adjustment = dce110_opp_v_set_csc_adjustment,
++ .opp_power_on_regamma_lut = dce110_opp_power_on_regamma_lut_v,
++ .opp_program_regamma_pwl = dce110_opp_program_regamma_pwl_v,
++ .opp_set_regamma_mode = dce110_opp_set_regamma_mode_v,
+ .transform_set_pixel_storage_depth =
+ dce110_xfmv_set_pixel_storage_depth,
+ .transform_get_optimal_number_of_taps =
+diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.h
+index b7f8fdb..eeed3b9 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.h
++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.h
+@@ -41,4 +41,18 @@ void dce110_opp_v_set_csc_default(
+ void dce110_opp_v_set_csc_adjustment(
+ struct transform *xfm,
+ const struct out_csc_color_matrix *tbl_entry);
++
++
++bool dce110_opp_program_regamma_pwl_v(
++ struct transform *xfm,
++ const struct pwl_params *params);
++
++void dce110_opp_power_on_regamma_lut_v(
++ struct transform *xfm,
++ bool power_on);
++
++void dce110_opp_set_regamma_mode_v(
++ struct transform *xfm,
++ enum opp_regamma mode);
++
+ #endif
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
+index a4f8556..dadd2ad 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
+@@ -251,24 +251,7 @@ enum ovl_csc_adjust_item {
+ };
+
+ struct opp_funcs {
+- void (*opp_power_on_regamma_lut)(
+- struct output_pixel_processor *opp,
+- bool power_on);
+-
+- bool (*opp_program_regamma_pwl)(
+- struct output_pixel_processor *opp,
+- const struct pwl_params *params);
+-
+- void (*opp_set_regamma_mode)(struct output_pixel_processor *opp,
+- enum opp_regamma mode);
+
+- void (*opp_set_csc_adjustment)(
+- struct output_pixel_processor *opp,
+- const struct out_csc_color_matrix *tbl_entry);
+-
+- void (*opp_set_csc_default)(
+- struct output_pixel_processor *opp,
+- const struct default_adjustment *default_adjust);
+
+ /* FORMATTER RELATED */
+
+--
+2.7.4
+