diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/0688-drm-amd-display-Fix-compilation-with-DCN-disabled.patch')
-rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.14.71/0688-drm-amd-display-Fix-compilation-with-DCN-disabled.patch | 51 |
1 files changed, 51 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/0688-drm-amd-display-Fix-compilation-with-DCN-disabled.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/0688-drm-amd-display-Fix-compilation-with-DCN-disabled.patch new file mode 100644 index 00000000..e137d9c1 --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/0688-drm-amd-display-Fix-compilation-with-DCN-disabled.patch @@ -0,0 +1,51 @@ +From d4347901787cf38850879633dd231ac3dc1e2982 Mon Sep 17 00:00:00 2001 +From: Harry Wentland <harry.wentland@amd.com> +Date: Wed, 26 Jul 2017 19:18:02 -0400 +Subject: [PATCH 0688/4131] drm/amd/display: Fix compilation with DCN disabled + +No need to guard the register defines. + +Signed-off-by: Harry Wentland <harry.wentland@amd.com> +Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> +Acked-by: Harry Wentland <Harry.Wentland@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | 6 ------ + 1 file changed, 6 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h +index 490ca12..ade7507 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h ++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h +@@ -462,7 +462,6 @@ struct dce_hwseq_registers { + type PHYPLL_PIXEL_RATE_SOURCE; \ + type PIXEL_RATE_PLL_SOURCE; \ + +-#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + #define HWSEQ_DCN_REG_FIELD_LIST(type) \ + type VUPDATE_NO_LOCK_EVENT_CLEAR; \ + type VUPDATE_NO_LOCK_EVENT_OCCURRED; \ +@@ -518,20 +517,15 @@ struct dce_hwseq_registers { + type DCFCLK_GATE_DIS; \ + type DCHUBBUB_GLOBAL_TIMER_REFDIV; \ + type DENTIST_DPPCLK_WDIVIDER; +-#endif + + struct dce_hwseq_shift { + HWSEQ_REG_FIELD_LIST(uint8_t) +-#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + HWSEQ_DCN_REG_FIELD_LIST(uint8_t) +-#endif + }; + + struct dce_hwseq_mask { + HWSEQ_REG_FIELD_LIST(uint32_t) +-#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + HWSEQ_DCN_REG_FIELD_LIST(uint32_t) +-#endif + }; + + +-- +2.7.4 + |