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Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/0653-drm-amd-display-move-ocsc-programming-from-opp-to-dp.patch')
-rw-r--r--common/recipes-kernel/linux/linux-yocto-4.14.71/0653-drm-amd-display-move-ocsc-programming-from-opp-to-dp.patch679
1 files changed, 679 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/0653-drm-amd-display-move-ocsc-programming-from-opp-to-dp.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/0653-drm-amd-display-move-ocsc-programming-from-opp-to-dp.patch
new file mode 100644
index 00000000..85a6bd24
--- /dev/null
+++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/0653-drm-amd-display-move-ocsc-programming-from-opp-to-dp.patch
@@ -0,0 +1,679 @@
+From b1d39c625210cb0f2b560b0e86c02debe5bf4fe7 Mon Sep 17 00:00:00 2001
+From: Tony Cheng <tony.cheng@amd.com>
+Date: Sat, 22 Jul 2017 21:58:08 -0400
+Subject: [PATCH 0653/4131] drm/amd/display: move ocsc programming from opp to
+ dpp
+
+Signed-off-by: Tony Cheng <tony.cheng@amd.com>
+Reviewed-by: Yuehin Lau <Yuehin.Lau@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Harry Wentland <Harry.Wentland@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c | 148 +++++++++++++++++++++
+ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h | 46 ++++++-
+ .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 2 +-
+ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c | 147 --------------------
+ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h | 40 ------
+ drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h | 37 ++++++
+ drivers/gpu/drm/amd/display/dc/inc/hw/opp.h | 21 ---
+ drivers/gpu/drm/amd/display/dc/inc/hw/transform.h | 26 ++--
+ 8 files changed, 242 insertions(+), 225 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
+index fff81a1..0f3f1a3 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
+@@ -988,11 +988,159 @@ static void dcn_dpp_set_gamut_remap(
+ }
+ }
+
++static void oppn10_set_output_csc_default(
++ struct transform *xfm_base,
++ const struct default_adjustment *default_adjust)
++{
++
++ struct dcn10_dpp *xfm = TO_DCN10_DPP(xfm_base);
++ uint32_t ocsc_mode = 0;
++
++ if (default_adjust != NULL) {
++ switch (default_adjust->out_color_space) {
++ case COLOR_SPACE_SRGB:
++ case COLOR_SPACE_2020_RGB_FULLRANGE:
++ ocsc_mode = 0;
++ break;
++ case COLOR_SPACE_SRGB_LIMITED:
++ case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
++ ocsc_mode = 1;
++ break;
++ case COLOR_SPACE_YCBCR601:
++ case COLOR_SPACE_YCBCR601_LIMITED:
++ ocsc_mode = 2;
++ break;
++ case COLOR_SPACE_YCBCR709:
++ case COLOR_SPACE_YCBCR709_LIMITED:
++ case COLOR_SPACE_2020_YCBCR:
++ ocsc_mode = 3;
++ break;
++ case COLOR_SPACE_UNKNOWN:
++ default:
++ break;
++ }
++ }
++
++ REG_SET(CM_OCSC_CONTROL, 0, CM_OCSC_MODE, ocsc_mode);
++
++}
++
++static void oppn10_program_color_matrix(
++ struct dcn10_dpp *xfm,
++ const struct out_csc_color_matrix *tbl_entry)
++{
++ uint32_t mode;
++
++ REG_GET(CM_OCSC_CONTROL, CM_OCSC_MODE, &mode);
++
++ if (tbl_entry == NULL) {
++ BREAK_TO_DEBUGGER();
++ return;
++ }
++
++ if (mode == 4) {
++ /*R*/
++ REG_SET_2(CM_OCSC_C11_C12, 0,
++ CM_OCSC_C11, tbl_entry->regval[0],
++ CM_OCSC_C12, tbl_entry->regval[1]);
++
++ REG_SET_2(CM_OCSC_C13_C14, 0,
++ CM_OCSC_C13, tbl_entry->regval[2],
++ CM_OCSC_C14, tbl_entry->regval[3]);
++
++ /*G*/
++ REG_SET_2(CM_OCSC_C21_C22, 0,
++ CM_OCSC_C21, tbl_entry->regval[4],
++ CM_OCSC_C22, tbl_entry->regval[5]);
++
++ REG_SET_2(CM_OCSC_C23_C24, 0,
++ CM_OCSC_C23, tbl_entry->regval[6],
++ CM_OCSC_C24, tbl_entry->regval[7]);
++
++ /*B*/
++ REG_SET_2(CM_OCSC_C31_C32, 0,
++ CM_OCSC_C31, tbl_entry->regval[8],
++ CM_OCSC_C32, tbl_entry->regval[9]);
++
++ REG_SET_2(CM_OCSC_C33_C34, 0,
++ CM_OCSC_C33, tbl_entry->regval[10],
++ CM_OCSC_C34, tbl_entry->regval[11]);
++ } else {
++ /*R*/
++ REG_SET_2(CM_COMB_C11_C12, 0,
++ CM_COMB_C11, tbl_entry->regval[0],
++ CM_COMB_C12, tbl_entry->regval[1]);
++
++ REG_SET_2(CM_COMB_C13_C14, 0,
++ CM_COMB_C13, tbl_entry->regval[2],
++ CM_COMB_C14, tbl_entry->regval[3]);
++
++ /*G*/
++ REG_SET_2(CM_COMB_C21_C22, 0,
++ CM_COMB_C21, tbl_entry->regval[4],
++ CM_COMB_C22, tbl_entry->regval[5]);
++
++ REG_SET_2(CM_COMB_C23_C24, 0,
++ CM_COMB_C23, tbl_entry->regval[6],
++ CM_COMB_C24, tbl_entry->regval[7]);
++
++ /*B*/
++ REG_SET_2(CM_COMB_C31_C32, 0,
++ CM_COMB_C31, tbl_entry->regval[8],
++ CM_COMB_C32, tbl_entry->regval[9]);
++
++ REG_SET_2(CM_COMB_C33_C34, 0,
++ CM_COMB_C33, tbl_entry->regval[10],
++ CM_COMB_C34, tbl_entry->regval[11]);
++ }
++}
++
++static void oppn10_set_output_csc_adjustment(
++ struct transform *xfm_base,
++ const struct out_csc_color_matrix *tbl_entry)
++{
++ struct dcn10_dpp *xfm = TO_DCN10_DPP(xfm_base);
++ //enum csc_color_mode config = CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC;
++ uint32_t ocsc_mode = 4;
++
++ /**
++ *if (tbl_entry != NULL) {
++ * switch (tbl_entry->color_space) {
++ * case COLOR_SPACE_SRGB:
++ * case COLOR_SPACE_2020_RGB_FULLRANGE:
++ * ocsc_mode = 0;
++ * break;
++ * case COLOR_SPACE_SRGB_LIMITED:
++ * case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
++ * ocsc_mode = 1;
++ * break;
++ * case COLOR_SPACE_YCBCR601:
++ * case COLOR_SPACE_YCBCR601_LIMITED:
++ * ocsc_mode = 2;
++ * break;
++ * case COLOR_SPACE_YCBCR709:
++ * case COLOR_SPACE_YCBCR709_LIMITED:
++ * case COLOR_SPACE_2020_YCBCR:
++ * ocsc_mode = 3;
++ * break;
++ * case COLOR_SPACE_UNKNOWN:
++ * default:
++ * break;
++ * }
++ *}
++ */
++
++ REG_SET(CM_OCSC_CONTROL, 0, CM_OCSC_MODE, ocsc_mode);
++ oppn10_program_color_matrix(xfm, tbl_entry);
++}
++
+ static struct transform_funcs dcn10_dpp_funcs = {
+ .transform_reset = dpp_reset,
+ .transform_set_scaler = dpp_set_scaler_manual_scale,
+ .transform_get_optimal_number_of_taps = dpp_get_optimal_number_of_taps,
+ .transform_set_gamut_remap = dcn_dpp_set_gamut_remap,
++ .opp_set_csc_adjustment = oppn10_set_output_csc_adjustment,
++ .opp_set_csc_default = oppn10_set_output_csc_default,
+ };
+
+ /*****************************************/
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
+index c1124e9..693060e 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
+@@ -86,7 +86,14 @@
+ SRI(CM_COMB_C21_C22, CM, id),\
+ SRI(CM_COMB_C23_C24, CM, id),\
+ SRI(CM_COMB_C31_C32, CM, id),\
+- SRI(CM_COMB_C33_C34, CM, id)
++ SRI(CM_COMB_C33_C34, CM, id),\
++ SRI(CM_OCSC_CONTROL, CM, id), \
++ SRI(CM_OCSC_C11_C12, CM, id), \
++ SRI(CM_OCSC_C13_C14, CM, id), \
++ SRI(CM_OCSC_C21_C22, CM, id), \
++ SRI(CM_OCSC_C23_C24, CM, id), \
++ SRI(CM_OCSC_C31_C32, CM, id), \
++ SRI(CM_OCSC_C33_C34, CM, id)
+
+ #define TF_REG_LIST_SH_MASK_DCN(mask_sh)\
+ TF_SF(CM0_CM_GAMUT_REMAP_CONTROL, CM_GAMUT_REMAP_MODE, mask_sh),\
+@@ -194,7 +201,20 @@
+ TF_SF(CM0_CM_COMB_C31_C32, CM_COMB_C31, mask_sh),\
+ TF_SF(CM0_CM_COMB_C33_C34, CM_COMB_C33, mask_sh),\
+ TF_SF(CM0_CM_COMB_C31_C32, CM_COMB_C32, mask_sh),\
+- TF_SF(CM0_CM_COMB_C33_C34, CM_COMB_C34, mask_sh)
++ TF_SF(CM0_CM_COMB_C33_C34, CM_COMB_C34, mask_sh),\
++ TF_SF(CM0_CM_OCSC_CONTROL, CM_OCSC_MODE, mask_sh), \
++ TF_SF(CM0_CM_OCSC_C11_C12, CM_OCSC_C11, mask_sh), \
++ TF_SF(CM0_CM_OCSC_C11_C12, CM_OCSC_C12, mask_sh), \
++ TF_SF(CM0_CM_OCSC_C13_C14, CM_OCSC_C13, mask_sh), \
++ TF_SF(CM0_CM_OCSC_C13_C14, CM_OCSC_C14, mask_sh), \
++ TF_SF(CM0_CM_OCSC_C21_C22, CM_OCSC_C21, mask_sh), \
++ TF_SF(CM0_CM_OCSC_C21_C22, CM_OCSC_C22, mask_sh), \
++ TF_SF(CM0_CM_OCSC_C23_C24, CM_OCSC_C23, mask_sh), \
++ TF_SF(CM0_CM_OCSC_C23_C24, CM_OCSC_C24, mask_sh), \
++ TF_SF(CM0_CM_OCSC_C31_C32, CM_OCSC_C31, mask_sh), \
++ TF_SF(CM0_CM_OCSC_C31_C32, CM_OCSC_C32, mask_sh), \
++ TF_SF(CM0_CM_OCSC_C33_C34, CM_OCSC_C33, mask_sh), \
++ TF_SF(CM0_CM_OCSC_C33_C34, CM_OCSC_C34, mask_sh)
+
+
+ #define TF_REG_FIELD_LIST(type) \
+@@ -300,7 +320,20 @@
+ type CM_COMB_C31; \
+ type CM_COMB_C32; \
+ type CM_COMB_C33; \
+- type CM_COMB_C34
++ type CM_COMB_C34; \
++ type CM_OCSC_MODE; \
++ type CM_OCSC_C11; \
++ type CM_OCSC_C12; \
++ type CM_OCSC_C13; \
++ type CM_OCSC_C14; \
++ type CM_OCSC_C21; \
++ type CM_OCSC_C22; \
++ type CM_OCSC_C23; \
++ type CM_OCSC_C24; \
++ type CM_OCSC_C31; \
++ type CM_OCSC_C32; \
++ type CM_OCSC_C33; \
++ type CM_OCSC_C34
+
+ struct dcn_dpp_shift {
+ TF_REG_FIELD_LIST(uint8_t);
+@@ -357,6 +390,13 @@ struct dcn_dpp_registers {
+ uint32_t CM_COMB_C23_C24;
+ uint32_t CM_COMB_C31_C32;
+ uint32_t CM_COMB_C33_C34;
++ uint32_t CM_OCSC_CONTROL;
++ uint32_t CM_OCSC_C11_C12;
++ uint32_t CM_OCSC_C13_C14;
++ uint32_t CM_OCSC_C21_C22;
++ uint32_t CM_OCSC_C23_C24;
++ uint32_t CM_OCSC_C31_C32;
++ uint32_t CM_OCSC_C33_C34;
+ };
+
+ struct dcn10_dpp {
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+index 633d858..4cbca15 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+@@ -1588,7 +1588,7 @@ static void update_dchubp_dpp(
+
+ /*TODO add adjustments parameters*/
+ ocsc.out_color_space = pipe_ctx->stream->public.output_color_space;
+- pipe_ctx->opp->funcs->opp_set_csc_default(pipe_ctx->opp, &ocsc);
++ pipe_ctx->xfm->funcs->opp_set_csc_default(pipe_ctx->xfm, &ocsc);
+
+ mi->funcs->mem_input_program_surface_config(
+ mi,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
+index c2aa69d..5cf985e 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
+@@ -327,42 +327,7 @@ static void oppn10_program_fmt(
+ return;
+ }
+
+-static void oppn10_set_output_csc_default(
+- struct output_pixel_processor *opp,
+- const struct default_adjustment *default_adjust)
+-{
+
+- struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp);
+- uint32_t ocsc_mode = 0;
+-
+- if (default_adjust != NULL) {
+- switch (default_adjust->out_color_space) {
+- case COLOR_SPACE_SRGB:
+- case COLOR_SPACE_2020_RGB_FULLRANGE:
+- ocsc_mode = 0;
+- break;
+- case COLOR_SPACE_SRGB_LIMITED:
+- case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
+- ocsc_mode = 1;
+- break;
+- case COLOR_SPACE_YCBCR601:
+- case COLOR_SPACE_YCBCR601_LIMITED:
+- ocsc_mode = 2;
+- break;
+- case COLOR_SPACE_YCBCR709:
+- case COLOR_SPACE_YCBCR709_LIMITED:
+- case COLOR_SPACE_2020_YCBCR:
+- ocsc_mode = 3;
+- break;
+- case COLOR_SPACE_UNKNOWN:
+- default:
+- break;
+- }
+- }
+-
+- REG_SET(CM_OCSC_CONTROL, 0, CM_OCSC_MODE, ocsc_mode);
+-
+-}
+ /*program re gamma RAM B*/
+ static void opp_program_regamma_lutb_settings(
+ struct output_pixel_processor *opp,
+@@ -714,117 +679,7 @@ static void oppn10_power_on_regamma_lut(
+ }
+
+
+-static void oppn10_program_color_matrix(struct dcn10_opp *oppn10,
+- const struct out_csc_color_matrix *tbl_entry)
+-{
+- uint32_t mode;
+-
+- REG_GET(CM_OCSC_CONTROL, CM_OCSC_MODE, &mode);
+-
+- if (tbl_entry == NULL) {
+- BREAK_TO_DEBUGGER();
+- return;
+- }
+-
+-
+- if (mode == 4) {
+- /*R*/
+- REG_SET_2(CM_OCSC_C11_C12, 0,
+- CM_OCSC_C11, tbl_entry->regval[0],
+- CM_OCSC_C12, tbl_entry->regval[1]);
+-
+- REG_SET_2(CM_OCSC_C13_C14, 0,
+- CM_OCSC_C13, tbl_entry->regval[2],
+- CM_OCSC_C14, tbl_entry->regval[3]);
+
+- /*G*/
+- REG_SET_2(CM_OCSC_C21_C22, 0,
+- CM_OCSC_C21, tbl_entry->regval[4],
+- CM_OCSC_C22, tbl_entry->regval[5]);
+-
+- REG_SET_2(CM_OCSC_C23_C24, 0,
+- CM_OCSC_C23, tbl_entry->regval[6],
+- CM_OCSC_C24, tbl_entry->regval[7]);
+-
+- /*B*/
+- REG_SET_2(CM_OCSC_C31_C32, 0,
+- CM_OCSC_C31, tbl_entry->regval[8],
+- CM_OCSC_C32, tbl_entry->regval[9]);
+-
+- REG_SET_2(CM_OCSC_C33_C34, 0,
+- CM_OCSC_C33, tbl_entry->regval[10],
+- CM_OCSC_C34, tbl_entry->regval[11]);
+- } else {
+- /*R*/
+- REG_SET_2(CM_COMB_C11_C12, 0,
+- CM_COMB_C11, tbl_entry->regval[0],
+- CM_COMB_C12, tbl_entry->regval[1]);
+-
+- REG_SET_2(CM_COMB_C13_C14, 0,
+- CM_COMB_C13, tbl_entry->regval[2],
+- CM_COMB_C14, tbl_entry->regval[3]);
+-
+- /*G*/
+- REG_SET_2(CM_COMB_C21_C22, 0,
+- CM_COMB_C21, tbl_entry->regval[4],
+- CM_COMB_C22, tbl_entry->regval[5]);
+-
+- REG_SET_2(CM_COMB_C23_C24, 0,
+- CM_COMB_C23, tbl_entry->regval[6],
+- CM_COMB_C24, tbl_entry->regval[7]);
+-
+- /*B*/
+- REG_SET_2(CM_COMB_C31_C32, 0,
+- CM_COMB_C31, tbl_entry->regval[8],
+- CM_COMB_C32, tbl_entry->regval[9]);
+-
+- REG_SET_2(CM_COMB_C33_C34, 0,
+- CM_COMB_C33, tbl_entry->regval[10],
+- CM_COMB_C34, tbl_entry->regval[11]);
+- }
+-}
+-
+-static void oppn10_set_output_csc_adjustment(
+- struct output_pixel_processor *opp,
+- const struct out_csc_color_matrix *tbl_entry)
+-{
+-
+- struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp);
+- //enum csc_color_mode config = CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC;
+-
+-
+- uint32_t ocsc_mode = 4;
+-
+- /**
+- *if (tbl_entry != NULL) {
+- * switch (tbl_entry->color_space) {
+- * case COLOR_SPACE_SRGB:
+- * case COLOR_SPACE_2020_RGB_FULLRANGE:
+- * ocsc_mode = 0;
+- * break;
+- * case COLOR_SPACE_SRGB_LIMITED:
+- * case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
+- * ocsc_mode = 1;
+- * break;
+- * case COLOR_SPACE_YCBCR601:
+- * case COLOR_SPACE_YCBCR601_LIMITED:
+- * ocsc_mode = 2;
+- * break;
+- * case COLOR_SPACE_YCBCR709:
+- * case COLOR_SPACE_YCBCR709_LIMITED:
+- * case COLOR_SPACE_2020_YCBCR:
+- * ocsc_mode = 3;
+- * break;
+- * case COLOR_SPACE_UNKNOWN:
+- * default:
+- * break;
+- * }
+- *}
+- */
+-
+- REG_SET(CM_OCSC_CONTROL, 0, CM_OCSC_MODE, ocsc_mode);
+- oppn10_program_color_matrix(oppn10, tbl_entry);
+-}
+
+ static void opp_program_regamma_lut(
+ struct output_pixel_processor *opp,
+@@ -889,8 +744,6 @@ static void dcn10_opp_destroy(struct output_pixel_processor **opp)
+
+ static struct opp_funcs dcn10_opp_funcs = {
+ .opp_power_on_regamma_lut = oppn10_power_on_regamma_lut,
+- .opp_set_csc_adjustment = oppn10_set_output_csc_adjustment,
+- .opp_set_csc_default = oppn10_set_output_csc_default,
+ .opp_set_dyn_expansion = oppn10_set_dyn_expansion,
+ .opp_program_regamma_pwl = oppn10_set_regamma_pwl,
+ .opp_set_regamma_mode = oppn10_set_regamma_mode,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h
+index d9d66a4..900298d 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h
+@@ -46,21 +46,8 @@
+
+ #define OPP_REG_LIST_DCN10(id) \
+ OPP_REG_LIST_DCN(id), \
+- SRI(CM_OCSC_C11_C12, CM, id), \
+- SRI(CM_OCSC_C13_C14, CM, id), \
+- SRI(CM_OCSC_C21_C22, CM, id), \
+- SRI(CM_OCSC_C23_C24, CM, id), \
+- SRI(CM_OCSC_C31_C32, CM, id), \
+- SRI(CM_OCSC_C33_C34, CM, id), \
+- SRI(CM_COMB_C11_C12, CM, id), \
+- SRI(CM_COMB_C13_C14, CM, id), \
+- SRI(CM_COMB_C21_C22, CM, id), \
+- SRI(CM_COMB_C23_C24, CM, id), \
+- SRI(CM_COMB_C31_C32, CM, id), \
+- SRI(CM_COMB_C33_C34, CM, id), \
+ SRI(CM_RGAM_LUT_WRITE_EN_MASK, CM, id), \
+ SRI(CM_RGAM_CONTROL, CM, id), \
+- SRI(CM_OCSC_CONTROL, CM, id), \
+ SRI(CM_RGAM_RAMB_START_CNTL_B, CM, id), \
+ SRI(CM_RGAM_RAMB_START_CNTL_G, CM, id), \
+ SRI(CM_RGAM_RAMB_START_CNTL_R, CM, id), \
+@@ -151,32 +138,7 @@
+ #define OPP_MASK_SH_LIST_DCN10(mask_sh) \
+ OPP_MASK_SH_LIST_DCN(mask_sh), \
+ OPP_SF(DSCL0_OBUF_CONTROL, OBUF_H_2X_UPSCALE_EN, mask_sh), \
+- OPP_SF(CM0_CM_OCSC_C11_C12, CM_OCSC_C11, mask_sh), \
+- OPP_SF(CM0_CM_OCSC_C11_C12, CM_OCSC_C12, mask_sh), \
+- OPP_SF(CM0_CM_OCSC_C13_C14, CM_OCSC_C13, mask_sh), \
+- OPP_SF(CM0_CM_OCSC_C13_C14, CM_OCSC_C14, mask_sh), \
+- OPP_SF(CM0_CM_OCSC_C21_C22, CM_OCSC_C21, mask_sh), \
+- OPP_SF(CM0_CM_OCSC_C21_C22, CM_OCSC_C22, mask_sh), \
+- OPP_SF(CM0_CM_OCSC_C23_C24, CM_OCSC_C23, mask_sh), \
+- OPP_SF(CM0_CM_OCSC_C23_C24, CM_OCSC_C24, mask_sh), \
+- OPP_SF(CM0_CM_OCSC_C31_C32, CM_OCSC_C31, mask_sh), \
+- OPP_SF(CM0_CM_OCSC_C31_C32, CM_OCSC_C32, mask_sh), \
+- OPP_SF(CM0_CM_OCSC_C33_C34, CM_OCSC_C33, mask_sh), \
+- OPP_SF(CM0_CM_OCSC_C33_C34, CM_OCSC_C34, mask_sh), \
+- OPP_SF(CM0_CM_COMB_C11_C12, CM_COMB_C11, mask_sh), \
+- OPP_SF(CM0_CM_COMB_C11_C12, CM_COMB_C12, mask_sh), \
+- OPP_SF(CM0_CM_COMB_C13_C14, CM_COMB_C13, mask_sh), \
+- OPP_SF(CM0_CM_COMB_C13_C14, CM_COMB_C14, mask_sh), \
+- OPP_SF(CM0_CM_COMB_C21_C22, CM_COMB_C21, mask_sh), \
+- OPP_SF(CM0_CM_COMB_C21_C22, CM_COMB_C22, mask_sh), \
+- OPP_SF(CM0_CM_COMB_C23_C24, CM_COMB_C23, mask_sh), \
+- OPP_SF(CM0_CM_COMB_C23_C24, CM_COMB_C24, mask_sh), \
+- OPP_SF(CM0_CM_COMB_C31_C32, CM_COMB_C31, mask_sh), \
+- OPP_SF(CM0_CM_COMB_C31_C32, CM_COMB_C32, mask_sh), \
+- OPP_SF(CM0_CM_COMB_C33_C34, CM_COMB_C33, mask_sh), \
+- OPP_SF(CM0_CM_COMB_C33_C34, CM_COMB_C34, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_CONTROL, CM_RGAM_LUT_MODE, mask_sh), \
+- OPP_SF(CM0_CM_OCSC_CONTROL, CM_OCSC_MODE, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_START_CNTL_B, CM_RGAM_RAMB_EXP_REGION_START_B, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_START_CNTL_B, CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_START_CNTL_G, CM_RGAM_RAMB_EXP_REGION_START_G, mask_sh), \
+@@ -414,7 +376,6 @@
+ type FMT_DYNAMIC_EXP_EN; \
+ type FMT_DYNAMIC_EXP_MODE; \
+ type FMT_MAP420MEM_PWR_FORCE; \
+- type CM_OCSC_MODE; \
+ type CM_RGAM_RAMB_EXP_REGION_START_B; \
+ type CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B; \
+ type CM_RGAM_RAMB_EXP_REGION_START_G; \
+@@ -630,7 +591,6 @@ struct dcn10_opp_registers {
+ uint32_t FMT_CLAMP_CNTL;
+ uint32_t FMT_DYNAMIC_EXP_CNTL;
+ uint32_t FMT_MAP420_MEMORY_CONTROL;
+- uint32_t CM_OCSC_CONTROL;
+ uint32_t CM_RGAM_RAMB_START_CNTL_B;
+ uint32_t CM_RGAM_RAMB_START_CNTL_G;
+ uint32_t CM_RGAM_RAMB_START_CNTL_R;
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h
+index 0212618..137b4c8 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h
+@@ -28,6 +28,7 @@
+
+ #include "os_types.h"
+ #include "fixed31_32.h"
++#include "dc_hw_types.h"
+
+ /******************************************************************************
+ * Data types shared between different Virtual HW blocks
+@@ -76,4 +77,40 @@ struct pwl_params {
+ struct pwl_result_data rgb_resulted[256 + 3];
+ uint32_t hw_points_num;
+ };
++
++/* move to dpp
++ * while we are moving functionality out of opp to dpp to align
++ * HW programming to HW IP, we define these struct in hw_shared
++ * so we can still compile while refactoring
++ */
++
++enum lb_pixel_depth {
++ /* do not change the values because it is used as bit vector */
++ LB_PIXEL_DEPTH_18BPP = 1,
++ LB_PIXEL_DEPTH_24BPP = 2,
++ LB_PIXEL_DEPTH_30BPP = 4,
++ LB_PIXEL_DEPTH_36BPP = 8
++};
++
++enum graphics_csc_adjust_type {
++ GRAPHICS_CSC_ADJUST_TYPE_BYPASS = 0,
++ GRAPHICS_CSC_ADJUST_TYPE_HW, /* without adjustments */
++ GRAPHICS_CSC_ADJUST_TYPE_SW /*use adjustments */
++};
++
++struct default_adjustment {
++ enum lb_pixel_depth lb_color_depth;
++ enum dc_color_space out_color_space;
++ enum dc_color_space in_color_space;
++ enum dc_color_depth color_depth;
++ enum pixel_format surface_pixel_format;
++ enum graphics_csc_adjust_type csc_adjust_type;
++ bool force_hw_default;
++};
++
++struct out_csc_color_matrix {
++ enum dc_color_space color_space;
++ uint16_t regval[12];
++};
++
+ #endif /* __DAL_HW_SHARED_H__ */
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
+index 57bdd6c..ef36ffd 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
+@@ -217,22 +217,6 @@ enum fmt_stereo_action {
+ FMT_STEREO_ACTION_UPDATE_POLARITY
+ };
+
+-enum graphics_csc_adjust_type {
+- GRAPHICS_CSC_ADJUST_TYPE_BYPASS = 0,
+- GRAPHICS_CSC_ADJUST_TYPE_HW, /* without adjustments */
+- GRAPHICS_CSC_ADJUST_TYPE_SW /*use adjustments */
+-};
+-
+-struct default_adjustment {
+- enum lb_pixel_depth lb_color_depth;
+- enum dc_color_space out_color_space;
+- enum dc_color_space in_color_space;
+- enum dc_color_depth color_depth;
+- enum pixel_format surface_pixel_format;
+- enum graphics_csc_adjust_type csc_adjust_type;
+- bool force_hw_default;
+-};
+-
+ enum grph_color_adjust_option {
+ GRPH_COLOR_MATRIX_HW_DEFAULT = 1,
+ GRPH_COLOR_MATRIX_SW
+@@ -250,11 +234,6 @@ struct opp_grph_csc_adjustment {
+ int32_t grph_hue;
+ };
+
+-struct out_csc_color_matrix {
+- enum dc_color_space color_space;
+- uint16_t regval[12];
+-};
+-
+ /* Underlay related types */
+
+ struct hw_adjustment_range {
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h b/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h
+index b4862c3..132c5db 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h
+@@ -26,6 +26,7 @@
+ #ifndef __DAL_TRANSFORM_H__
+ #define __DAL_TRANSFORM_H__
+
++#include "hw_shared.h"
+ #include "dc_hw_types.h"
+ #include "fixed31_32.h"
+
+@@ -112,14 +113,6 @@ struct xfm_grph_csc_adjustment {
+ enum graphics_gamut_adjust_type gamut_adjust_type;
+ };
+
+-enum lb_pixel_depth {
+- /* do not change the values because it is used as bit vector */
+- LB_PIXEL_DEPTH_18BPP = 1,
+- LB_PIXEL_DEPTH_24BPP = 2,
+- LB_PIXEL_DEPTH_30BPP = 4,
+- LB_PIXEL_DEPTH_36BPP = 8
+-};
+-
+ struct overscan_info {
+ int left;
+ int right;
+@@ -176,11 +169,6 @@ struct transform_funcs {
+ void (*transform_set_scaler)(struct transform *xfm,
+ const struct scaler_data *scl_data);
+
+- void (*transform_set_gamut_remap)(
+- struct transform *xfm,
+- const struct xfm_grph_csc_adjustment *adjust);
+-
+-
+ void (*transform_set_pixel_storage_depth)(
+ struct transform *xfm,
+ enum lb_pixel_depth depth,
+@@ -190,6 +178,18 @@ struct transform_funcs {
+ struct transform *xfm,
+ struct scaler_data *scl_data,
+ const struct scaling_taps *in_taps);
++
++ void (*transform_set_gamut_remap)(
++ struct transform *xfm,
++ const struct xfm_grph_csc_adjustment *adjust);
++
++ void (*opp_set_csc_default)(
++ struct transform *xfm,
++ const struct default_adjustment *default_adjust);
++
++ void (*opp_set_csc_adjustment)(
++ struct transform *xfm,
++ const struct out_csc_color_matrix *tbl_entry);
+ };
+
+ extern const uint16_t filter_2tap_16p[18];
+--
+2.7.4
+