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Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/0647-drm-amd-display-support-for-updated-register-headers.patch')
-rw-r--r--common/recipes-kernel/linux/linux-yocto-4.14.71/0647-drm-amd-display-support-for-updated-register-headers.patch316
1 files changed, 0 insertions, 316 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/0647-drm-amd-display-support-for-updated-register-headers.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/0647-drm-amd-display-support-for-updated-register-headers.patch
deleted file mode 100644
index 5df08a1d..00000000
--- a/common/recipes-kernel/linux/linux-yocto-4.14.71/0647-drm-amd-display-support-for-updated-register-headers.patch
+++ /dev/null
@@ -1,316 +0,0 @@
-From 9bfac8a35c4da99bca635030718bfc2588fdb637 Mon Sep 17 00:00:00 2001
-From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Date: Fri, 21 Jul 2017 17:35:16 -0400
-Subject: [PATCH 0647/4131] drm/amd/display: support for updated register
- headers on DCN
-
-Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Acked-by: Harry Wentland <Harry.Wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | 12 +++++++-
- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 2 +-
- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 14 +++++++--
- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c | 17 +++++++---
- .../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c | 19 +++++++++---
- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h | 15 ++++++++-
- .../amd/display/dc/dcn10/dcn10_timing_generator.c | 36 ++++++++++++----------
- drivers/gpu/drm/amd/display/dc/inc/hw/opp.h | 4 +++
- 8 files changed, 88 insertions(+), 31 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
-index 0479554..80ee1ac32 100644
---- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
-+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
-@@ -227,6 +227,15 @@ struct dce_hwseq_registers {
- uint32_t DISPCLK_FREQ_CHANGE_CNTL;
- uint32_t RBBMIF_TIMEOUT_DIS;
- uint32_t RBBMIF_TIMEOUT_DIS_2;
-+ uint32_t DENTIST_DISPCLK_CNTL;
-+ uint32_t DCHUBBUB_CRC_CTRL;
-+ uint32_t DPP_TOP0_DPP_CRC_CTRL;
-+ uint32_t DPP_TOP0_DPP_CRC_VAL_R_G;
-+ uint32_t DPP_TOP0_DPP_CRC_VAL_B_A;
-+ uint32_t MPC_CRC_CTRL;
-+ uint32_t MPC_CRC_RESULT_GB;
-+ uint32_t MPC_CRC_RESULT_C;
-+ uint32_t MPC_CRC_RESULT_AR;
- #endif
- };
- /* set field name */
-@@ -388,7 +397,8 @@ struct dce_hwseq_registers {
- type DOMAIN6_PGFSM_PWR_STATUS; \
- type DOMAIN7_PGFSM_PWR_STATUS; \
- type DCFCLK_GATE_DIS; \
-- type DCHUBBUB_GLOBAL_TIMER_REFDIV;
-+ type DCHUBBUB_GLOBAL_TIMER_REFDIV; \
-+ type DENTIST_DPPCLK_WDIVIDER;
- #endif
-
- struct dce_hwseq_shift {
-diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
-index b691ef9..baafe66 100644
---- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
-@@ -256,7 +256,7 @@ static bool dce110_set_input_transfer_func(
- ipp->funcs->ipp_program_prescale(ipp, &prescale_params);
-
- if (surface->public.gamma_correction && dce_use_lut(surface))
-- ipp->funcs->ipp_program_input_lut(ipp, surface->public.gamma_correction);
-+ ipp->funcs->ipp_program_input_lut(ipp, surface->public.gamma_correction);
-
- if (tf == NULL) {
- /* Default case if no input transfer function specified */
-diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
-index 6db78d9..ce7da88 100644
---- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
-@@ -550,7 +550,9 @@ static void reset_front_end(
- if (dc->public.debug.sanity_checks)
- verify_allow_pstate_change_high(dc->hwseq);
-
-- REG_WAIT(OTG_GLOBAL_SYNC_STATUS[tg->inst], VUPDATE_NO_LOCK_EVENT_OCCURRED, 1, 20000, 200000);
-+ if (tg->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS)
-+ REG_WAIT(OTG_GLOBAL_SYNC_STATUS[tg->inst],
-+ VUPDATE_NO_LOCK_EVENT_OCCURRED, 1, 20000, 200000);
-
- mpcc->funcs->wait_for_idle(mpcc);
-
-@@ -1295,6 +1297,7 @@ static void dcn10_power_on_fe(
- /* make sure OPP_PIPE_CLOCK_EN = 1 */
- REG_UPDATE(OPP_PIPE_CONTROL[pipe_ctx->tg->inst],
- OPP_PIPE_CLOCK_EN, 1);
-+ /*TODO: REG_UPDATE(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_WDIVIDER, 0x1f);*/
-
- if (dc_surface) {
- dm_logger_write(dc->ctx->logger, LOG_DC,
-@@ -1984,9 +1987,16 @@ static void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct core_dc *dc)
- static void dcn10_log_hw_state(struct core_dc *dc)
- {
- struct dc_context *dc_ctx = dc->ctx;
-+ struct dce_hwseq *hws = dc->hwseq;
-
- DTN_INFO("%s: Hello World", __func__);
-
-+ if (REG(MPC_CRC_RESULT_GB))
-+ DTN_INFO("MPC_CRC_RESULT_GB:%d MPC_CRC_RESULT_C:%d MPC_CRC_RESULT_AR:%d\n",
-+ REG_READ(MPC_CRC_RESULT_GB), REG_READ(MPC_CRC_RESULT_C), REG_READ(MPC_CRC_RESULT_AR));
-+ if (REG(DPP_TOP0_DPP_CRC_VAL_B_A))
-+ DTN_INFO("DPP_TOP0_DPP_CRC_VAL_B_A:%d DPP_TOP0_DPP_CRC_VAL_R_G:%d\n",
-+ REG_READ(DPP_TOP0_DPP_CRC_VAL_B_A), REG_READ(DPP_TOP0_DPP_CRC_VAL_R_G));
- /* todo: add meaningful register reads and print out HW state
- *
- */
-@@ -2065,7 +2075,7 @@ static const struct hw_sequencer_funcs dcn10_funcs = {
- .set_static_screen_control = set_static_screen_control,
- .setup_stereo = dcn10_setup_stereo,
- .set_avmute = dce110_set_avmute,
-- .log_hw_state = dcn10_log_hw_state,
-+ .log_hw_state = dcn10_log_hw_state
- };
-
-
-diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c
-index 53dd9a9..ee12f67 100644
---- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c
-+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c
-@@ -472,11 +472,18 @@ static bool ippn10_cursor_program_control(
- bool pixel_data_invert,
- enum dc_cursor_color_format color_format)
- {
-- REG_SET_2(CURSOR_SETTINS, 0,
-- /* no shift of the cursor HDL schedule */
-- CURSOR0_DST_Y_OFFSET, 0,
-- /* used to shift the cursor chunk request deadline */
-- CURSOR0_CHUNK_HDL_ADJUST, 3);
-+ if (REG(CURSOR_SETTINS))
-+ REG_SET_2(CURSOR_SETTINS, 0,
-+ /* no shift of the cursor HDL schedule */
-+ CURSOR0_DST_Y_OFFSET, 0,
-+ /* used to shift the cursor chunk request deadline */
-+ CURSOR0_CHUNK_HDL_ADJUST, 3);
-+ else
-+ REG_SET_2(CURSOR_SETTINGS, 0,
-+ /* no shift of the cursor HDL schedule */
-+ CURSOR0_DST_Y_OFFSET, 0,
-+ /* used to shift the cursor chunk request deadline */
-+ CURSOR0_CHUNK_HDL_ADJUST, 3);
-
- REG_UPDATE_2(CURSOR0_CONTROL,
- CUR0_MODE, color_format,
-diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c
-index 8054794..1f86295 100644
---- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c
-+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c
-@@ -460,9 +460,14 @@ static void min10_program_deadline(
- REFCYC_X_AFTER_SCALER, dlg_attr->refcyc_x_after_scaler,
- DST_Y_AFTER_SCALER, dlg_attr->dst_y_after_scaler);
-
-- REG_SET_2(PREFETCH_SETTINS, 0,
-- DST_Y_PREFETCH, dlg_attr->dst_y_prefetch,
-- VRATIO_PREFETCH, dlg_attr->vratio_prefetch);
-+ if (REG(PREFETCH_SETTINS))
-+ REG_SET_2(PREFETCH_SETTINS, 0,
-+ DST_Y_PREFETCH, dlg_attr->dst_y_prefetch,
-+ VRATIO_PREFETCH, dlg_attr->vratio_prefetch);
-+ else
-+ REG_SET_2(PREFETCH_SETTINGS, 0,
-+ DST_Y_PREFETCH, dlg_attr->dst_y_prefetch,
-+ VRATIO_PREFETCH, dlg_attr->vratio_prefetch);
-
- REG_SET_2(VBLANK_PARAMETERS_0, 0,
- DST_Y_PER_VM_VBLANK, dlg_attr->dst_y_per_vm_vblank,
-@@ -498,8 +503,12 @@ static void min10_program_deadline(
- REFCYC_PER_LINE_DELIVERY_L, dlg_attr->refcyc_per_line_delivery_l,
- REFCYC_PER_LINE_DELIVERY_C, dlg_attr->refcyc_per_line_delivery_c);
-
-- REG_SET(PREFETCH_SETTINS_C, 0,
-- VRATIO_PREFETCH_C, dlg_attr->vratio_prefetch_c);
-+ if (REG(PREFETCH_SETTINS_C))
-+ REG_SET(PREFETCH_SETTINS_C, 0,
-+ VRATIO_PREFETCH_C, dlg_attr->vratio_prefetch_c);
-+ else
-+ REG_SET(PREFETCH_SETTINGS_C, 0,
-+ VRATIO_PREFETCH_C, dlg_attr->vratio_prefetch_c);
-
- REG_SET(VBLANK_PARAMETERS_2, 0,
- REFCYC_PER_PTE_GROUP_VBLANK_C, dlg_attr->refcyc_per_pte_group_vblank_c);
-diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h
-index de0b631..d9d66a4 100644
---- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h
-+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h
-@@ -123,7 +123,6 @@
- SRI(CM_MEM_PWR_CTRL, CM, id), \
- SRI(CM_RGAM_LUT_DATA, CM, id)
-
--
- #define OPP_MASK_SH_LIST_DCN(mask_sh) \
- OPP_SF(DSCL0_OBUF_CONTROL, OBUF_BYPASS, mask_sh), \
- OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, mask_sh), \
-@@ -357,6 +356,16 @@
- OPP_SF(CM0_CM_RGAM_LUT_DATA, CM_RGAM_LUT_DATA, mask_sh)
-
- #define OPP_DCN10_REG_FIELD_LIST(type) \
-+ type DPG_EN; \
-+ type DPG_MODE; \
-+ type DPG_VRES; \
-+ type DPG_HRES; \
-+ type DPG_COLOUR0_R_CR; \
-+ type DPG_COLOUR1_R_CR; \
-+ type DPG_COLOUR0_B_CB; \
-+ type DPG_COLOUR1_B_CB; \
-+ type DPG_COLOUR0_G_Y; \
-+ type DPG_COLOUR1_G_Y; \
- type CM_OCSC_C11; \
- type CM_OCSC_C12; \
- type CM_OCSC_C13; \
-@@ -594,6 +603,10 @@ struct dcn10_opp_mask {
- };
-
- struct dcn10_opp_registers {
-+ uint32_t DPG_CONTROL;
-+ uint32_t DPG_COLOUR_B_CB;
-+ uint32_t DPG_COLOUR_G_Y;
-+ uint32_t DPG_COLOUR_R_CR;
- uint32_t CM_OCSC_C11_C12;
- uint32_t CM_OCSC_C13_C14;
- uint32_t CM_OCSC_C21_C22;
-diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
-index 12d7f35..b2e796d 100644
---- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
-+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
-@@ -345,17 +345,18 @@ static void tgn10_enable_optc_clock(struct timing_generator *tg, bool enable)
- struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
-
- if (enable) {
-- REG_UPDATE(OPTC_INPUT_CLOCK_CONTROL,
-- OPTC_INPUT_CLK_EN, 1);
-+ REG_UPDATE_2(OPTC_INPUT_CLOCK_CONTROL,
-+ OPTC_INPUT_CLK_EN, 1,
-+ OPTC_INPUT_CLK_GATE_DIS, 1);
-
- REG_WAIT(OPTC_INPUT_CLOCK_CONTROL,
- OPTC_INPUT_CLK_ON, 1,
- 2000, 500);
-
- /* Enable clock */
-- REG_UPDATE(OTG_CLOCK_CONTROL,
-- OTG_CLOCK_EN, 1);
--
-+ REG_UPDATE_2(OTG_CLOCK_CONTROL,
-+ OTG_CLOCK_EN, 1,
-+ OTG_CLOCK_GATE_DIS, 1);
- REG_WAIT(OTG_CLOCK_CONTROL,
- OTG_CLOCK_ON, 1,
- 2000, 500);
-@@ -364,17 +365,19 @@ static void tgn10_enable_optc_clock(struct timing_generator *tg, bool enable)
- OTG_CLOCK_GATE_DIS, 0,
- OTG_CLOCK_EN, 0);
-
-- REG_WAIT(OTG_CLOCK_CONTROL,
-- OTG_CLOCK_ON, 0,
-- 2000, 500);
-+ if (tg->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS)
-+ REG_WAIT(OTG_CLOCK_CONTROL,
-+ OTG_CLOCK_ON, 0,
-+ 2000, 500);
-
- REG_UPDATE_2(OPTC_INPUT_CLOCK_CONTROL,
- OPTC_INPUT_CLK_GATE_DIS, 0,
- OPTC_INPUT_CLK_EN, 0);
-
-- REG_WAIT(OPTC_INPUT_CLOCK_CONTROL,
-- OPTC_INPUT_CLK_ON, 0,
-- 2000, 500);
-+ if (tg->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS)
-+ REG_WAIT(OPTC_INPUT_CLOCK_CONTROL,
-+ OPTC_INPUT_CLK_ON, 0,
-+ 2000, 500);
- }
- }
-
-@@ -574,9 +577,10 @@ static void tgn10_lock(struct timing_generator *tg)
- REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
- OTG_MASTER_UPDATE_LOCK, 1);
-
-- REG_WAIT(OTG_MASTER_UPDATE_LOCK,
-- UPDATE_LOCK_STATUS, 1,
-- 1, 100);
-+ if (tg->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS)
-+ REG_WAIT(OTG_MASTER_UPDATE_LOCK,
-+ UPDATE_LOCK_STATUS, 1,
-+ 1, 100);
- }
-
- static void tgn10_unlock(struct timing_generator *tg)
-@@ -587,9 +591,9 @@ static void tgn10_unlock(struct timing_generator *tg)
- OTG_MASTER_UPDATE_LOCK, 0);
-
- /* why are we waiting here? */
-- /*REG_WAIT(OTG_DOUBLE_BUFFER_CONTROL,
-+ REG_WAIT(OTG_DOUBLE_BUFFER_CONTROL,
- OTG_UPDATE_PENDING, 0,
-- 20000, 200000);*/
-+ 20000, 200000);
- }
-
- static void tgn10_get_position(struct timing_generator *tg,
-diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
-index a101f4b..4b0c28e 100644
---- a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
-+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
-@@ -324,6 +324,10 @@ struct opp_funcs {
- struct output_pixel_processor *opp,
- bool enable,
- bool rightEyePolarity);
-+
-+ void (*opp_set_test_pattern)(
-+ struct output_pixel_processor *opp,
-+ bool enable);
- };
-
- #endif
---
-2.7.4
-