diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/0633-drm-amd-Add-missing-SURFACE_TMZ-register-shift-mask.patch')
-rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.14.71/0633-drm-amd-Add-missing-SURFACE_TMZ-register-shift-mask.patch | 34 |
1 files changed, 0 insertions, 34 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/0633-drm-amd-Add-missing-SURFACE_TMZ-register-shift-mask.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/0633-drm-amd-Add-missing-SURFACE_TMZ-register-shift-mask.patch deleted file mode 100644 index 41a5d82a..00000000 --- a/common/recipes-kernel/linux/linux-yocto-4.14.71/0633-drm-amd-Add-missing-SURFACE_TMZ-register-shift-mask.patch +++ /dev/null @@ -1,34 +0,0 @@ -From fd09a3eea29aee2479bca9fde2e2f6dab0e237c3 Mon Sep 17 00:00:00 2001 -From: Harry Wentland <harry.wentland@amd.com> -Date: Fri, 4 Aug 2017 16:20:10 -0400 -Subject: [PATCH 0633/4131] drm/amd: Add missing SURFACE_TMZ register - shift/mask - -Signed-off-by: Harry Wentland <harry.wentland@amd.com> -Signed-off-by: Alex Deucher <alexander.deucher@amd.com> ---- - drivers/gpu/drm/amd/include/asic_reg/raven1/DCN/dcn_1_0_sh_mask.h | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/DCN/dcn_1_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/raven1/DCN/dcn_1_0_sh_mask.h -index ecbe5bf..b28d4b6 100644 ---- a/drivers/gpu/drm/amd/include/asic_reg/raven1/DCN/dcn_1_0_sh_mask.h -+++ b/drivers/gpu/drm/amd/include/asic_reg/raven1/DCN/dcn_1_0_sh_mask.h -@@ -9361,12 +9361,14 @@ - #define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 - #define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL - //HUBPREQ0_DCSURF_SURFACE_CONTROL -+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT 0x0 - #define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT 0x1 - #define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK__SHIFT 0x2 - #define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_C__SHIFT 0x5 - #define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT 0x9 - #define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK__SHIFT 0xa - #define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_C__SHIFT 0xd -+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK 0x00000001L - #define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK 0x00000002L - #define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_MASK 0x00000004L - #define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_C_MASK 0x00000020L --- -2.7.4 - |