diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/0621-drm-amd-display-Move-view-port-registers-and-program.patch')
-rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.14.71/0621-drm-amd-display-Move-view-port-registers-and-program.patch | 304 |
1 files changed, 304 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/0621-drm-amd-display-Move-view-port-registers-and-program.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/0621-drm-amd-display-Move-view-port-registers-and-program.patch new file mode 100644 index 00000000..3254be50 --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/0621-drm-amd-display-Move-view-port-registers-and-program.patch @@ -0,0 +1,304 @@ +From 65ed67e884d0792153b7de0b11c042a93caed3db Mon Sep 17 00:00:00 2001 +From: Vitaly Prosyak <vitaly.prosyak@amd.com> +Date: Thu, 13 Jul 2017 15:42:58 -0500 +Subject: [PATCH 0621/4131] drm/amd/display: Move view port registers and + programming to memory input. + +Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com> +Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> +Acked-by: Harry Wentland <Harry.Wentland@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c | 36 --------------------- + drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h | 36 --------------------- + .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 2 ++ + .../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c | 37 +++++++++++++++++++++- + .../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h | 36 +++++++++++++++++++++ + drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h | 4 +++ + 6 files changed, 78 insertions(+), 73 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c +index 85d3ca3..fff81a1 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c +@@ -452,37 +452,6 @@ static void dpp_set_scl_filter( + } + } + +-static void dpp_set_viewport( +- struct dcn10_dpp *xfm, +- const struct rect *viewport, +- const struct rect *viewport_c) +-{ +- REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 0, +- PRI_VIEWPORT_WIDTH, viewport->width, +- PRI_VIEWPORT_HEIGHT, viewport->height); +- +- REG_SET_2(DCSURF_PRI_VIEWPORT_START, 0, +- PRI_VIEWPORT_X_START, viewport->x, +- PRI_VIEWPORT_Y_START, viewport->y); +- +- /*for stereo*/ +- REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION, 0, +- SEC_VIEWPORT_WIDTH, viewport->width, +- SEC_VIEWPORT_HEIGHT, viewport->height); +- +- REG_SET_2(DCSURF_SEC_VIEWPORT_START, 0, +- SEC_VIEWPORT_X_START, viewport->x, +- SEC_VIEWPORT_Y_START, viewport->y); +- +- /* DC supports NV12 only at the moment */ +- REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION_C, 0, +- PRI_VIEWPORT_WIDTH_C, viewport_c->width, +- PRI_VIEWPORT_HEIGHT_C, viewport_c->height); +- +- REG_SET_2(DCSURF_PRI_VIEWPORT_START_C, 0, +- PRI_VIEWPORT_X_START_C, viewport_c->x, +- PRI_VIEWPORT_Y_START_C, viewport_c->y); +-} + + static int get_lb_depth_bpc(enum lb_pixel_depth depth) + { +@@ -616,8 +585,6 @@ void dpp_set_scaler_auto_scale( + + REG_UPDATE(SCL_MODE, DSCL_MODE, dscl_mode); + +- dpp_set_viewport(xfm, &scl_data->viewport, &scl_data->viewport_c); +- + if (dscl_mode == DSCL_MODE_DSCL_BYPASS) + return; + +@@ -762,9 +729,6 @@ static void dpp_set_scaler_manual_scale( + /* SCL mode */ + REG_UPDATE(SCL_MODE, DSCL_MODE, dscl_mode); + +- /* Viewport */ +- dpp_set_viewport(xfm, &scl_data->viewport, &scl_data->viewport_c); +- + if (dscl_mode == DSCL_MODE_DSCL_BYPASS) + return; + /* LB */ +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h +index 9936435..c1124e9 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h +@@ -59,12 +59,6 @@ + SRI(SCL_COEF_RAM_TAP_SELECT, DSCL, id), \ + SRI(SCL_COEF_RAM_TAP_DATA, DSCL, id), \ + SRI(DSCL_2TAP_CONTROL, DSCL, id), \ +- SRI(DCSURF_PRI_VIEWPORT_DIMENSION, HUBP, id), \ +- SRI(DCSURF_PRI_VIEWPORT_START, HUBP, id), \ +- SRI(DCSURF_SEC_VIEWPORT_DIMENSION, HUBP, id), \ +- SRI(DCSURF_SEC_VIEWPORT_START, HUBP, id), \ +- SRI(DCSURF_PRI_VIEWPORT_DIMENSION_C, HUBP, id), \ +- SRI(DCSURF_PRI_VIEWPORT_START_C, HUBP, id), \ + SRI(MPC_SIZE, DSCL, id), \ + SRI(SCL_HORZ_FILTER_SCALE_RATIO, DSCL, id), \ + SRI(SCL_VERT_FILTER_SCALE_RATIO, DSCL, id), \ +@@ -144,18 +138,6 @@ + TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_V_2TAP_SHARP_EN, mask_sh),\ + TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_V_2TAP_SHARP_FACTOR, mask_sh),\ + TF_SF(DSCL0_SCL_MODE, SCL_COEF_RAM_SELECT, mask_sh),\ +- TF_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH, mask_sh),\ +- TF_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT, mask_sh),\ +- TF_SF(HUBP0_DCSURF_PRI_VIEWPORT_START, PRI_VIEWPORT_X_START, mask_sh),\ +- TF_SF(HUBP0_DCSURF_PRI_VIEWPORT_START, PRI_VIEWPORT_Y_START, mask_sh),\ +- TF_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION, SEC_VIEWPORT_WIDTH, mask_sh),\ +- TF_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION, SEC_VIEWPORT_HEIGHT, mask_sh),\ +- TF_SF(HUBP0_DCSURF_SEC_VIEWPORT_START, SEC_VIEWPORT_X_START, mask_sh),\ +- TF_SF(HUBP0_DCSURF_SEC_VIEWPORT_START, SEC_VIEWPORT_Y_START, mask_sh),\ +- TF_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C, PRI_VIEWPORT_WIDTH_C, mask_sh),\ +- TF_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C, PRI_VIEWPORT_HEIGHT_C, mask_sh),\ +- TF_SF(HUBP0_DCSURF_PRI_VIEWPORT_START_C, PRI_VIEWPORT_X_START_C, mask_sh),\ +- TF_SF(HUBP0_DCSURF_PRI_VIEWPORT_START_C, PRI_VIEWPORT_Y_START_C, mask_sh),\ + TF_SF(DSCL0_SCL_MODE, DSCL_MODE, mask_sh),\ + TF_SF(DSCL0_RECOUT_START, RECOUT_START_X, mask_sh),\ + TF_SF(DSCL0_RECOUT_START, RECOUT_START_Y, mask_sh),\ +@@ -257,18 +239,6 @@ + type SCL_V_2TAP_SHARP_EN; \ + type SCL_V_2TAP_SHARP_FACTOR; \ + type SCL_COEF_RAM_SELECT; \ +- type PRI_VIEWPORT_WIDTH; \ +- type PRI_VIEWPORT_HEIGHT; \ +- type PRI_VIEWPORT_X_START; \ +- type PRI_VIEWPORT_Y_START; \ +- type SEC_VIEWPORT_WIDTH; \ +- type SEC_VIEWPORT_HEIGHT; \ +- type SEC_VIEWPORT_X_START; \ +- type SEC_VIEWPORT_Y_START; \ +- type PRI_VIEWPORT_WIDTH_C; \ +- type PRI_VIEWPORT_HEIGHT_C; \ +- type PRI_VIEWPORT_X_START_C; \ +- type PRI_VIEWPORT_Y_START_C; \ + type DSCL_MODE; \ + type RECOUT_START_X; \ + type RECOUT_START_Y; \ +@@ -355,12 +325,6 @@ struct dcn_dpp_registers { + uint32_t SCL_COEF_RAM_TAP_SELECT; + uint32_t SCL_COEF_RAM_TAP_DATA; + uint32_t DSCL_2TAP_CONTROL; +- uint32_t DCSURF_PRI_VIEWPORT_DIMENSION; +- uint32_t DCSURF_PRI_VIEWPORT_START; +- uint32_t DCSURF_SEC_VIEWPORT_DIMENSION; +- uint32_t DCSURF_SEC_VIEWPORT_START; +- uint32_t DCSURF_PRI_VIEWPORT_DIMENSION_C; +- uint32_t DCSURF_PRI_VIEWPORT_START_C; + uint32_t MPC_SIZE; + uint32_t SCL_HORZ_FILTER_SCALE_RATIO; + uint32_t SCL_VERT_FILTER_SCALE_RATIO; +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +index eca0d53..d714422 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +@@ -1470,6 +1470,8 @@ static void update_dchubp_dpp( + /* scaler configuration */ + pipe_ctx->xfm->funcs->transform_set_scaler( + pipe_ctx->xfm, &pipe_ctx->scl_data); ++ mi->funcs->mem_program_viewport(mi, ++ &pipe_ctx->scl_data.viewport, &pipe_ctx->scl_data.viewport_c); + + /*gamut remap*/ + program_gamut_remap(pipe_ctx); +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c +index 4e723a0..efa02d1 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c +@@ -1057,6 +1057,41 @@ static void min10_program_pte_vm(struct mem_input *mem_input, + SYSTEM_ACCESS_MODE, 3); + } + ++static void min_set_viewport( ++ struct mem_input *mem_input, ++ const struct rect *viewport, ++ const struct rect *viewport_c) ++{ ++ struct dcn10_mem_input *mi = TO_DCN10_MEM_INPUT(mem_input); ++ ++ REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 0, ++ PRI_VIEWPORT_WIDTH, viewport->width, ++ PRI_VIEWPORT_HEIGHT, viewport->height); ++ ++ REG_SET_2(DCSURF_PRI_VIEWPORT_START, 0, ++ PRI_VIEWPORT_X_START, viewport->x, ++ PRI_VIEWPORT_Y_START, viewport->y); ++ ++ /*for stereo*/ ++ REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION, 0, ++ SEC_VIEWPORT_WIDTH, viewport->width, ++ SEC_VIEWPORT_HEIGHT, viewport->height); ++ ++ REG_SET_2(DCSURF_SEC_VIEWPORT_START, 0, ++ SEC_VIEWPORT_X_START, viewport->x, ++ SEC_VIEWPORT_Y_START, viewport->y); ++ ++ /* DC supports NV12 only at the moment */ ++ REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION_C, 0, ++ PRI_VIEWPORT_WIDTH_C, viewport_c->width, ++ PRI_VIEWPORT_HEIGHT_C, viewport_c->height); ++ ++ REG_SET_2(DCSURF_PRI_VIEWPORT_START_C, 0, ++ PRI_VIEWPORT_X_START_C, viewport_c->x, ++ PRI_VIEWPORT_Y_START_C, viewport_c->y); ++} ++ ++ + static struct mem_input_funcs dcn10_mem_input_funcs = { + .mem_input_program_display_marks = min10_program_display_marks, + .mem_input_program_surface_flip_and_addr = +@@ -1070,9 +1105,9 @@ static struct mem_input_funcs dcn10_mem_input_funcs = { + .mem_input_program_pte_vm = min10_program_pte_vm, + .set_blank = min10_set_blank, + .dcc_control = min10_dcc_control, ++ .mem_program_viewport = min_set_viewport, + }; + +- + /*****************************************/ + /* Constructor, Destructor */ + /*****************************************/ +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h +index c3f18bd..7efa857 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h +@@ -40,6 +40,12 @@ + SRI(DCSURF_SURFACE_PITCH_C, HUBPREQ, id),\ + SRI(DCSURF_SURFACE_CONFIG, HUBP, id),\ + SRI(DCSURF_FLIP_CONTROL, HUBPREQ, id),\ ++ SRI(DCSURF_PRI_VIEWPORT_DIMENSION, HUBP, id), \ ++ SRI(DCSURF_PRI_VIEWPORT_START, HUBP, id), \ ++ SRI(DCSURF_SEC_VIEWPORT_DIMENSION, HUBP, id), \ ++ SRI(DCSURF_SEC_VIEWPORT_START, HUBP, id), \ ++ SRI(DCSURF_PRI_VIEWPORT_DIMENSION_C, HUBP, id), \ ++ SRI(DCSURF_PRI_VIEWPORT_START_C, HUBP, id), \ + SRI(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, HUBPREQ, id),\ + SRI(DCSURF_PRIMARY_SURFACE_ADDRESS, HUBPREQ, id),\ + SRI(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, HUBPREQ, id),\ +@@ -164,6 +170,12 @@ struct dcn_mi_registers { + uint32_t DCSURF_SURFACE_PITCH_C; + uint32_t DCSURF_SURFACE_CONFIG; + uint32_t DCSURF_FLIP_CONTROL; ++ uint32_t DCSURF_PRI_VIEWPORT_DIMENSION; ++ uint32_t DCSURF_PRI_VIEWPORT_START; ++ uint32_t DCSURF_SEC_VIEWPORT_DIMENSION; ++ uint32_t DCSURF_SEC_VIEWPORT_START; ++ uint32_t DCSURF_PRI_VIEWPORT_DIMENSION_C; ++ uint32_t DCSURF_PRI_VIEWPORT_START_C; + uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; + uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; + uint32_t DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH; +@@ -312,6 +324,18 @@ struct dcn_mi_registers { + MI_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_TYPE, mask_sh),\ + MI_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_PENDING, mask_sh),\ + MI_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, mask_sh),\ ++ MI_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH, mask_sh),\ ++ MI_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT, mask_sh),\ ++ MI_SF(HUBP0_DCSURF_PRI_VIEWPORT_START, PRI_VIEWPORT_X_START, mask_sh),\ ++ MI_SF(HUBP0_DCSURF_PRI_VIEWPORT_START, PRI_VIEWPORT_Y_START, mask_sh),\ ++ MI_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION, SEC_VIEWPORT_WIDTH, mask_sh),\ ++ MI_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION, SEC_VIEWPORT_HEIGHT, mask_sh),\ ++ MI_SF(HUBP0_DCSURF_SEC_VIEWPORT_START, SEC_VIEWPORT_X_START, mask_sh),\ ++ MI_SF(HUBP0_DCSURF_SEC_VIEWPORT_START, SEC_VIEWPORT_Y_START, mask_sh),\ ++ MI_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C, PRI_VIEWPORT_WIDTH_C, mask_sh),\ ++ MI_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C, PRI_VIEWPORT_HEIGHT_C, mask_sh),\ ++ MI_SF(HUBP0_DCSURF_PRI_VIEWPORT_START_C, PRI_VIEWPORT_X_START_C, mask_sh),\ ++ MI_SF(HUBP0_DCSURF_PRI_VIEWPORT_START_C, PRI_VIEWPORT_Y_START_C, mask_sh),\ + MI_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, PRIMARY_SURFACE_ADDRESS_HIGH, mask_sh),\ + MI_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS, PRIMARY_SURFACE_ADDRESS, mask_sh),\ + MI_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, SECONDARY_SURFACE_ADDRESS_HIGH, mask_sh),\ +@@ -459,6 +483,18 @@ struct dcn_mi_registers { + type SURFACE_FLIP_TYPE;\ + type SURFACE_UPDATE_LOCK;\ + type SURFACE_FLIP_PENDING;\ ++ type PRI_VIEWPORT_WIDTH; \ ++ type PRI_VIEWPORT_HEIGHT; \ ++ type PRI_VIEWPORT_X_START; \ ++ type PRI_VIEWPORT_Y_START; \ ++ type SEC_VIEWPORT_WIDTH; \ ++ type SEC_VIEWPORT_HEIGHT; \ ++ type SEC_VIEWPORT_X_START; \ ++ type SEC_VIEWPORT_Y_START; \ ++ type PRI_VIEWPORT_WIDTH_C; \ ++ type PRI_VIEWPORT_HEIGHT_C; \ ++ type PRI_VIEWPORT_X_START_C; \ ++ type PRI_VIEWPORT_Y_START_C; \ + type PRIMARY_SURFACE_ADDRESS_HIGH;\ + type PRIMARY_SURFACE_ADDRESS;\ + type SECONDARY_SURFACE_ADDRESS_HIGH;\ +diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h +index 64b810d..1b7d151 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h +@@ -89,6 +89,10 @@ struct mem_input_funcs { + + void (*dcc_control)(struct mem_input *mem_input, bool enable, + bool independent_64b_blks); ++ void (*mem_program_viewport)( ++ struct mem_input *mem_input, ++ const struct rect *viewport, ++ const struct rect *viewport_c); + #endif + + void (*mem_input_program_display_marks)( +-- +2.7.4 + |