diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/0609-drm-amd-display-change-order-of-HUBP-and-MPC-disable.patch')
| -rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.14.71/0609-drm-amd-display-change-order-of-HUBP-and-MPC-disable.patch | 65 |
1 files changed, 0 insertions, 65 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/0609-drm-amd-display-change-order-of-HUBP-and-MPC-disable.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/0609-drm-amd-display-change-order-of-HUBP-and-MPC-disable.patch deleted file mode 100644 index 40a75ccb..00000000 --- a/common/recipes-kernel/linux/linux-yocto-4.14.71/0609-drm-amd-display-change-order-of-HUBP-and-MPC-disable.patch +++ /dev/null @@ -1,65 +0,0 @@ -From 309f06c61f6606a97f3bc227d903fa79ca80a279 Mon Sep 17 00:00:00 2001 -From: Tony Cheng <tony.cheng@amd.com> -Date: Wed, 12 Jul 2017 09:02:54 -0400 -Subject: [PATCH 0609/4131] drm/amd/display: change order of HUBP and MPC - disable according to HW guide - -blank hubp first before disconnect MPC - -Signed-off-by: Tony Cheng <tony.cheng@amd.com> -Reviewed-by: Eric Yang <eric.yang2@amd.com> -Acked-by: Harry Wentland <Harry.Wentland@amd.com> -Signed-off-by: Alex Deucher <alexander.deucher@amd.com> ---- - drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 10 +++++++--- - drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c | 4 +++- - 2 files changed, 10 insertions(+), 4 deletions(-) - -diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c -index ac0d62c..0e90e6c 100644 ---- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c -+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c -@@ -477,9 +477,14 @@ static void reset_front_end( - if (mpcc->opp_id == 0xf) - return; - -- mi->funcs->dcc_control(mi, false, false); - tg->funcs->lock(tg); - -+ mi->funcs->dcc_control(mi, false, false); -+ mi->funcs->set_blank(mi, true); -+ REG_WAIT(DCHUBP_CNTL[fe_idx], -+ HUBP_NO_OUTSTANDING_REQ, 1, -+ 1, 200); -+ - mpcc_cfg.opp_id = 0xf; - mpcc_cfg.top_dpp_id = 0xf; - mpcc_cfg.bot_mpcc_id = 0xf; -@@ -491,8 +496,7 @@ static void reset_front_end( - REG_WAIT(OTG_GLOBAL_SYNC_STATUS[tg->inst], VUPDATE_NO_LOCK_EVENT_OCCURRED, 1, 20000, 200000); - - mpcc->funcs->wait_for_idle(mpcc); -- mi->funcs->set_blank(mi, true); -- REG_WAIT(DCHUBP_CNTL[fe_idx], HUBP_NO_OUTSTANDING_REQ, 1, 20000, 200000); -+ - REG_UPDATE(HUBP_CLK_CNTL[fe_idx], HUBP_CLOCK_ENABLE, 0); - REG_UPDATE(DPP_CONTROL[fe_idx], DPP_CLOCK_ENABLE, 0); - -diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c -index 1c9d5e9..9875d81 100644 ---- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c -+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c -@@ -117,7 +117,9 @@ static void dcn10_mpcc_wait_idle(struct mpcc *mpcc) - { - struct dcn10_mpcc *mpcc10 = TO_DCN10_MPCC(mpcc); - -- REG_WAIT(MPCC_STATUS, MPCC_BUSY, 0, 1000, 1000); -+ REG_WAIT(MPCC_STATUS, -+ MPCC_BUSY, 0, -+ 1000, 1000); - } - - --- -2.7.4 - |