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Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/0480-drm-amd-display-update-NV12-NV21-as-the-YUV-format.patch')
-rw-r--r--common/recipes-kernel/linux/linux-yocto-4.14.71/0480-drm-amd-display-update-NV12-NV21-as-the-YUV-format.patch93
1 files changed, 93 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/0480-drm-amd-display-update-NV12-NV21-as-the-YUV-format.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/0480-drm-amd-display-update-NV12-NV21-as-the-YUV-format.patch
new file mode 100644
index 00000000..96682ad1
--- /dev/null
+++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/0480-drm-amd-display-update-NV12-NV21-as-the-YUV-format.patch
@@ -0,0 +1,93 @@
+From 7f072d4fcd5ed26456abccd719b1392b7604db29 Mon Sep 17 00:00:00 2001
+From: Shirish S <shirish.s@amd.com>
+Date: Thu, 25 May 2017 14:36:47 +0530
+Subject: [PATCH 0480/4131] drm/amd/display: update NV12/NV21 as the YUV format
+
+This patch updates the YUV format supported to
+NV12 and NV21 and hence updates the offsets.
+
+BUG: SWDEV-119421
+TEST: (On Chromium OS for Stoney Only)
+ * Executed below tests to see YUV(underlay) & RGB planes on eDP
+ plane_test --format XR24 --size 500x100 -p --format NV12 --size
+ 500x500
+
+Signed-off-by: Shirish S <shirish.s@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Harry Wentland <Harry.Wentland@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 22 ++++++++++++----------
+ 1 file changed, 12 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
+index fbdb599..bb452ad 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
+@@ -455,6 +455,7 @@ static void fill_plane_attributes_from_fb(
+ {
+ uint64_t tiling_flags;
+ uint64_t fb_location = 0;
++ unsigned int awidth;
+ const struct drm_framebuffer *fb = &amdgpu_fb->base;
+ struct drm_format_name_buf format_name;
+
+@@ -483,10 +484,10 @@ static void fill_plane_attributes_from_fb(
+ case DRM_FORMAT_ABGR2101010:
+ surface->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
+ break;
+- case DRM_FORMAT_YUV420:
++ case DRM_FORMAT_NV21:
+ surface->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
+ break;
+- case DRM_FORMAT_YVU420:
++ case DRM_FORMAT_NV12:
+ surface->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
+ break;
+ default:
+@@ -509,24 +510,25 @@ static void fill_plane_attributes_from_fb(
+ surface->color_space = COLOR_SPACE_SRGB;
+
+ } else {
++ awidth = ALIGN(fb->width, 64);
+ surface->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
+ surface->address.video_progressive.luma_addr.low_part
+ = lower_32_bits(fb_location);
+ surface->address.video_progressive.chroma_addr.low_part
+ = lower_32_bits(fb_location) +
+- (fb->width * fb->height);
++ (awidth * fb->height);
+ surface->plane_size.video.luma_size.x = 0;
+ surface->plane_size.video.luma_size.y = 0;
+- surface->plane_size.video.luma_size.width = fb->width;
++ surface->plane_size.video.luma_size.width = awidth;
+ surface->plane_size.video.luma_size.height = fb->height;
+ /* TODO: unhardcode */
+- surface->plane_size.video.luma_pitch = ALIGN(fb->width, 64);
++ surface->plane_size.video.luma_pitch = awidth;
+
+ surface->plane_size.video.chroma_size.x = 0;
+ surface->plane_size.video.chroma_size.y = 0;
+- surface->plane_size.video.chroma_size.width = fb->width / 2;
+- surface->plane_size.video.chroma_size.height = fb->height / 2;
+- surface->plane_size.video.chroma_pitch = ALIGN(fb->width, 64) / 2;
++ surface->plane_size.video.chroma_size.width = awidth;
++ surface->plane_size.video.chroma_size.height = fb->height;
++ surface->plane_size.video.chroma_pitch = awidth / 2;
+
+ /* TODO: unhardcode */
+ surface->color_space = COLOR_SPACE_YCBCR709;
+@@ -1817,8 +1819,8 @@ static uint32_t rgb_formats[] = {
+ };
+
+ static uint32_t yuv_formats[] = {
+- DRM_FORMAT_YUV420,
+- DRM_FORMAT_YVU420,
++ DRM_FORMAT_NV12,
++ DRM_FORMAT_NV21,
+ };
+
+ int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
+--
+2.7.4
+