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Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/0417-drm-amd-display-single-channel-bandwidth-verses-dual.patch')
-rw-r--r--common/recipes-kernel/linux/linux-yocto-4.14.71/0417-drm-amd-display-single-channel-bandwidth-verses-dual.patch54
1 files changed, 0 insertions, 54 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/0417-drm-amd-display-single-channel-bandwidth-verses-dual.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/0417-drm-amd-display-single-channel-bandwidth-verses-dual.patch
deleted file mode 100644
index 99212994..00000000
--- a/common/recipes-kernel/linux/linux-yocto-4.14.71/0417-drm-amd-display-single-channel-bandwidth-verses-dual.patch
+++ /dev/null
@@ -1,54 +0,0 @@
-From b6b9f092acc5a479377b28999784a13b417a6408 Mon Sep 17 00:00:00 2001
-From: Charlene Liu <charlene.liu@amd.com>
-Date: Mon, 8 May 2017 17:46:57 -0400
-Subject: [PATCH 0417/4131] drm/amd/display: single channel bandwidth verses
- dual channel bandwidth
-
-DPM0, FCLK=MCLK, single channel bandwidth = dual channel bandwidth
-for the rest of the DPM levels, single channel bandwidth = 1/2 dual channel bandwidth
-
-Signed-off-by: Charlene Liu <charlene.liu@amd.com>
-Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Acked-by: Harry Wentland <Harry.Wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 9 ++++++---
- 1 file changed, 6 insertions(+), 3 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
-index 26587bc..6d8bc6c 100644
---- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
-+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
-@@ -920,6 +920,10 @@ bool dcn_validate_bandwidth(
- calc_wm_sets_and_perf_params(context, v);
- context->bw.dcn.calc_clk.fclk_khz = (int)(bw_consumed * 1000000 /
- (ddr4_dram_factor_single_Channel * v->number_of_channels));
-+ if (bw_consumed == v->fabric_and_dram_bandwidth_vmin0p65) {
-+ context->bw.dcn.calc_clk.fclk_khz = (int)(bw_consumed * 1000000 / 32);
-+ }
-+
- context->bw.dcn.calc_clk.dram_ccm_us = (int)(v->dram_clock_change_margin);
- context->bw.dcn.calc_clk.min_active_dram_ccm_us = (int)(v->min_active_dram_clock_change_margin);
- context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz = (int)(v->dcf_clk_deep_sleep * 1000);
-@@ -1178,8 +1182,7 @@ void dcn_bw_update_from_pplib(struct core_dc *dc)
- ctx, DM_PP_CLOCK_TYPE_FCLK, &clks) &&
- clks.num_levels != 0) {
- ASSERT(clks.num_levels >= 3);
-- dc->dcn_soc.fabric_and_dram_bandwidth_vmin0p65 = dc->dcn_soc.number_of_channels *
-- (clks.data[0].clocks_in_khz / 1000.0) * ddr4_dram_factor_single_Channel / 1000.0;
-+ dc->dcn_soc.fabric_and_dram_bandwidth_vmin0p65 = 32 * (clks.data[0].clocks_in_khz / 1000.0) / 1000.0;
- if (clks.num_levels > 2) {
- dc->dcn_soc.fabric_and_dram_bandwidth_vmid0p72 = dc->dcn_soc.number_of_channels *
- (clks.data[clks.num_levels - 3].clocks_in_khz / 1000.0) * ddr4_dram_factor_single_Channel / 1000.0;
-@@ -1240,7 +1243,7 @@ void dcn_bw_notify_pplib_of_wm_ranges(struct core_dc *dc)
- kernel_fpu_begin();
- max_fclk_khz = dc->dcn_soc.fabric_and_dram_bandwidth_vmax0p9 * 1000000 / factor;
- nom_fclk_khz = dc->dcn_soc.fabric_and_dram_bandwidth_vnom0p8 * 1000000 / factor;
-- min_fclk_khz = dc->dcn_soc.fabric_and_dram_bandwidth_vmin0p65 * 1000000 / factor;
-+ min_fclk_khz = dc->dcn_soc.fabric_and_dram_bandwidth_vmin0p65 * 1000000 / 32;
- max_dcfclk_khz = dc->dcn_soc.dcfclkv_max0p9 * 1000;
- nom_dcfclk_khz = dc->dcn_soc.dcfclkv_nom0p8 * 1000;
- min_dcfclk_khz = dc->dcn_soc.dcfclkv_min0p65 * 1000;
---
-2.7.4
-