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Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/0414-drm-amd-display-switch-to-using-calc_clk-and-cur_clk.patch')
-rw-r--r--common/recipes-kernel/linux/linux-yocto-4.14.71/0414-drm-amd-display-switch-to-using-calc_clk-and-cur_clk.patch184
1 files changed, 0 insertions, 184 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/0414-drm-amd-display-switch-to-using-calc_clk-and-cur_clk.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/0414-drm-amd-display-switch-to-using-calc_clk-and-cur_clk.patch
deleted file mode 100644
index 47d3b723..00000000
--- a/common/recipes-kernel/linux/linux-yocto-4.14.71/0414-drm-amd-display-switch-to-using-calc_clk-and-cur_clk.patch
+++ /dev/null
@@ -1,184 +0,0 @@
-From 678696b30c76b1ee98dcaca1fccf784096de1758 Mon Sep 17 00:00:00 2001
-From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Date: Wed, 3 May 2017 11:40:40 -0400
-Subject: [PATCH 0414/4131] drm/amd/display: switch to using calc_clk and
- cur_clk for dcn bw setting
-
-Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
-Acked-by: Harry Wentland <Harry.Wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 50 +++++++++++-------
- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 59 +++++++++++++++++-----
- 2 files changed, 79 insertions(+), 30 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
-index 41aeceb..150c8a4 100644
---- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
-@@ -1647,24 +1647,38 @@ enum dc_status dce110_apply_ctx_to_hw(
- apply_min_clocks(dc, context, &clocks_state, true);
-
- #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
-- if (context->bw.dcn.calc_clk.fclk_khz
-- > dc->current_context->bw.dcn.calc_clk.fclk_khz) {
-- struct dm_pp_clock_for_voltage_req clock;
--
-- clock.clk_type = DM_PP_CLOCK_TYPE_FCLK;
-- clock.clocks_in_khz = context->bw.dcn.calc_clk.fclk_khz;
-- dm_pp_apply_clock_for_voltage_request(dc->ctx, &clock);
-- dc->current_context->bw.dcn.calc_clk.fclk_khz = clock.clocks_in_khz;
-- }
-- if (context->bw.dcn.calc_clk.dcfclk_khz
-- > dc->current_context->bw.dcn.calc_clk.dcfclk_khz) {
-- struct dm_pp_clock_for_voltage_req clock;
--
-- clock.clk_type = DM_PP_CLOCK_TYPE_DCFCLK;
-- clock.clocks_in_khz = context->bw.dcn.calc_clk.dcfclk_khz;
-- dm_pp_apply_clock_for_voltage_request(dc->ctx, &clock);
-- dc->current_context->bw.dcn.calc_clk.dcfclk_khz = clock.clocks_in_khz;
-- }
-+ if (resource_parse_asic_id(dc->ctx->asic_id) == DCN_VERSION_1_0) {
-+ if (context->bw.dcn.calc_clk.fclk_khz
-+ > dc->current_context->bw.dcn.cur_clk.fclk_khz) {
-+ struct dm_pp_clock_for_voltage_req clock;
-+
-+ clock.clk_type = DM_PP_CLOCK_TYPE_FCLK;
-+ clock.clocks_in_khz = context->bw.dcn.calc_clk.fclk_khz;
-+ dm_pp_apply_clock_for_voltage_request(dc->ctx, &clock);
-+ dc->current_context->bw.dcn.cur_clk.fclk_khz = clock.clocks_in_khz;
-+ context->bw.dcn.cur_clk.fclk_khz = clock.clocks_in_khz;
-+ }
-+ if (context->bw.dcn.calc_clk.dcfclk_khz
-+ > dc->current_context->bw.dcn.cur_clk.dcfclk_khz) {
-+ struct dm_pp_clock_for_voltage_req clock;
-+
-+ clock.clk_type = DM_PP_CLOCK_TYPE_DCFCLK;
-+ clock.clocks_in_khz = context->bw.dcn.calc_clk.dcfclk_khz;
-+ dm_pp_apply_clock_for_voltage_request(dc->ctx, &clock);
-+ dc->current_context->bw.dcn.cur_clk.dcfclk_khz = clock.clocks_in_khz;
-+ context->bw.dcn.cur_clk.dcfclk_khz = clock.clocks_in_khz;
-+ }
-+ if (context->bw.dcn.calc_clk.dispclk_khz
-+ > dc->current_context->bw.dcn.cur_clk.dispclk_khz) {
-+ dc->res_pool->display_clock->funcs->set_clock(
-+ dc->res_pool->display_clock,
-+ context->bw.dcn.calc_clk.dispclk_khz);
-+ dc->current_context->bw.dcn.cur_clk.dispclk_khz =
-+ context->bw.dcn.calc_clk.dispclk_khz;
-+ context->bw.dcn.cur_clk.dispclk_khz =
-+ context->bw.dcn.calc_clk.dispclk_khz;
-+ }
-+ } else
- #endif
- if (context->bw.dce.dispclk_khz
- > dc->current_context->bw.dce.dispclk_khz) {
-diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
-index a62c4e7..f5638ad 100644
---- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
-@@ -1429,6 +1429,9 @@ static void dcn10_power_on_fe(
- pipe_ctx->pipe_idx,
- pipe_ctx->pix_clk_params.requested_pix_clk,
- context->bw.dcn.calc_clk.dppclk_div);
-+ dc->current_context->bw.dcn.cur_clk.dppclk_div =
-+ context->bw.dcn.calc_clk.dppclk_div;
-+ context->bw.dcn.cur_clk.dppclk_div = context->bw.dcn.calc_clk.dppclk_div;
-
- if (dc_surface) {
- dm_logger_write(dc->ctx->logger, LOG_DC,
-@@ -1531,6 +1534,9 @@ static void update_dchubp_dpp(
- pipe_ctx->pipe_idx,
- pipe_ctx->pix_clk_params.requested_pix_clk,
- context->bw.dcn.calc_clk.dppclk_div);
-+ dc->current_context->bw.dcn.cur_clk.dppclk_div =
-+ context->bw.dcn.calc_clk.dppclk_div;
-+ context->bw.dcn.cur_clk.dppclk_div = context->bw.dcn.calc_clk.dppclk_div;
-
- select_vtg(dc->ctx, pipe_ctx->pipe_idx, pipe_ctx->tg->inst);
-
-@@ -1679,16 +1685,16 @@ static void dcn10_pplib_apply_display_requirements(
-
- pp_display_cfg->all_displays_in_sync = false;/*todo*/
- pp_display_cfg->nb_pstate_switch_disable = false;
-- pp_display_cfg->min_engine_clock_khz = context->bw.dcn.calc_clk.dcfclk_khz;
-- pp_display_cfg->min_memory_clock_khz = context->bw.dcn.calc_clk.fclk_khz;
-- pp_display_cfg->min_engine_clock_deep_sleep_khz = context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz;
-- pp_display_cfg->min_dcfc_deep_sleep_clock_khz = context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz;
-+ pp_display_cfg->min_engine_clock_khz = context->bw.dcn.cur_clk.dcfclk_khz;
-+ pp_display_cfg->min_memory_clock_khz = context->bw.dcn.cur_clk.fclk_khz;
-+ pp_display_cfg->min_engine_clock_deep_sleep_khz = context->bw.dcn.cur_clk.dcfclk_deep_sleep_khz;
-+ pp_display_cfg->min_dcfc_deep_sleep_clock_khz = context->bw.dcn.cur_clk.dcfclk_deep_sleep_khz;
- pp_display_cfg->avail_mclk_switch_time_us =
-- context->bw.dcn.calc_clk.dram_ccm_us > 0 ? context->bw.dcn.calc_clk.dram_ccm_us : 0;
-+ context->bw.dcn.cur_clk.dram_ccm_us > 0 ? context->bw.dcn.cur_clk.dram_ccm_us : 0;
- pp_display_cfg->avail_mclk_switch_time_in_disp_active_us =
-- context->bw.dcn.calc_clk.min_active_dram_ccm_us > 0 ? context->bw.dcn.calc_clk.min_active_dram_ccm_us : 0;
-- pp_display_cfg->min_dcfclock_khz = context->bw.dcn.calc_clk.dcfclk_khz;
-- pp_display_cfg->disp_clk_khz = context->bw.dcn.calc_clk.dispclk_khz;
-+ context->bw.dcn.cur_clk.min_active_dram_ccm_us > 0 ? context->bw.dcn.cur_clk.min_active_dram_ccm_us : 0;
-+ pp_display_cfg->min_dcfclock_khz = context->bw.dcn.cur_clk.dcfclk_khz;
-+ pp_display_cfg->disp_clk_khz = context->bw.dcn.cur_clk.dispclk_khz;
- dce110_fill_display_configs(context, pp_display_cfg);
-
- if (memcmp(&dc->prev_display_config, pp_display_cfg, sizeof(
-@@ -1755,22 +1761,51 @@ static void dcn10_set_bandwidth(
- if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
- return;
-
-- if (decrease_allowed || context->bw.dcn.calc_clk.dispclk_khz > dc->current_context->bw.dcn.calc_clk.dispclk_khz) {
-+ if (decrease_allowed || context->bw.dcn.calc_clk.dispclk_khz
-+ > dc->current_context->bw.dcn.cur_clk.dispclk_khz) {
- dc->res_pool->display_clock->funcs->set_clock(
- dc->res_pool->display_clock,
- context->bw.dcn.calc_clk.dispclk_khz);
-- dc->current_context->bw.dcn.calc_clk.dispclk_khz = context->bw.dcn.calc_clk.dispclk_khz;
-+ dc->current_context->bw.dcn.cur_clk.dispclk_khz =
-+ context->bw.dcn.calc_clk.dispclk_khz;
- }
-- if (decrease_allowed || context->bw.dcn.calc_clk.dcfclk_khz > dc->current_context->bw.dcn.calc_clk.dcfclk_khz) {
-+ if (decrease_allowed || context->bw.dcn.calc_clk.dcfclk_khz
-+ > dc->current_context->bw.dcn.cur_clk.dcfclk_khz) {
- clock.clk_type = DM_PP_CLOCK_TYPE_DCFCLK;
- clock.clocks_in_khz = context->bw.dcn.calc_clk.dcfclk_khz;
- dm_pp_apply_clock_for_voltage_request(dc->ctx, &clock);
-+ dc->current_context->bw.dcn.cur_clk.dcfclk_khz = clock.clocks_in_khz;
-+ context->bw.dcn.cur_clk.dcfclk_khz = clock.clocks_in_khz;
- }
-- if (decrease_allowed || context->bw.dcn.calc_clk.fclk_khz > dc->current_context->bw.dcn.calc_clk.fclk_khz) {
-+ if (decrease_allowed || context->bw.dcn.calc_clk.fclk_khz
-+ > dc->current_context->bw.dcn.cur_clk.fclk_khz) {
- clock.clk_type = DM_PP_CLOCK_TYPE_FCLK;
- clock.clocks_in_khz = context->bw.dcn.calc_clk.fclk_khz;
- dm_pp_apply_clock_for_voltage_request(dc->ctx, &clock);
- dc->current_context->bw.dcn.calc_clk.fclk_khz = clock.clocks_in_khz;
-+ context->bw.dcn.cur_clk.fclk_khz = clock.clocks_in_khz;
-+ }
-+ if (decrease_allowed || context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz
-+ > dc->current_context->bw.dcn.cur_clk.dcfclk_deep_sleep_khz) {
-+ dc->current_context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz =
-+ context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz;
-+ context->bw.dcn.cur_clk.dcfclk_deep_sleep_khz =
-+ context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz;
-+ }
-+ /* Decrease in freq is increase in period so opposite comparison for dram_ccm */
-+ if (decrease_allowed || context->bw.dcn.calc_clk.dram_ccm_us
-+ < dc->current_context->bw.dcn.cur_clk.dram_ccm_us) {
-+ dc->current_context->bw.dcn.calc_clk.dram_ccm_us =
-+ context->bw.dcn.calc_clk.dram_ccm_us;
-+ context->bw.dcn.cur_clk.dram_ccm_us =
-+ context->bw.dcn.calc_clk.dram_ccm_us;
-+ }
-+ if (decrease_allowed || context->bw.dcn.calc_clk.min_active_dram_ccm_us
-+ < dc->current_context->bw.dcn.cur_clk.min_active_dram_ccm_us) {
-+ dc->current_context->bw.dcn.calc_clk.min_active_dram_ccm_us =
-+ context->bw.dcn.calc_clk.min_active_dram_ccm_us;
-+ context->bw.dcn.cur_clk.min_active_dram_ccm_us =
-+ context->bw.dcn.calc_clk.min_active_dram_ccm_us;
- }
- dcn10_pplib_apply_display_requirements(dc, context);
- }
---
-2.7.4
-