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Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/0413-drm-amd-display-refactor-bw-related-variable-structu.patch')
-rw-r--r--common/recipes-kernel/linux/linux-yocto-4.14.71/0413-drm-amd-display-refactor-bw-related-variable-structu.patch1217
1 files changed, 1217 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/0413-drm-amd-display-refactor-bw-related-variable-structu.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/0413-drm-amd-display-refactor-bw-related-variable-structu.patch
new file mode 100644
index 00000000..16d16a52
--- /dev/null
+++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/0413-drm-amd-display-refactor-bw-related-variable-structu.patch
@@ -0,0 +1,1217 @@
+From 552253822f34541423595df5353f4d604a56983f Mon Sep 17 00:00:00 2001
+From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Date: Tue, 2 May 2017 17:29:48 -0400
+Subject: [PATCH 0413/4131] drm/amd/display: refactor bw related variable
+ structure in val_ctx
+
+Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Harry Wentland <Harry.Wentland@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c | 18 ++---
+ drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 79 +++++++++++-----------
+ drivers/gpu/drm/amd/display/dc/core/dc.c | 20 +-----
+ drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c | 6 +-
+ drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h | 12 ++--
+ .../amd/display/dc/dce100/dce100_hw_sequencer.c | 9 ++-
+ .../drm/amd/display/dc/dce100/dce100_resource.c | 4 +-
+ .../amd/display/dc/dce110/dce110_hw_sequencer.c | 65 +++++++++---------
+ .../drm/amd/display/dc/dce110/dce110_mem_input.c | 12 ++--
+ .../drm/amd/display/dc/dce110/dce110_mem_input.h | 6 +-
+ .../drm/amd/display/dc/dce110/dce110_mem_input_v.c | 30 ++++----
+ .../drm/amd/display/dc/dce110/dce110_mem_input_v.h | 6 +-
+ .../drm/amd/display/dc/dce110/dce110_resource.c | 63 +++++++++--------
+ .../drm/amd/display/dc/dce112/dce112_resource.c | 63 +++++++++--------
+ .../gpu/drm/amd/display/dc/dce80/dce80_resource.c | 4 +-
+ .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 38 +++++------
+ .../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c | 6 +-
+ drivers/gpu/drm/amd/display/dc/inc/core_types.h | 56 +++++++++++----
+ drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h | 29 +-------
+ drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h | 20 ++++--
+ 20 files changed, 269 insertions(+), 277 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
+index 627b758..8766698 100644
+--- a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
++++ b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
+@@ -2557,7 +2557,7 @@ void bw_calcs_init(struct bw_calcs_dceip *bw_dceip,
+ */
+ static bool is_display_configuration_supported(
+ const struct bw_calcs_vbios *vbios,
+- const struct bw_calcs_output *calcs_output)
++ const struct dce_bw_output *calcs_output)
+ {
+ uint32_t int_max_clk;
+
+@@ -2568,7 +2568,7 @@ static bool is_display_configuration_supported(
+
+ int_max_clk = bw_fixed_to_int(vbios->high_sclk);
+ int_max_clk *= 1000; /* MHz to kHz */
+- if (calcs_output->required_sclk > int_max_clk)
++ if (calcs_output->sclk_khz > int_max_clk)
+ return false;
+
+ return true;
+@@ -2790,7 +2790,7 @@ bool bw_calcs(struct dc_context *ctx,
+ const struct bw_calcs_vbios *vbios,
+ const struct pipe_ctx pipe[],
+ int pipe_count,
+- struct bw_calcs_output *calcs_output)
++ struct dce_bw_output *calcs_output)
+ {
+ struct bw_calcs_data *data = dm_alloc(sizeof(struct bw_calcs_data));
+
+@@ -2831,20 +2831,20 @@ bool bw_calcs(struct dc_context *ctx,
+ bw_int_to_fixed(1000)));
+ calcs_output->blackout_recovery_time_us =
+ bw_fixed_to_int(data->blackout_recovery_time);
+- calcs_output->required_sclk =
++ calcs_output->sclk_khz =
+ bw_fixed_to_int(bw_mul(data->required_sclk,
+ bw_int_to_fixed(1000)));
+- calcs_output->required_sclk_deep_sleep =
++ calcs_output->sclk_deep_sleep_khz =
+ bw_fixed_to_int(bw_mul(data->sclk_deep_sleep,
+ bw_int_to_fixed(1000)));
+ if (yclk_lvl == 0)
+- calcs_output->required_yclk = bw_fixed_to_int(
++ calcs_output->yclk_khz = bw_fixed_to_int(
+ bw_mul(low_yclk, bw_int_to_fixed(1000)));
+ else if (yclk_lvl == 1)
+- calcs_output->required_yclk = bw_fixed_to_int(
++ calcs_output->yclk_khz = bw_fixed_to_int(
+ bw_mul(mid_yclk, bw_int_to_fixed(1000)));
+ else
+- calcs_output->required_yclk = bw_fixed_to_int(
++ calcs_output->yclk_khz = bw_fixed_to_int(
+ bw_mul(high_yclk, bw_int_to_fixed(1000)));
+
+ /* units: nanosecond, 16bit storage. */
+@@ -3245,7 +3245,7 @@ bool bw_calcs(struct dc_context *ctx,
+ calcs_output->cpup_state_change_enable = true;
+ calcs_output->stutter_mode_enable = true;
+ calcs_output->dispclk_khz = 0;
+- calcs_output->required_sclk = 0;
++ calcs_output->sclk_khz = 0;
+ }
+
+ dm_free(data);
+diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+index 22d98ef..1b9edfd 100644
+--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
++++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+@@ -470,17 +470,17 @@ static void dcn_dml_wm_override(
+ a.cpstate = dml_wm_cstate_pstate_e2e(dml, input, active_count);
+ a.pte_meta_urgent = dml_wm_pte_meta_urgent(dml, a.urgent);
+
+- context->watermarks.a.cstate_pstate.cstate_exit_ns =
++ context->bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns =
+ a.cpstate.cstate_exit_us * 1000;
+- context->watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns =
++ context->bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns =
+ a.cpstate.cstate_enter_plus_exit_us * 1000;
+- context->watermarks.a.cstate_pstate.pstate_change_ns =
++ context->bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns =
+ a.cpstate.pstate_change_us * 1000;
+- context->watermarks.a.pte_meta_urgent_ns = a.pte_meta_urgent * 1000;
+- context->watermarks.a.urgent_ns = a.urgent * 1000;
+- context->watermarks.b = context->watermarks.a;
+- context->watermarks.c = context->watermarks.a;
+- context->watermarks.d = context->watermarks.a;
++ context->bw.dcn.watermarks.a.pte_meta_urgent_ns = a.pte_meta_urgent * 1000;
++ context->bw.dcn.watermarks.a.urgent_ns = a.urgent * 1000;
++ context->bw.dcn.watermarks.b = context->bw.dcn.watermarks.a;
++ context->bw.dcn.watermarks.c = context->bw.dcn.watermarks.a;
++ context->bw.dcn.watermarks.d = context->bw.dcn.watermarks.a;
+
+
+ for (i = 0, in_idx = 0; i < pool->pipe_count; i++) {
+@@ -543,28 +543,28 @@ static void calc_wm_sets_and_perf_params(
+ v->fabric_and_dram_bandwidth = v->fabric_and_dram_bandwidth_vnom0p8;
+ dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v);
+
+- context->watermarks.b.cstate_pstate.cstate_exit_ns =
++ context->bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns =
+ v->stutter_exit_watermark * 1000;
+- context->watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns =
++ context->bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns =
+ v->stutter_enter_plus_exit_watermark * 1000;
+- context->watermarks.b.cstate_pstate.pstate_change_ns =
++ context->bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns =
+ v->dram_clock_change_watermark * 1000;
+- context->watermarks.b.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
+- context->watermarks.b.urgent_ns = v->urgent_watermark * 1000;
++ context->bw.dcn.watermarks.b.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
++ context->bw.dcn.watermarks.b.urgent_ns = v->urgent_watermark * 1000;
+
+ v->dcfclk_per_state[1] = v->dcfclkv_nom0p8;
+ v->dcfclk_per_state[0] = v->dcfclkv_nom0p8;
+ v->dcfclk = v->dcfclkv_nom0p8;
+ dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v);
+
+- context->watermarks.c.cstate_pstate.cstate_exit_ns =
++ context->bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns =
+ v->stutter_exit_watermark * 1000;
+- context->watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns =
++ context->bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns =
+ v->stutter_enter_plus_exit_watermark * 1000;
+- context->watermarks.c.cstate_pstate.pstate_change_ns =
++ context->bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns =
+ v->dram_clock_change_watermark * 1000;
+- context->watermarks.c.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
+- context->watermarks.c.urgent_ns = v->urgent_watermark * 1000;
++ context->bw.dcn.watermarks.c.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
++ context->bw.dcn.watermarks.c.urgent_ns = v->urgent_watermark * 1000;
+ }
+
+ if (v->voltage_level < 3) {
+@@ -578,14 +578,14 @@ static void calc_wm_sets_and_perf_params(
+ v->dcfclk = v->dcfclkv_max0p9;
+ dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v);
+
+- context->watermarks.d.cstate_pstate.cstate_exit_ns =
++ context->bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns =
+ v->stutter_exit_watermark * 1000;
+- context->watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns =
++ context->bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns =
+ v->stutter_enter_plus_exit_watermark * 1000;
+- context->watermarks.d.cstate_pstate.pstate_change_ns =
++ context->bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns =
+ v->dram_clock_change_watermark * 1000;
+- context->watermarks.d.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
+- context->watermarks.d.urgent_ns = v->urgent_watermark * 1000;
++ context->bw.dcn.watermarks.d.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
++ context->bw.dcn.watermarks.d.urgent_ns = v->urgent_watermark * 1000;
+ }
+
+ v->fabric_and_dram_bandwidth_per_state[2] = v->fabric_and_dram_bandwidth_vnom0p8;
+@@ -598,20 +598,20 @@ static void calc_wm_sets_and_perf_params(
+ v->dcfclk = v->dcfclk_per_state[v->voltage_level];
+ dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v);
+
+- context->watermarks.a.cstate_pstate.cstate_exit_ns =
++ context->bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns =
+ v->stutter_exit_watermark * 1000;
+- context->watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns =
++ context->bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns =
+ v->stutter_enter_plus_exit_watermark * 1000;
+- context->watermarks.a.cstate_pstate.pstate_change_ns =
++ context->bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns =
+ v->dram_clock_change_watermark * 1000;
+- context->watermarks.a.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
+- context->watermarks.a.urgent_ns = v->urgent_watermark * 1000;
++ context->bw.dcn.watermarks.a.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
++ context->bw.dcn.watermarks.a.urgent_ns = v->urgent_watermark * 1000;
+ if (v->voltage_level >= 2) {
+- context->watermarks.b = context->watermarks.a;
+- context->watermarks.c = context->watermarks.a;
++ context->bw.dcn.watermarks.b = context->bw.dcn.watermarks.a;
++ context->bw.dcn.watermarks.c = context->bw.dcn.watermarks.a;
+ }
+ if (v->voltage_level >= 3)
+- context->watermarks.d = context->watermarks.a;
++ context->bw.dcn.watermarks.d = context->bw.dcn.watermarks.a;
+ }
+
+ static bool dcn_bw_apply_registry_override(struct core_dc *dc)
+@@ -916,17 +916,16 @@ bool dcn_validate_bandwidth(
+
+ display_pipe_configuration(v);
+ calc_wm_sets_and_perf_params(context, v);
+- context->fclk_khz = (int)(bw_consumed * 1000000 /
++ context->bw.dcn.calc_clk.fclk_khz = (int)(bw_consumed * 1000000 /
+ (ddr4_dram_factor_single_Channel * v->number_of_channels));
+- context->dram_ccm_us = (int)(v->dram_clock_change_margin);
+- context->min_active_dram_ccm_us = (int)(v->min_active_dram_clock_change_margin);
+- context->dcfclk_deep_sleep_khz = (int)(v->dcf_clk_deep_sleep * 1000);
+- context->dcfclk_khz = (int)(v->dcfclk * 1000);
+- context->dispclk_khz = (int)(v->dispclk * 1000);
++ context->bw.dcn.calc_clk.dram_ccm_us = (int)(v->dram_clock_change_margin);
++ context->bw.dcn.calc_clk.min_active_dram_ccm_us = (int)(v->min_active_dram_clock_change_margin);
++ context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz = (int)(v->dcf_clk_deep_sleep * 1000);
++ context->bw.dcn.calc_clk.dcfclk_khz = (int)(v->dcfclk * 1000);
++ context->bw.dcn.calc_clk.dispclk_khz = (int)(v->dispclk * 1000);
+ if (dc->public.debug.max_disp_clk == true)
+- context->dispclk_khz = (int)(dc->dcn_soc.max_dispclk_vmax0p9 * 1000);
+- context->dppclk_khz = (int)(v->dppclk * 1000);
+- context->dppclk_div = (int)(v->dispclk_dppclk_ratio) == 2;
++ context->bw.dcn.calc_clk.dispclk_khz = (int)(dc->dcn_soc.max_dispclk_vmax0p9 * 1000);
++ context->bw.dcn.calc_clk.dppclk_div = (int)(v->dispclk_dppclk_ratio) == 2;
+
+ for (i = 0, input_idx = 0; i < pool->pipe_count; i++) {
+ struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index d063a25..b30d4bc 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -970,13 +970,7 @@ bool dc_post_update_surfaces_to_stream(struct dc *dc)
+ {
+ int i;
+ struct core_dc *core_dc = DC_TO_CORE(dc);
+- struct validate_context *context = dm_alloc(sizeof(struct validate_context));
+-
+- if (!context) {
+- dm_error("%s: failed to create validate ctx\n", __func__);
+- return false;
+- }
+- dc_resource_validate_ctx_copy_construct(core_dc->current_context, context);
++ struct validate_context *context = core_dc->current_context;
+
+ post_surface_trace(dc);
+
+@@ -986,21 +980,9 @@ bool dc_post_update_surfaces_to_stream(struct dc *dc)
+ core_dc->hwss.power_down_front_end(
+ core_dc, &context->res_ctx.pipe_ctx[i]);
+ }
+- if (!core_dc->res_pool->funcs->validate_bandwidth(core_dc, context)) {
+- BREAK_TO_DEBUGGER();
+- dc_resource_validate_ctx_destruct(context);
+- dm_free(context);
+- return false;
+- }
+
+ core_dc->hwss.set_bandwidth(core_dc, context, true);
+
+- if (core_dc->current_context) {
+- dc_resource_validate_ctx_destruct(core_dc->current_context);
+- dm_free(core_dc->current_context);
+- }
+- core_dc->current_context = context;
+-
+ return true;
+ }
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
+index 884f453..9da539d 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
+@@ -218,9 +218,9 @@ static void program_stutter_watermark(struct mem_input *mi,
+ }
+
+ void dce_mem_input_program_display_marks(struct mem_input *mi,
+- struct bw_watermarks nbp,
+- struct bw_watermarks stutter,
+- struct bw_watermarks urgent,
++ struct dce_watermarks nbp,
++ struct dce_watermarks stutter,
++ struct dce_watermarks urgent,
+ uint32_t total_dest_line_time_ns)
+ {
+ uint32_t stutter_en = mi->ctx->dc->debug.disable_stutter ? 0 : 1;
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
+index 6af533b..be37f52 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
+@@ -25,6 +25,10 @@
+ #ifndef __DCE_MEM_INPUT_H__
+ #define __DCE_MEM_INPUT_H__
+
++#include "dc_hw_types.h"
++struct dce_watermarks;
++struct mem_input;
++
+ #define MI_DCE_BASE_REG_LIST(id)\
+ SRI(GRPH_ENABLE, DCP, id),\
+ SRI(GRPH_CONTROL, DCP, id),\
+@@ -262,8 +266,6 @@ struct dce_mem_input_wa {
+ uint8_t single_head_rdreq_dmif_limit;
+ };
+
+-struct mem_input;
+-
+ void dce_mem_input_program_pte_vm(struct mem_input *mi,
+ enum surface_pixel_format format,
+ union dc_tiling_info *tiling_info,
+@@ -288,9 +290,9 @@ void dce_mem_input_free_dmif(struct mem_input *mi,
+ uint32_t total_stream_num);
+
+ void dce_mem_input_program_display_marks(struct mem_input *mi,
+- struct bw_watermarks nbp,
+- struct bw_watermarks stutter,
+- struct bw_watermarks urgent,
++ struct dce_watermarks nbp,
++ struct dce_watermarks stutter,
++ struct dce_watermarks urgent,
+ uint32_t total_dest_line_time_ns);
+
+ #endif /*__DCE_MEM_INPUT_H__*/
+diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c
+index 30c197f..843f50a 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c
+@@ -114,7 +114,7 @@ static void dce100_pplib_apply_display_requirements(
+
+ pp_display_cfg->avail_mclk_switch_time_us =
+ dce110_get_min_vblank_time_us(context);
+- pp_display_cfg->min_memory_clock_khz = context->bw_results.required_yclk
++ pp_display_cfg->min_memory_clock_khz = context->bw.dce.yclk_khz
+ / MEMORY_TYPE_MULTIPLIER;
+
+ dce110_fill_display_configs(context, pp_display_cfg);
+@@ -131,12 +131,11 @@ void dce100_set_bandwidth(
+ struct validate_context *context,
+ bool decrease_allowed)
+ {
+- if (decrease_allowed || context->dispclk_khz > dc->current_context->dispclk_khz) {
++ if (decrease_allowed || context->bw.dce.dispclk_khz > dc->current_context->bw.dce.dispclk_khz) {
+ dc->res_pool->display_clock->funcs->set_clock(
+ dc->res_pool->display_clock,
+- context->dispclk_khz * 115 / 100);
+- dc->current_context->bw_results.dispclk_khz = context->dispclk_khz;
+- dc->current_context->dispclk_khz = context->dispclk_khz;
++ context->bw.dce.dispclk_khz * 115 / 100);
++ dc->current_context->bw.dce.dispclk_khz = context->bw.dce.dispclk_khz;
+ }
+ dce100_pplib_apply_display_requirements(dc, context);
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+index f070070..254f9e4 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+@@ -764,8 +764,8 @@ bool dce100_validate_bandwidth(
+ struct validate_context *context)
+ {
+ /* TODO implement when needed but for now hardcode max value*/
+- context->dispclk_khz = 681000;
+- context->bw_results.required_yclk = 250000 * MEMORY_TYPE_MULTIPLIER;
++ context->bw.dce.dispclk_khz = 681000;
++ context->bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER;
+
+ return true;
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+index c89df8a..41aeceb 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+@@ -1252,17 +1252,17 @@ void dce110_set_displaymarks(
+ dc->bw_vbios.blackout_duration, pipe_ctx->stream);
+ pipe_ctx->mi->funcs->mem_input_program_display_marks(
+ pipe_ctx->mi,
+- context->bw_results.nbp_state_change_wm_ns[num_pipes],
+- context->bw_results.stutter_exit_wm_ns[num_pipes],
+- context->bw_results.urgent_wm_ns[num_pipes],
++ context->bw.dce.nbp_state_change_wm_ns[num_pipes],
++ context->bw.dce.stutter_exit_wm_ns[num_pipes],
++ context->bw.dce.urgent_wm_ns[num_pipes],
+ total_dest_line_time_ns);
+ if (i == underlay_idx) {
+ num_pipes++;
+ pipe_ctx->mi->funcs->mem_input_program_chroma_display_marks(
+ pipe_ctx->mi,
+- context->bw_results.nbp_state_change_wm_ns[num_pipes],
+- context->bw_results.stutter_exit_wm_ns[num_pipes],
+- context->bw_results.urgent_wm_ns[num_pipes],
++ context->bw.dce.nbp_state_change_wm_ns[num_pipes],
++ context->bw.dce.stutter_exit_wm_ns[num_pipes],
++ context->bw.dce.urgent_wm_ns[num_pipes],
+ total_dest_line_time_ns);
+ }
+ num_pipes++;
+@@ -1275,9 +1275,9 @@ static void set_safe_displaymarks(
+ {
+ int i;
+ int underlay_idx = pool->underlay_pipe_index;
+- struct bw_watermarks max_marks = {
++ struct dce_watermarks max_marks = {
+ MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK };
+- struct bw_watermarks nbp_marks = {
++ struct dce_watermarks nbp_marks = {
+ SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK };
+
+ for (i = 0; i < MAX_PIPES; i++) {
+@@ -1502,7 +1502,7 @@ static void apply_min_clocks(
+ /* get the required state based on state dependent clocks:
+ * display clock and pixel clock
+ */
+- req_clocks.display_clk_khz = context->dispclk_khz;
++ req_clocks.display_clk_khz = context->bw.dce.dispclk_khz;
+
+ req_clocks.pixel_clk_khz = get_max_pixel_clock_for_all_paths(
+ dc, context, true);
+@@ -1647,30 +1647,30 @@ enum dc_status dce110_apply_ctx_to_hw(
+ apply_min_clocks(dc, context, &clocks_state, true);
+
+ #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+- if (context->fclk_khz
+- > dc->current_context->fclk_khz) {
++ if (context->bw.dcn.calc_clk.fclk_khz
++ > dc->current_context->bw.dcn.calc_clk.fclk_khz) {
+ struct dm_pp_clock_for_voltage_req clock;
+
+ clock.clk_type = DM_PP_CLOCK_TYPE_FCLK;
+- clock.clocks_in_khz = context->fclk_khz;
++ clock.clocks_in_khz = context->bw.dcn.calc_clk.fclk_khz;
+ dm_pp_apply_clock_for_voltage_request(dc->ctx, &clock);
+- dc->current_context->fclk_khz = clock.clocks_in_khz;
++ dc->current_context->bw.dcn.calc_clk.fclk_khz = clock.clocks_in_khz;
+ }
+- if (context->dcfclk_khz
+- > dc->current_context->dcfclk_khz) {
++ if (context->bw.dcn.calc_clk.dcfclk_khz
++ > dc->current_context->bw.dcn.calc_clk.dcfclk_khz) {
+ struct dm_pp_clock_for_voltage_req clock;
+
+ clock.clk_type = DM_PP_CLOCK_TYPE_DCFCLK;
+- clock.clocks_in_khz = context->dcfclk_khz;
++ clock.clocks_in_khz = context->bw.dcn.calc_clk.dcfclk_khz;
+ dm_pp_apply_clock_for_voltage_request(dc->ctx, &clock);
+- dc->current_context->dcfclk_khz = clock.clocks_in_khz;
++ dc->current_context->bw.dcn.calc_clk.dcfclk_khz = clock.clocks_in_khz;
+ }
+ #endif
+- if (context->dispclk_khz
+- > dc->current_context->dispclk_khz) {
++ if (context->bw.dce.dispclk_khz
++ > dc->current_context->bw.dce.dispclk_khz) {
+ dc->res_pool->display_clock->funcs->set_clock(
+ dc->res_pool->display_clock,
+- context->dispclk_khz * 115 / 100);
++ context->bw.dce.dispclk_khz * 115 / 100);
+ }
+ /* program audio wall clock. use HDMI as clock source if HDMI
+ * audio active. Otherwise, use DP as clock source
+@@ -2275,32 +2275,32 @@ static void pplib_apply_display_requirements(
+ struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;
+
+ pp_display_cfg->all_displays_in_sync =
+- context->bw_results.all_displays_in_sync;
++ context->bw.dce.all_displays_in_sync;
+ pp_display_cfg->nb_pstate_switch_disable =
+- context->bw_results.nbp_state_change_enable == false;
++ context->bw.dce.nbp_state_change_enable == false;
+ pp_display_cfg->cpu_cc6_disable =
+- context->bw_results.cpuc_state_change_enable == false;
++ context->bw.dce.cpuc_state_change_enable == false;
+ pp_display_cfg->cpu_pstate_disable =
+- context->bw_results.cpup_state_change_enable == false;
++ context->bw.dce.cpup_state_change_enable == false;
+ pp_display_cfg->cpu_pstate_separation_time =
+- context->bw_results.blackout_recovery_time_us;
++ context->bw.dce.blackout_recovery_time_us;
+
+- pp_display_cfg->min_memory_clock_khz = context->bw_results.required_yclk
++ pp_display_cfg->min_memory_clock_khz = context->bw.dce.yclk_khz
+ / MEMORY_TYPE_MULTIPLIER;
+
+ pp_display_cfg->min_engine_clock_khz = determine_sclk_from_bounding_box(
+ dc,
+- context->bw_results.required_sclk);
++ context->bw.dce.sclk_khz);
+
+ pp_display_cfg->min_engine_clock_deep_sleep_khz
+- = context->bw_results.required_sclk_deep_sleep;
++ = context->bw.dce.sclk_deep_sleep_khz;
+
+ pp_display_cfg->avail_mclk_switch_time_us =
+ dce110_get_min_vblank_time_us(context);
+ /* TODO: dce11.2*/
+ pp_display_cfg->avail_mclk_switch_time_in_disp_active_us = 0;
+
+- pp_display_cfg->disp_clk_khz = context->dispclk_khz;
++ pp_display_cfg->disp_clk_khz = context->bw.dce.dispclk_khz;
+
+ dce110_fill_display_configs(context, pp_display_cfg);
+
+@@ -2329,12 +2329,11 @@ static void dce110_set_bandwidth(
+ {
+ dce110_set_displaymarks(dc, context);
+
+- if (decrease_allowed || context->dispclk_khz > dc->current_context->dispclk_khz) {
++ if (decrease_allowed || context->bw.dce.dispclk_khz > dc->current_context->bw.dce.dispclk_khz) {
+ dc->res_pool->display_clock->funcs->set_clock(
+ dc->res_pool->display_clock,
+- context->dispclk_khz * 115 / 100);
+- dc->current_context->bw_results.dispclk_khz = context->dispclk_khz;
+- dc->current_context->dispclk_khz = context->dispclk_khz;
++ context->bw.dce.dispclk_khz * 115 / 100);
++ dc->current_context->bw.dce.dispclk_khz = context->bw.dce.dispclk_khz;
+ }
+
+ pplib_apply_display_requirements(dc, context);
+diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.c
+index a20feae..45e1a8d 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.c
++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.c
+@@ -166,7 +166,7 @@ bool dce110_mem_input_program_surface_flip_and_addr(
+ static void program_urgency_watermark(
+ const struct dc_context *ctx,
+ const uint32_t offset,
+- struct bw_watermarks marks_low,
++ struct dce_watermarks marks_low,
+ uint32_t total_dest_line_time_ns)
+ {
+ /* register value */
+@@ -224,7 +224,7 @@ static void program_urgency_watermark(
+ static void program_stutter_watermark(
+ const struct dc_context *ctx,
+ const uint32_t offset,
+- struct bw_watermarks marks)
++ struct dce_watermarks marks)
+ {
+ /* register value */
+ uint32_t stutter_cntl = 0;
+@@ -289,7 +289,7 @@ static void program_stutter_watermark(
+ static void program_nbp_watermark(
+ const struct dc_context *ctx,
+ const uint32_t offset,
+- struct bw_watermarks marks)
++ struct dce_watermarks marks)
+ {
+ uint32_t value;
+ uint32_t addr;
+@@ -372,9 +372,9 @@ static void program_nbp_watermark(
+
+ void dce110_mem_input_program_display_marks(
+ struct mem_input *mem_input,
+- struct bw_watermarks nbp,
+- struct bw_watermarks stutter,
+- struct bw_watermarks urgent,
++ struct dce_watermarks nbp,
++ struct dce_watermarks stutter,
++ struct dce_watermarks urgent,
+ uint32_t total_dest_line_time_ns)
+ {
+ struct dce110_mem_input *bm_dce110 = TO_DCE110_MEM_INPUT(mem_input);
+diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.h
+index 4aec18c..5f10f26 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.h
++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.h
+@@ -55,9 +55,9 @@ bool dce110_mem_input_construct(
+ */
+ void dce110_mem_input_program_display_marks(
+ struct mem_input *mem_input,
+- struct bw_watermarks nbp,
+- struct bw_watermarks stutter,
+- struct bw_watermarks urgent,
++ struct dce_watermarks nbp,
++ struct dce_watermarks stutter,
++ struct dce_watermarks urgent,
+ uint32_t total_dest_line_time_ns);
+
+ /*
+diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c
+index 9c32b5b..02739d3 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c
++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c
+@@ -679,7 +679,7 @@ static void program_urgency_watermark(
+ const struct dc_context *ctx,
+ const uint32_t urgency_addr,
+ const uint32_t wm_addr,
+- struct bw_watermarks marks_low,
++ struct dce_watermarks marks_low,
+ uint32_t total_dest_line_time_ns)
+ {
+ /* register value */
+@@ -734,7 +734,7 @@ static void program_urgency_watermark(
+
+ static void program_urgency_watermark_l(
+ const struct dc_context *ctx,
+- struct bw_watermarks marks_low,
++ struct dce_watermarks marks_low,
+ uint32_t total_dest_line_time_ns)
+ {
+ program_urgency_watermark(
+@@ -747,7 +747,7 @@ static void program_urgency_watermark_l(
+
+ static void program_urgency_watermark_c(
+ const struct dc_context *ctx,
+- struct bw_watermarks marks_low,
++ struct dce_watermarks marks_low,
+ uint32_t total_dest_line_time_ns)
+ {
+ program_urgency_watermark(
+@@ -762,7 +762,7 @@ static void program_stutter_watermark(
+ const struct dc_context *ctx,
+ const uint32_t stutter_addr,
+ const uint32_t wm_addr,
+- struct bw_watermarks marks)
++ struct dce_watermarks marks)
+ {
+ /* register value */
+ uint32_t stutter_cntl = 0;
+@@ -822,7 +822,7 @@ static void program_stutter_watermark(
+
+ static void program_stutter_watermark_l(
+ const struct dc_context *ctx,
+- struct bw_watermarks marks)
++ struct dce_watermarks marks)
+ {
+ program_stutter_watermark(ctx,
+ mmDPGV0_PIPE_STUTTER_CONTROL,
+@@ -832,7 +832,7 @@ static void program_stutter_watermark_l(
+
+ static void program_stutter_watermark_c(
+ const struct dc_context *ctx,
+- struct bw_watermarks marks)
++ struct dce_watermarks marks)
+ {
+ program_stutter_watermark(ctx,
+ mmDPGV1_PIPE_STUTTER_CONTROL,
+@@ -844,7 +844,7 @@ static void program_nbp_watermark(
+ const struct dc_context *ctx,
+ const uint32_t wm_mask_ctrl_addr,
+ const uint32_t nbp_pstate_ctrl_addr,
+- struct bw_watermarks marks)
++ struct dce_watermarks marks)
+ {
+ uint32_t value;
+
+@@ -926,7 +926,7 @@ static void program_nbp_watermark(
+
+ static void program_nbp_watermark_l(
+ const struct dc_context *ctx,
+- struct bw_watermarks marks)
++ struct dce_watermarks marks)
+ {
+ program_nbp_watermark(ctx,
+ mmDPGV0_WATERMARK_MASK_CONTROL,
+@@ -936,7 +936,7 @@ static void program_nbp_watermark_l(
+
+ static void program_nbp_watermark_c(
+ const struct dc_context *ctx,
+- struct bw_watermarks marks)
++ struct dce_watermarks marks)
+ {
+ program_nbp_watermark(ctx,
+ mmDPGV1_WATERMARK_MASK_CONTROL,
+@@ -946,9 +946,9 @@ static void program_nbp_watermark_c(
+
+ void dce110_mem_input_v_program_display_marks(
+ struct mem_input *mem_input,
+- struct bw_watermarks nbp,
+- struct bw_watermarks stutter,
+- struct bw_watermarks urgent,
++ struct dce_watermarks nbp,
++ struct dce_watermarks stutter,
++ struct dce_watermarks urgent,
+ uint32_t total_dest_line_time_ns)
+ {
+ program_urgency_watermark_l(
+@@ -968,9 +968,9 @@ void dce110_mem_input_v_program_display_marks(
+
+ void dce110_mem_input_program_chroma_display_marks(
+ struct mem_input *mem_input,
+- struct bw_watermarks nbp,
+- struct bw_watermarks stutter,
+- struct bw_watermarks urgent,
++ struct dce_watermarks nbp,
++ struct dce_watermarks stutter,
++ struct dce_watermarks urgent,
+ uint32_t total_dest_line_time_ns)
+ {
+ program_urgency_watermark_c(
+diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.h
+index 44cf066..b2667ee 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.h
++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.h
+@@ -38,9 +38,9 @@ bool dce110_mem_input_v_construct(
+ */
+ void dce110_mem_input_v_program_display_marks(
+ struct mem_input *mem_input,
+- struct bw_watermarks nbp,
+- struct bw_watermarks stutter,
+- struct bw_watermarks urgent,
++ struct dce_watermarks nbp,
++ struct dce_watermarks stutter,
++ struct dce_watermarks urgent,
+ uint32_t total_dest_line_time_ns);
+
+ /*
+diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+index 5b2b41e..041d119 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+@@ -875,9 +875,8 @@ bool dce110_validate_bandwidth(
+ &dc->bw_vbios,
+ context->res_ctx.pipe_ctx,
+ dc->res_pool->pipe_count,
+- &context->bw_results))
++ &context->bw.dce))
+ result = true;
+- context->dispclk_khz = context->bw_results.dispclk_khz;
+
+ if (!result)
+ dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_VALIDATION,
+@@ -887,8 +886,8 @@ bool dce110_validate_bandwidth(
+ context->streams[0]->public.timing.v_addressable,
+ context->streams[0]->public.timing.pix_clk_khz);
+
+- if (memcmp(&dc->current_context->bw_results,
+- &context->bw_results, sizeof(context->bw_results))) {
++ if (memcmp(&dc->current_context->bw.dce,
++ &context->bw.dce, sizeof(context->bw.dce))) {
+ struct log_entry log_entry;
+ dm_logger_open(
+ dc->ctx->logger,
+@@ -898,43 +897,43 @@ bool dce110_validate_bandwidth(
+ "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
+ "stutMark_b: %d stutMark_a: %d\n",
+ __func__,
+- context->bw_results.nbp_state_change_wm_ns[0].b_mark,
+- context->bw_results.nbp_state_change_wm_ns[0].a_mark,
+- context->bw_results.urgent_wm_ns[0].b_mark,
+- context->bw_results.urgent_wm_ns[0].a_mark,
+- context->bw_results.stutter_exit_wm_ns[0].b_mark,
+- context->bw_results.stutter_exit_wm_ns[0].a_mark);
++ context->bw.dce.nbp_state_change_wm_ns[0].b_mark,
++ context->bw.dce.nbp_state_change_wm_ns[0].a_mark,
++ context->bw.dce.urgent_wm_ns[0].b_mark,
++ context->bw.dce.urgent_wm_ns[0].a_mark,
++ context->bw.dce.stutter_exit_wm_ns[0].b_mark,
++ context->bw.dce.stutter_exit_wm_ns[0].a_mark);
+ dm_logger_append(&log_entry,
+ "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
+ "stutMark_b: %d stutMark_a: %d\n",
+- context->bw_results.nbp_state_change_wm_ns[1].b_mark,
+- context->bw_results.nbp_state_change_wm_ns[1].a_mark,
+- context->bw_results.urgent_wm_ns[1].b_mark,
+- context->bw_results.urgent_wm_ns[1].a_mark,
+- context->bw_results.stutter_exit_wm_ns[1].b_mark,
+- context->bw_results.stutter_exit_wm_ns[1].a_mark);
++ context->bw.dce.nbp_state_change_wm_ns[1].b_mark,
++ context->bw.dce.nbp_state_change_wm_ns[1].a_mark,
++ context->bw.dce.urgent_wm_ns[1].b_mark,
++ context->bw.dce.urgent_wm_ns[1].a_mark,
++ context->bw.dce.stutter_exit_wm_ns[1].b_mark,
++ context->bw.dce.stutter_exit_wm_ns[1].a_mark);
+ dm_logger_append(&log_entry,
+ "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
+ "stutMark_b: %d stutMark_a: %d stutter_mode_enable: %d\n",
+- context->bw_results.nbp_state_change_wm_ns[2].b_mark,
+- context->bw_results.nbp_state_change_wm_ns[2].a_mark,
+- context->bw_results.urgent_wm_ns[2].b_mark,
+- context->bw_results.urgent_wm_ns[2].a_mark,
+- context->bw_results.stutter_exit_wm_ns[2].b_mark,
+- context->bw_results.stutter_exit_wm_ns[2].a_mark,
+- context->bw_results.stutter_mode_enable);
++ context->bw.dce.nbp_state_change_wm_ns[2].b_mark,
++ context->bw.dce.nbp_state_change_wm_ns[2].a_mark,
++ context->bw.dce.urgent_wm_ns[2].b_mark,
++ context->bw.dce.urgent_wm_ns[2].a_mark,
++ context->bw.dce.stutter_exit_wm_ns[2].b_mark,
++ context->bw.dce.stutter_exit_wm_ns[2].a_mark,
++ context->bw.dce.stutter_mode_enable);
+ dm_logger_append(&log_entry,
+ "cstate: %d pstate: %d nbpstate: %d sync: %d dispclk: %d\n"
+ "sclk: %d sclk_sleep: %d yclk: %d blackout_recovery_time_us: %d\n",
+- context->bw_results.cpuc_state_change_enable,
+- context->bw_results.cpup_state_change_enable,
+- context->bw_results.nbp_state_change_enable,
+- context->bw_results.all_displays_in_sync,
+- context->bw_results.dispclk_khz,
+- context->bw_results.required_sclk,
+- context->bw_results.required_sclk_deep_sleep,
+- context->bw_results.required_yclk,
+- context->bw_results.blackout_recovery_time_us);
++ context->bw.dce.cpuc_state_change_enable,
++ context->bw.dce.cpup_state_change_enable,
++ context->bw.dce.nbp_state_change_enable,
++ context->bw.dce.all_displays_in_sync,
++ context->bw.dce.dispclk_khz,
++ context->bw.dce.sclk_khz,
++ context->bw.dce.sclk_deep_sleep_khz,
++ context->bw.dce.yclk_khz,
++ context->bw.dce.blackout_recovery_time_us);
+ dm_logger_close(&log_entry);
+ }
+ return result;
+diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
+index 18c1b89..0ed2616 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
+@@ -845,17 +845,16 @@ bool dce112_validate_bandwidth(
+ &dc->bw_vbios,
+ context->res_ctx.pipe_ctx,
+ dc->res_pool->pipe_count,
+- &context->bw_results))
++ &context->bw.dce))
+ result = true;
+- context->dispclk_khz = context->bw_results.dispclk_khz;
+
+ if (!result)
+ dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_VALIDATION,
+ "%s: Bandwidth validation failed!",
+ __func__);
+
+- if (memcmp(&dc->current_context->bw_results,
+- &context->bw_results, sizeof(context->bw_results))) {
++ if (memcmp(&dc->current_context->bw.dce,
++ &context->bw.dce, sizeof(context->bw.dce))) {
+ struct log_entry log_entry;
+ dm_logger_open(
+ dc->ctx->logger,
+@@ -865,43 +864,43 @@ bool dce112_validate_bandwidth(
+ "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
+ "stutMark_b: %d stutMark_a: %d\n",
+ __func__,
+- context->bw_results.nbp_state_change_wm_ns[0].b_mark,
+- context->bw_results.nbp_state_change_wm_ns[0].a_mark,
+- context->bw_results.urgent_wm_ns[0].b_mark,
+- context->bw_results.urgent_wm_ns[0].a_mark,
+- context->bw_results.stutter_exit_wm_ns[0].b_mark,
+- context->bw_results.stutter_exit_wm_ns[0].a_mark);
++ context->bw.dce.nbp_state_change_wm_ns[0].b_mark,
++ context->bw.dce.nbp_state_change_wm_ns[0].a_mark,
++ context->bw.dce.urgent_wm_ns[0].b_mark,
++ context->bw.dce.urgent_wm_ns[0].a_mark,
++ context->bw.dce.stutter_exit_wm_ns[0].b_mark,
++ context->bw.dce.stutter_exit_wm_ns[0].a_mark);
+ dm_logger_append(&log_entry,
+ "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
+ "stutMark_b: %d stutMark_a: %d\n",
+- context->bw_results.nbp_state_change_wm_ns[1].b_mark,
+- context->bw_results.nbp_state_change_wm_ns[1].a_mark,
+- context->bw_results.urgent_wm_ns[1].b_mark,
+- context->bw_results.urgent_wm_ns[1].a_mark,
+- context->bw_results.stutter_exit_wm_ns[1].b_mark,
+- context->bw_results.stutter_exit_wm_ns[1].a_mark);
++ context->bw.dce.nbp_state_change_wm_ns[1].b_mark,
++ context->bw.dce.nbp_state_change_wm_ns[1].a_mark,
++ context->bw.dce.urgent_wm_ns[1].b_mark,
++ context->bw.dce.urgent_wm_ns[1].a_mark,
++ context->bw.dce.stutter_exit_wm_ns[1].b_mark,
++ context->bw.dce.stutter_exit_wm_ns[1].a_mark);
+ dm_logger_append(&log_entry,
+ "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
+ "stutMark_b: %d stutMark_a: %d stutter_mode_enable: %d\n",
+- context->bw_results.nbp_state_change_wm_ns[2].b_mark,
+- context->bw_results.nbp_state_change_wm_ns[2].a_mark,
+- context->bw_results.urgent_wm_ns[2].b_mark,
+- context->bw_results.urgent_wm_ns[2].a_mark,
+- context->bw_results.stutter_exit_wm_ns[2].b_mark,
+- context->bw_results.stutter_exit_wm_ns[2].a_mark,
+- context->bw_results.stutter_mode_enable);
++ context->bw.dce.nbp_state_change_wm_ns[2].b_mark,
++ context->bw.dce.nbp_state_change_wm_ns[2].a_mark,
++ context->bw.dce.urgent_wm_ns[2].b_mark,
++ context->bw.dce.urgent_wm_ns[2].a_mark,
++ context->bw.dce.stutter_exit_wm_ns[2].b_mark,
++ context->bw.dce.stutter_exit_wm_ns[2].a_mark,
++ context->bw.dce.stutter_mode_enable);
+ dm_logger_append(&log_entry,
+ "cstate: %d pstate: %d nbpstate: %d sync: %d dispclk: %d\n"
+ "sclk: %d sclk_sleep: %d yclk: %d blackout_recovery_time_us: %d\n",
+- context->bw_results.cpuc_state_change_enable,
+- context->bw_results.cpup_state_change_enable,
+- context->bw_results.nbp_state_change_enable,
+- context->bw_results.all_displays_in_sync,
+- context->bw_results.dispclk_khz,
+- context->bw_results.required_sclk,
+- context->bw_results.required_sclk_deep_sleep,
+- context->bw_results.required_yclk,
+- context->bw_results.blackout_recovery_time_us);
++ context->bw.dce.cpuc_state_change_enable,
++ context->bw.dce.cpup_state_change_enable,
++ context->bw.dce.nbp_state_change_enable,
++ context->bw.dce.all_displays_in_sync,
++ context->bw.dce.dispclk_khz,
++ context->bw.dce.sclk_khz,
++ context->bw.dce.sclk_deep_sleep_khz,
++ context->bw.dce.yclk_khz,
++ context->bw.dce.blackout_recovery_time_us);
+ dm_logger_close(&log_entry);
+ }
+ return result;
+diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
+index 0aa128e..5735914 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
+@@ -781,8 +781,8 @@ bool dce80_validate_bandwidth(
+ struct validate_context *context)
+ {
+ /* TODO implement when needed but for now hardcode max value*/
+- context->dispclk_khz = 681000;
+- context->bw_results.required_yclk = 250000 * MEMORY_TYPE_MULTIPLIER;
++ context->bw.dce.dispclk_khz = 681000;
++ context->bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER;
+
+ return true;
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+index 41a6fa5..a62c4e7 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+@@ -1428,7 +1428,7 @@ static void dcn10_power_on_fe(
+ enable_dcfclk(dc->ctx,
+ pipe_ctx->pipe_idx,
+ pipe_ctx->pix_clk_params.requested_pix_clk,
+- context->dppclk_div);
++ context->bw.dcn.calc_clk.dppclk_div);
+
+ if (dc_surface) {
+ dm_logger_write(dc->ctx->logger, LOG_DC,
+@@ -1530,7 +1530,7 @@ static void update_dchubp_dpp(
+ dc->ctx,
+ pipe_ctx->pipe_idx,
+ pipe_ctx->pix_clk_params.requested_pix_clk,
+- context->dppclk_div);
++ context->bw.dcn.calc_clk.dppclk_div);
+
+ select_vtg(dc->ctx, pipe_ctx->pipe_idx, pipe_ctx->tg->inst);
+
+@@ -1649,7 +1649,7 @@ static void program_all_pipe_in_tree(
+ if (pipe_ctx->top_pipe == NULL) {
+ /* watermark is for all pipes */
+ pipe_ctx->mi->funcs->program_watermarks(
+- pipe_ctx->mi, &context->watermarks, ref_clk_mhz);
++ pipe_ctx->mi, &context->bw.dcn.watermarks, ref_clk_mhz);
+ lock_otg_master_update(dc->ctx, pipe_ctx->tg->inst);
+ }
+
+@@ -1679,16 +1679,16 @@ static void dcn10_pplib_apply_display_requirements(
+
+ pp_display_cfg->all_displays_in_sync = false;/*todo*/
+ pp_display_cfg->nb_pstate_switch_disable = false;
+- pp_display_cfg->min_engine_clock_khz = context->dcfclk_khz;
+- pp_display_cfg->min_memory_clock_khz = context->fclk_khz;
+- pp_display_cfg->min_engine_clock_deep_sleep_khz = context->dcfclk_deep_sleep_khz;
+- pp_display_cfg->min_dcfc_deep_sleep_clock_khz = context->dcfclk_deep_sleep_khz;
++ pp_display_cfg->min_engine_clock_khz = context->bw.dcn.calc_clk.dcfclk_khz;
++ pp_display_cfg->min_memory_clock_khz = context->bw.dcn.calc_clk.fclk_khz;
++ pp_display_cfg->min_engine_clock_deep_sleep_khz = context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz;
++ pp_display_cfg->min_dcfc_deep_sleep_clock_khz = context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz;
+ pp_display_cfg->avail_mclk_switch_time_us =
+- context->dram_ccm_us > 0 ? context->dram_ccm_us : 0;
++ context->bw.dcn.calc_clk.dram_ccm_us > 0 ? context->bw.dcn.calc_clk.dram_ccm_us : 0;
+ pp_display_cfg->avail_mclk_switch_time_in_disp_active_us =
+- context->min_active_dram_ccm_us > 0 ? context->min_active_dram_ccm_us : 0;
+- pp_display_cfg->min_dcfclock_khz = context->dcfclk_khz;
+- pp_display_cfg->disp_clk_khz = context->dispclk_khz;
++ context->bw.dcn.calc_clk.min_active_dram_ccm_us > 0 ? context->bw.dcn.calc_clk.min_active_dram_ccm_us : 0;
++ pp_display_cfg->min_dcfclock_khz = context->bw.dcn.calc_clk.dcfclk_khz;
++ pp_display_cfg->disp_clk_khz = context->bw.dcn.calc_clk.dispclk_khz;
+ dce110_fill_display_configs(context, pp_display_cfg);
+
+ if (memcmp(&dc->prev_display_config, pp_display_cfg, sizeof(
+@@ -1755,22 +1755,22 @@ static void dcn10_set_bandwidth(
+ if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
+ return;
+
+- if (decrease_allowed || context->dispclk_khz > dc->current_context->dispclk_khz) {
++ if (decrease_allowed || context->bw.dcn.calc_clk.dispclk_khz > dc->current_context->bw.dcn.calc_clk.dispclk_khz) {
+ dc->res_pool->display_clock->funcs->set_clock(
+ dc->res_pool->display_clock,
+- context->dispclk_khz);
+- dc->current_context->dispclk_khz = context->dispclk_khz;
++ context->bw.dcn.calc_clk.dispclk_khz);
++ dc->current_context->bw.dcn.calc_clk.dispclk_khz = context->bw.dcn.calc_clk.dispclk_khz;
+ }
+- if (decrease_allowed || context->dcfclk_khz > dc->current_context->dcfclk_khz) {
++ if (decrease_allowed || context->bw.dcn.calc_clk.dcfclk_khz > dc->current_context->bw.dcn.calc_clk.dcfclk_khz) {
+ clock.clk_type = DM_PP_CLOCK_TYPE_DCFCLK;
+- clock.clocks_in_khz = context->dcfclk_khz;
++ clock.clocks_in_khz = context->bw.dcn.calc_clk.dcfclk_khz;
+ dm_pp_apply_clock_for_voltage_request(dc->ctx, &clock);
+ }
+- if (decrease_allowed || context->fclk_khz > dc->current_context->fclk_khz) {
++ if (decrease_allowed || context->bw.dcn.calc_clk.fclk_khz > dc->current_context->bw.dcn.calc_clk.fclk_khz) {
+ clock.clk_type = DM_PP_CLOCK_TYPE_FCLK;
+- clock.clocks_in_khz = context->fclk_khz;
++ clock.clocks_in_khz = context->bw.dcn.calc_clk.fclk_khz;
+ dm_pp_apply_clock_for_voltage_request(dc->ctx, &clock);
+- dc->current_context->fclk_khz = clock.clocks_in_khz ;
++ dc->current_context->bw.dcn.calc_clk.fclk_khz = clock.clocks_in_khz;
+ }
+ dcn10_pplib_apply_display_requirements(dc, context);
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c
+index bf89608..50b2445 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c
+@@ -820,9 +820,9 @@ static void program_watermarks(
+
+ static void mem_input_program_display_marks(
+ struct mem_input *mem_input,
+- struct bw_watermarks nbp,
+- struct bw_watermarks stutter,
+- struct bw_watermarks urgent,
++ struct dce_watermarks nbp,
++ struct dce_watermarks stutter,
++ struct dce_watermarks urgent,
+ uint32_t total_dest_line_time_ns)
+ {
+ /* only for dce
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+index 919c663..52ac6d1 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+@@ -312,7 +312,48 @@ struct resource_context {
+ bool is_audio_acquired[MAX_PIPES];
+ uint8_t clock_source_ref_count[MAX_CLOCK_SOURCES];
+ uint8_t dp_clock_source_ref_count;
+- };
++};
++
++struct dce_bw_output {
++ bool cpuc_state_change_enable;
++ bool cpup_state_change_enable;
++ bool stutter_mode_enable;
++ bool nbp_state_change_enable;
++ bool all_displays_in_sync;
++ struct dce_watermarks urgent_wm_ns[MAX_PIPES];
++ struct dce_watermarks stutter_exit_wm_ns[MAX_PIPES];
++ struct dce_watermarks nbp_state_change_wm_ns[MAX_PIPES];
++ int sclk_khz;
++ int sclk_deep_sleep_khz;
++ int yclk_khz;
++ int dispclk_khz;
++ int blackout_recovery_time_us;
++};
++
++#ifdef CONFIG_DRM_AMD_DC_DCN1_0
++struct dcn_bw_clocks {
++ int dispclk_khz;
++ bool dppclk_div;
++ int dcfclk_khz;
++ int dcfclk_deep_sleep_khz;
++ int fclk_khz;
++ int dram_ccm_us;
++ int min_active_dram_ccm_us;
++};
++
++struct dcn_bw_output {
++ struct dcn_bw_clocks cur_clk;
++ struct dcn_bw_clocks calc_clk;
++ struct dcn_watermark_set watermarks;
++};
++#endif
++
++union bw_context {
++#ifdef CONFIG_DRM_AMD_DC_DCN1_0
++ struct dcn_bw_output dcn;
++#endif
++ struct dce_bw_output dce;
++};
+
+ struct validate_context {
+ struct core_stream *streams[MAX_PIPES];
+@@ -322,20 +363,11 @@ struct validate_context {
+ struct resource_context res_ctx;
+
+ /* The output from BW and WM calculations. */
+- struct bw_calcs_output bw_results;
++ union bw_context bw;
++
+ /* Note: these are big structures, do *not* put on stack! */
+ struct dm_pp_display_configuration pp_display_cfg;
+- int dispclk_khz;
+ #ifdef CONFIG_DRM_AMD_DC_DCN1_0
+- int dppclk_khz;
+- bool dppclk_div;
+- int dcfclk_khz;
+- int dcfclk_deep_sleep_khz;
+- int socclk_khz;
+- int fclk_khz;
+- int dram_ccm_us;
+- int min_active_dram_ccm_us;
+- struct dcn_watermark_set watermarks;
+ struct dcn_bw_internal_vars dcn_bw_vars;
+ #endif
+ };
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h b/drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h
+index 580dee95..36c48f7 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h
+@@ -35,6 +35,7 @@
+ struct pipe_ctx;
+ struct core_dc;
+ struct validate_context;
++struct dce_bw_output;
+
+ enum bw_calcs_version {
+ BW_CALCS_VERSION_INVALID,
+@@ -454,32 +455,6 @@ struct bw_calcs_data {
+ struct bw_fixed dmif_required_sclk_for_urgent_latency[6];
+ };
+
+-/*******************************************************************************
+- * Output data structures.
+- ******************************************************************************/
+-struct bw_watermarks {
+- uint32_t a_mark;
+- uint32_t b_mark;
+- uint32_t c_mark;
+- uint32_t d_mark;
+-};
+-
+-struct bw_calcs_output {
+- bool cpuc_state_change_enable;
+- bool cpup_state_change_enable;
+- bool stutter_mode_enable;
+- bool nbp_state_change_enable;
+- bool all_displays_in_sync;
+- struct bw_watermarks urgent_wm_ns[6];
+- struct bw_watermarks stutter_exit_wm_ns[6];
+- struct bw_watermarks nbp_state_change_wm_ns[6];
+- uint32_t required_sclk;
+- uint32_t required_sclk_deep_sleep;
+- uint32_t required_yclk;
+- uint32_t dispclk_khz;
+- int blackout_recovery_time_us;
+-};
+-
+ /**
+ * Initialize structures with data which will NOT change at runtime.
+ */
+@@ -500,7 +475,7 @@ bool bw_calcs(
+ const struct bw_calcs_vbios *vbios,
+ const struct pipe_ctx *pipe,
+ int pipe_count,
+- struct bw_calcs_output *calcs_output);
++ struct dce_bw_output *calcs_output);
+
+ #endif /* __BANDWIDTH_CALCS_H__ */
+
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
+index 0880ce9..c4aea24 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
+@@ -27,7 +27,6 @@
+
+ #include "dc.h"
+ #include "include/grph_object_id.h"
+-#include "inc/dce_calcs.h"
+
+ #include "dce/dce_mem_input.h" /* temporary */
+
+@@ -55,6 +54,13 @@ struct dcn_watermark_set {
+
+ #endif
+
++struct dce_watermarks {
++ int a_mark;
++ int b_mark;
++ int c_mark;
++ int d_mark;
++};
++
+ struct stutter_modes {
+ bool enhanced;
+ bool quad_dmif_buffer;
+@@ -95,16 +101,16 @@ struct mem_input_funcs {
+
+ void (*mem_input_program_display_marks)(
+ struct mem_input *mem_input,
+- struct bw_watermarks nbp,
+- struct bw_watermarks stutter,
+- struct bw_watermarks urgent,
++ struct dce_watermarks nbp,
++ struct dce_watermarks stutter,
++ struct dce_watermarks urgent,
+ uint32_t total_dest_line_time_ns);
+
+ void (*mem_input_program_chroma_display_marks)(
+ struct mem_input *mem_input,
+- struct bw_watermarks nbp,
+- struct bw_watermarks stutter,
+- struct bw_watermarks urgent,
++ struct dce_watermarks nbp,
++ struct dce_watermarks stutter,
++ struct dce_watermarks urgent,
+ uint32_t total_dest_line_time_ns);
+
+ void (*allocate_mem_input)(
+--
+2.7.4
+