diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/0346-drm-amd-display-Add-support-for-programming-stereo-s.patch')
-rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.14.71/0346-drm-amd-display-Add-support-for-programming-stereo-s.patch | 205 |
1 files changed, 205 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/0346-drm-amd-display-Add-support-for-programming-stereo-s.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/0346-drm-amd-display-Add-support-for-programming-stereo-s.patch new file mode 100644 index 00000000..6e75eb55 --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/0346-drm-amd-display-Add-support-for-programming-stereo-s.patch @@ -0,0 +1,205 @@ +From 5fcf600b3de60b9cfd2e399ef92de5f884ce5f2d Mon Sep 17 00:00:00 2001 +From: Vitaly Prosyak <vitaly.prosyak@amd.com> +Date: Fri, 31 Mar 2017 15:25:04 -0500 +Subject: [PATCH 0346/4131] drm/amd/display: Add support for programming stereo + sync + +Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com> +Acked-by: Harry Wentland <Harry.Wentland@amd.com> +Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/display/dc/dce/dce_opp.h | 11 ++++++++--- + drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c | 12 ++++++++++++ + drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h | 14 ++++++++++++-- + .../gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 7 +++++++ + drivers/gpu/drm/amd/display/dc/inc/hw/opp.h | 5 +++++ + drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h | 5 +++++ + 6 files changed, 49 insertions(+), 5 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h +index 03ce9ba..e5045d2 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h ++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h +@@ -174,7 +174,8 @@ enum dce110_opp_reg_type { + OPP_SF(DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh),\ + OPP_SF(DCFE_MEM_PWR_STATUS, DCP_REGAMMA_MEM_PWR_STATE, mask_sh),\ + OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh),\ +- OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh) ++ OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh),\ ++ OPP_SF(FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh) + + #define OPP_COMMON_MASK_SH_LIST_DCE_100(mask_sh)\ + OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh),\ +@@ -182,7 +183,8 @@ enum dce110_opp_reg_type { + OPP_SF(DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh),\ + OPP_SF(DCFE_MEM_PWR_STATUS, DCP_REGAMMA_MEM_PWR_STATE, mask_sh),\ + OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh),\ +- OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh) ++ OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh),\ ++ OPP_SF(FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh) + + #define OPP_COMMON_MASK_SH_LIST_DCE_112(mask_sh)\ + OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh),\ +@@ -195,7 +197,8 @@ enum dce110_opp_reg_type { + OPP_SF(FMT_CONTROL, FMT_420_PIXEL_PHASE_LOCKED, mask_sh),\ + OPP_SF(FMT_CONTROL, FMT_CBCR_BIT_REDUCTION_BYPASS, mask_sh),\ + OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh),\ +- OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh) ++ OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh),\ ++ OPP_SF(FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh) + + #define OPP_COMMON_MASK_SH_LIST_DCE_80(mask_sh)\ + OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh),\ +@@ -244,6 +247,7 @@ enum dce110_opp_reg_type { + OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN, mask_sh),\ + OPP_SF(FMT0_FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh),\ + OPP_SF(FMT0_FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh),\ ++ OPP_SF(FMT0_FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh),\ + OPP_SF(FMT0_FMT_DITHER_RAND_R_SEED, FMT_RAND_R_SEED, mask_sh),\ + OPP_SF(FMT0_FMT_DITHER_RAND_G_SEED, FMT_RAND_G_SEED, mask_sh),\ + OPP_SF(FMT0_FMT_DITHER_RAND_B_SEED, FMT_RAND_B_SEED, mask_sh),\ +@@ -308,6 +312,7 @@ enum dce110_opp_reg_type { + type FMT_RGB_RANDOM_ENABLE; \ + type FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX; \ + type FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP; \ ++ type FMT_STEREOSYNC_OVERRIDE; \ + type FMT_RAND_R_SEED; \ + type FMT_RAND_G_SEED; \ + type FMT_RAND_B_SEED; \ +diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c +index f3e1a29..9713def 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c ++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c +@@ -1286,6 +1286,17 @@ void dce110_se_hdmi_audio_disable( + dce110_se_enable_audio_clock(enc, false); + } + ++ ++static void setup_stereo_sync( ++ struct stream_encoder *enc, ++ int tg_inst, bool enable) ++{ ++ struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); ++ REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, tg_inst); ++ REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, !enable); ++} ++ ++ + static const struct stream_encoder_funcs dce110_str_enc_funcs = { + .dp_set_stream_attribute = + dce110_stream_encoder_dp_set_stream_attribute, +@@ -1316,6 +1327,7 @@ static const struct stream_encoder_funcs dce110_str_enc_funcs = { + + .hdmi_audio_setup = dce110_se_hdmi_audio_setup, + .hdmi_audio_disable = dce110_se_hdmi_audio_disable, ++ .setup_stereo_sync = setup_stereo_sync, + }; + + bool dce110_stream_encoder_construct( +diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h +index c2f4050..850e12a 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h ++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h +@@ -151,6 +151,8 @@ + SE_SF(DP_VID_N, DP_VID_N, mask_sh),\ + SE_SF(DP_VID_M, DP_VID_M, mask_sh),\ + SE_SF(DIG_FE_CNTL, DIG_START, mask_sh),\ ++ SE_SF(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, mask_sh),\ ++ SE_SF(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, mask_sh),\ + SE_SF(AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, mask_sh),\ + SE_SF(AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, mask_sh),\ + SE_SF(HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, mask_sh),\ +@@ -265,7 +267,9 @@ + SE_SF(DIG0_AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, mask_sh),\ + SE_SF(DIG0_HDMI_CONTROL, HDMI_CLOCK_CHANNEL_RATE, mask_sh),\ + SE_SF(DIG0_DIG_FE_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\ +- SE_SF(DIG0_DIG_FE_CNTL, TMDS_COLOR_FORMAT, mask_sh) ++ SE_SF(DIG0_DIG_FE_CNTL, TMDS_COLOR_FORMAT, mask_sh),\ ++ SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, mask_sh),\ ++ SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, mask_sh) + + #define SE_COMMON_MASK_SH_LIST_SOC(mask_sh)\ + SE_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh) +@@ -281,7 +285,9 @@ + SE_SF(HDMI_CONTROL, HDMI_CLOCK_CHANNEL_RATE, mask_sh),\ + SE_SF(HDMI_CONTROL, HDMI_DATA_SCRAMBLE_EN, mask_sh),\ + SE_SF(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\ +- SE_SF(DIG_FE_CNTL, TMDS_COLOR_FORMAT, mask_sh) ++ SE_SF(DIG_FE_CNTL, TMDS_COLOR_FORMAT, mask_sh),\ ++ SE_SF(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, mask_sh),\ ++ SE_SF(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, mask_sh) + + #define SE_COMMON_MASK_SH_LIST_DCE112(mask_sh)\ + SE_COMMON_MASK_SH_LIST_DCE_COMMON(mask_sh),\ +@@ -416,6 +422,8 @@ struct dce_stream_encoder_shift { + uint8_t AFMT_AUDIO_CLOCK_EN; + uint8_t TMDS_PIXEL_ENCODING; + uint8_t TMDS_COLOR_FORMAT; ++ uint8_t DIG_STEREOSYNC_SELECT; ++ uint8_t DIG_STEREOSYNC_GATE_EN; + uint8_t DP_DB_DISABLE; + uint8_t DP_MSA_MISC0; + uint8_t DP_MSA_HTOTAL; +@@ -543,6 +551,8 @@ struct dce_stream_encoder_mask { + uint32_t AFMT_AUDIO_SAMPLE_SEND; + uint32_t AFMT_AUDIO_CLOCK_EN; + uint32_t TMDS_PIXEL_ENCODING; ++ uint32_t DIG_STEREOSYNC_SELECT; ++ uint32_t DIG_STEREOSYNC_GATE_EN; + uint32_t TMDS_COLOR_FORMAT; + uint32_t DP_DB_DISABLE; + uint32_t DP_MSA_MISC0; +diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +index 1401331..6bf03d6 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c ++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +@@ -1056,6 +1056,13 @@ static enum dc_status apply_single_controller_ctx_to_hw( + stream->sink->link->link_enc, + pipe_ctx->stream->signal); + ++ if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL) ++ pipe_ctx->stream_enc->funcs->setup_stereo_sync( ++ pipe_ctx->stream_enc, ++ pipe_ctx->tg->inst, ++ stream->public.timing.timing_3d_format != TIMING_3D_FORMAT_NONE); ++ ++ + /*vbios crtc_source_selection and encoder_setup will override fmt_C*/ + pipe_ctx->opp->funcs->opp_program_fmt( + pipe_ctx->opp, +diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h +index e01b831..521bd21e 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h +@@ -316,6 +316,11 @@ struct opp_funcs { + struct hw_adjustment_range *range); + + void (*opp_destroy)(struct output_pixel_processor **opp); ++ ++ void (*opp_set_stereo_polarity)( ++ struct output_pixel_processor *opp, ++ bool enable, ++ bool rightEyePolarity); + }; + + #endif +diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h +index 674bebf..9fb27bd 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h +@@ -118,6 +118,11 @@ struct stream_encoder_funcs { + + void (*hdmi_audio_disable) ( + struct stream_encoder *enc); ++ ++ void (*setup_stereo_sync) ( ++ struct stream_encoder *enc, ++ int tg_inst, ++ bool enable); + }; + + #endif /* STREAM_ENCODER_H_ */ +-- +2.7.4 + |