diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/0253-drm-amd-display-clean-up-and-simply-locking-logic.patch')
-rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.14.71/0253-drm-amd-display-clean-up-and-simply-locking-logic.patch | 115 |
1 files changed, 115 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/0253-drm-amd-display-clean-up-and-simply-locking-logic.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/0253-drm-amd-display-clean-up-and-simply-locking-logic.patch new file mode 100644 index 00000000..f2f4b5e5 --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/0253-drm-amd-display-clean-up-and-simply-locking-logic.patch @@ -0,0 +1,115 @@ +From d46415be88363822d5cfa3243e3b0a6429480d75 Mon Sep 17 00:00:00 2001 +From: Tony Cheng <tony.cheng@amd.com> +Date: Tue, 28 Feb 2017 21:30:32 -0500 +Subject: [PATCH 0253/4131] drm/amd/display: clean up and simply locking logic + +always take update lock instead of using HW built in update +lock trigger with write to primary_addr_lo. + +we will be a little more inefficient with the extra registers +write to lock, but this simplify code and make it always correct. + +Will revisit locking optimization once update sequence mature + +Signed-off-by: Tony Cheng <tony.cheng@amd.com> +Acked-by: Harry Wentland <Harry.Wentland@amd.com> +Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/display/dc/core/dc.c | 32 +++++++---------------- + drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c | 3 +-- + drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 1 - + 3 files changed, 11 insertions(+), 25 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c +index efe50fd..8f871924 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c +@@ -1321,22 +1321,22 @@ void dc_update_surfaces_for_stream(struct dc *dc, + + if (pipe_ctx->surface != surface) + continue; +- /*lock all the MCPP if blnd is enable for DRR*/ +- if ((update_type == UPDATE_TYPE_FAST && +- (dc_stream->freesync_ctx.enabled == true && +- surface_count != context->res_ctx.pool->pipe_count)) && +- !pipe_ctx->tg->funcs->is_blanked(pipe_ctx->tg)) { +- lock_mask = PIPE_LOCK_CONTROL_MPCC_ADDR; ++ ++ if (update_type == UPDATE_TYPE_FULL) { ++ /* only apply for top pipe */ ++ if (!pipe_ctx->top_pipe) { ++ core_dc->hwss.apply_ctx_for_surface(core_dc, ++ surface, context); ++ context_timing_trace(dc, &context->res_ctx); ++ } + } + +- if (update_type != UPDATE_TYPE_FAST && +- !pipe_ctx->tg->funcs->is_blanked(pipe_ctx->tg)) { ++ if (!pipe_ctx->tg->funcs->is_blanked(pipe_ctx->tg)) { + lock_mask = PIPE_LOCK_CONTROL_GRAPHICS | + PIPE_LOCK_CONTROL_SCL | + PIPE_LOCK_CONTROL_BLENDER | + PIPE_LOCK_CONTROL_MODE; +- } +- if (lock_mask != 0) { ++ + core_dc->hwss.pipe_control_lock( + core_dc, + pipe_ctx, +@@ -1344,15 +1344,6 @@ void dc_update_surfaces_for_stream(struct dc *dc, + true); + } + +- if (update_type == UPDATE_TYPE_FULL) { +- /* only apply for top pipe */ +- if (!pipe_ctx->top_pipe) { +- core_dc->hwss.apply_ctx_for_surface(core_dc, +- surface, context); +- context_timing_trace(dc, &context->res_ctx); +- } +- } +- + if (updates[i].flip_addr) + core_dc->hwss.update_plane_addr(core_dc, pipe_ctx); + +@@ -1382,9 +1373,6 @@ void dc_update_surfaces_for_stream(struct dc *dc, + } + } + +- if ((update_type == UPDATE_TYPE_FAST) && lock_mask == 0) +- return; +- + for (i = context->res_ctx.pool->pipe_count - 1; i >= 0; i--) { + struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; + +diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c +index 1e1d60a..89a8274 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c ++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c +@@ -52,8 +52,7 @@ void dce_pipe_control_lock(struct core_dc *dc, + uint32_t lock_val = lock ? 1 : 0; + uint32_t dcp_grph, scl, blnd, update_lock_mode, val; + struct dce_hwseq *hws = dc->hwseq; +- if (control_mask & PIPE_LOCK_CONTROL_MPCC_ADDR) +- return; ++ + val = REG_GET_4(BLND_V_UPDATE_LOCK[pipe->pipe_idx], + BLND_DCP_GRPH_V_UPDATE_LOCK, &dcp_grph, + BLND_SCL_V_UPDATE_LOCK, &scl, +diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +index a902de5..612910e 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +@@ -39,7 +39,6 @@ enum pipe_lock_control { + PIPE_LOCK_CONTROL_BLENDER = 1 << 1, + PIPE_LOCK_CONTROL_SCL = 1 << 2, + PIPE_LOCK_CONTROL_MODE = 1 << 3, +- PIPE_LOCK_CONTROL_MPCC_ADDR = 1 << 4 + }; + + struct dce_hwseq_wa { +-- +2.7.4 + |