diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/0213-drm-amd-display-Fix-logic-that-causes-segfault-on-DP.patch')
| -rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.14.71/0213-drm-amd-display-Fix-logic-that-causes-segfault-on-DP.patch | 50 |
1 files changed, 50 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/0213-drm-amd-display-Fix-logic-that-causes-segfault-on-DP.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/0213-drm-amd-display-Fix-logic-that-causes-segfault-on-DP.patch new file mode 100644 index 00000000..f33e965f --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/0213-drm-amd-display-Fix-logic-that-causes-segfault-on-DP.patch @@ -0,0 +1,50 @@ +From ab3c97fd4649fcc42e1380229e8e05d4975616a9 Mon Sep 17 00:00:00 2001 +From: Zeyu Fan <Zeyu.Fan@amd.com> +Date: Mon, 13 Feb 2017 11:49:07 -0500 +Subject: [PATCH 0213/4131] drm/amd/display: Fix logic that causes segfault on + DP display. + +Signed-off-by: Zeyu Fan <Zeyu.Fan@amd.com> +Acked-by: Jordan Lazare <Jordan.Lazare@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + .../gpu/drm/amd/display/dc/dce/dce_clock_source.c | 22 ++++++++++++---------- + 1 file changed, 12 insertions(+), 10 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c +index 87eba4b..26742e0 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c ++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c +@@ -852,17 +852,19 @@ static bool dce110_program_pix_clk( + * during PLL Reset, but they do not have effect + * until SS_EN is asserted.*/ + if (clock_source->id != CLOCK_SOURCE_ID_EXTERNAL +- && pix_clk_params->flags.ENABLE_SS && !dc_is_dp_signal( +- pix_clk_params->signal_type)) { +- if (!enable_spread_spectrum(clk_src, +- pix_clk_params->signal_type, +- pll_settings)) +- return false; ++ && !dc_is_dp_signal(pix_clk_params->signal_type)) { ++ ++ if (pix_clk_params->flags.ENABLE_SS) ++ if (!enable_spread_spectrum(clk_src, ++ pix_clk_params->signal_type, ++ pll_settings)) ++ return false; ++ ++ /* Resync deep color DTO */ ++ dce110_program_pixel_clk_resync(clk_src, ++ pix_clk_params->signal_type, ++ pix_clk_params->color_depth); + } +- /* Resync deep color DTO */ +- dce110_program_pixel_clk_resync(clk_src, +- pix_clk_params->signal_type, +- pix_clk_params->color_depth); + + break; + case DCE_VERSION_11_2: +-- +2.7.4 + |