diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/0210-drm-amd-display-Fix-program-pix-clk-logic-to-unblock.patch')
-rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.14.71/0210-drm-amd-display-Fix-program-pix-clk-logic-to-unblock.patch | 43 |
1 files changed, 43 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/0210-drm-amd-display-Fix-program-pix-clk-logic-to-unblock.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/0210-drm-amd-display-Fix-program-pix-clk-logic-to-unblock.patch new file mode 100644 index 00000000..5844edbb --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/0210-drm-amd-display-Fix-program-pix-clk-logic-to-unblock.patch @@ -0,0 +1,43 @@ +From 479c28d43afaba61eceea04bbf39a51f059aa1f2 Mon Sep 17 00:00:00 2001 +From: Zeyu Fan <Zeyu.Fan@amd.com> +Date: Fri, 10 Feb 2017 11:59:31 -0500 +Subject: [PATCH 0210/4131] drm/amd/display: Fix program pix clk logic to + unblock deep color set. + +Signed-off-by: Zeyu Fan <Zeyu.Fan@amd.com> +Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> +Acked-by: Harry Wentland <Harry.Wentland@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c | 10 +++++----- + 1 file changed, 5 insertions(+), 5 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c +index a9f3921..87eba4b 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c ++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c +@@ -854,16 +854,16 @@ static bool dce110_program_pix_clk( + if (clock_source->id != CLOCK_SOURCE_ID_EXTERNAL + && pix_clk_params->flags.ENABLE_SS && !dc_is_dp_signal( + pix_clk_params->signal_type)) { +- + if (!enable_spread_spectrum(clk_src, + pix_clk_params->signal_type, + pll_settings)) + return false; +- /* Resync deep color DTO */ +- dce110_program_pixel_clk_resync(clk_src, +- pix_clk_params->signal_type, +- pix_clk_params->color_depth); + } ++ /* Resync deep color DTO */ ++ dce110_program_pixel_clk_resync(clk_src, ++ pix_clk_params->signal_type, ++ pix_clk_params->color_depth); ++ + break; + case DCE_VERSION_11_2: + if (clock_source->id != CLOCK_SOURCE_ID_DP_DTO) { +-- +2.7.4 + |