diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/0205-drm-amd-display-fix-psr-status-wait.patch')
-rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.14.71/0205-drm-amd-display-fix-psr-status-wait.patch | 106 |
1 files changed, 106 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/0205-drm-amd-display-fix-psr-status-wait.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/0205-drm-amd-display-fix-psr-status-wait.patch new file mode 100644 index 00000000..f7f2900a --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/0205-drm-amd-display-fix-psr-status-wait.patch @@ -0,0 +1,106 @@ +From 733a21b727e22e8c69abe5bb818d6ce2972961df Mon Sep 17 00:00:00 2001 +From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> +Date: Mon, 6 Feb 2017 15:07:19 -0500 +Subject: [PATCH 0205/4131] drm/amd/display: fix psr status wait + +Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> +Reviewed-by: Eagle Yeh <eagle.yeh@amd.com> +Acked-by: Harry Wentland <Harry.Wentland@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + .../gpu/drm/amd/display/dc/dce/dce_link_encoder.c | 18 +++++++++++++++--- + .../gpu/drm/amd/display/dc/dce/dce_link_encoder.h | 22 +++++++++++----------- + drivers/gpu/drm/amd/display/dc/dm_services.h | 2 +- + 3 files changed, 27 insertions(+), 15 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c +index 3847764..60fdf58 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c ++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c +@@ -38,6 +38,14 @@ + #include "dce/dce_11_0_sh_mask.h" + #include "dce/dce_11_0_enum.h" + ++#ifndef DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE__SHIFT ++#define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE__SHIFT 0xa ++#endif ++ ++#ifndef DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE_MASK ++#define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE_MASK 0x00000400L ++#endif ++ + #ifndef HPD0_DC_HPD_CONTROL__DC_HPD_EN_MASK + #define HPD0_DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000L + #endif +@@ -1557,15 +1565,19 @@ static void get_dmcu_psr_state(struct link_encoder *enc, uint32_t *psr_state) + + uint32_t count = 0; + uint32_t psrStateOffset = 0xf0; +- uint32_t value; ++ uint32_t value = -1; + + /* Enable write access to IRAM */ + REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 1); + +- do { ++ while (REG(DCI_MEM_PWR_STATUS) && value != 0 && count++ < 10) { + dm_delay_in_microseconds(ctx, 2); + REG_GET(DCI_MEM_PWR_STATUS, DMCU_IRAM_MEM_PWR_STATE, &value); +- } while (value != 0 && count++ < 10); ++ } ++ while (REG(DMU_MEM_PWR_CNTL) && value != 0 && count++ < 10) { ++ dm_delay_in_microseconds(ctx, 2); ++ REG_GET(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, &value); ++ } + + /* Write address to IRAM_RD_ADDR in DMCU_IRAM_RD_CTRL */ + REG_WRITE(DMCU_IRAM_RD_CTRL, psrStateOffset); +diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h +index 8a07665..d382a68 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h ++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h +@@ -72,17 +72,17 @@ + SRI(DP_DPHY_FAST_TRAINING, DP, id), \ + SRI(DP_SEC_CNTL1, DP, id) + +- #define LE_COMMON_REG_LIST(id)\ +- LE_COMMON_REG_LIST_BASE(id), \ +- SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \ +- SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \ +- SR(DCI_MEM_PWR_STATUS) +- +- #define LE_DCE110_REG_LIST(id)\ +- LE_COMMON_REG_LIST_BASE(id), \ +- SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \ +- SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \ +- SR(DCI_MEM_PWR_STATUS) ++#define LE_COMMON_REG_LIST(id)\ ++ LE_COMMON_REG_LIST_BASE(id), \ ++ SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \ ++ SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \ ++ SR(DCI_MEM_PWR_STATUS) ++ ++#define LE_DCE110_REG_LIST(id)\ ++ LE_COMMON_REG_LIST_BASE(id), \ ++ SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \ ++ SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \ ++ SR(DCI_MEM_PWR_STATUS) + + #define LE_DCE80_REG_LIST(id)\ + SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \ +diff --git a/drivers/gpu/drm/amd/display/dc/dm_services.h b/drivers/gpu/drm/amd/display/dc/dm_services.h +index 052a43a..73c0f1f 100644 +--- a/drivers/gpu/drm/amd/display/dc/dm_services.h ++++ b/drivers/gpu/drm/amd/display/dc/dm_services.h +@@ -103,7 +103,7 @@ static inline uint32_t dm_read_reg_func( + uint32_t value; + + if (address == 0) { +- DC_ERR("invalid register read. address = 0"); ++ DC_ERR("invalid register read; address = 0\n"); + return 0; + } + +-- +2.7.4 + |