diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/0190-drm-amd-display-Support-ABM-without-PPlib.patch')
| -rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.14.71/0190-drm-amd-display-Support-ABM-without-PPlib.patch | 138 |
1 files changed, 0 insertions, 138 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/0190-drm-amd-display-Support-ABM-without-PPlib.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/0190-drm-amd-display-Support-ABM-without-PPlib.patch deleted file mode 100644 index 6a258b8e..00000000 --- a/common/recipes-kernel/linux/linux-yocto-4.14.71/0190-drm-amd-display-Support-ABM-without-PPlib.patch +++ /dev/null @@ -1,138 +0,0 @@ -From 15e9a6385903e96f46a850d6c151f33706293cfa Mon Sep 17 00:00:00 2001 -From: Anthony Koo <Anthony.Koo@amd.com> -Date: Fri, 27 Jan 2017 17:22:46 -0500 -Subject: [PATCH 0190/4131] drm/amd/display: Support ABM without PPlib - -Fix problem with loading IRAM - -Signed-off-by: Anthony Koo <anthony.koo@amd.com> -Signed-off-by: Alex Deucher <alexander.deucher@amd.com> ---- - drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h | 7 +++++- - .../gpu/drm/amd/display/dc/dce/dce_link_encoder.h | 26 +++------------------- - 2 files changed, 9 insertions(+), 24 deletions(-) - -diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h -index b026157..33c1754 100644 ---- a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h -+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h -@@ -30,6 +30,7 @@ - #include "dmcu.h" - - #define DMCU_COMMON_REG_LIST_DCE_BASE() \ -+ SR(DMCU_CTRL), \ - SR(DMCU_RAM_ACCESS_CTRL), \ - SR(DMCU_IRAM_WR_CTRL), \ - SR(DMCU_IRAM_WR_DATA) -@@ -42,6 +43,8 @@ - .field_name = reg_name ## __ ## field_name ## post_fix - - #define DMCU_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \ -+ DMCU_SF(DMCU_CTRL, \ -+ DMCU_ENABLE, mask_sh), \ - DMCU_SF(DMCU_RAM_ACCESS_CTRL, \ - IRAM_HOST_ACCESS_EN, mask_sh), \ - DMCU_SF(DMCU_RAM_ACCESS_CTRL, \ -@@ -55,7 +58,8 @@ - #define DMCU_REG_FIELD_LIST(type) \ - type DMCU_IRAM_MEM_PWR_STATE; \ - type IRAM_HOST_ACCESS_EN; \ -- type IRAM_WR_ADDR_AUTO_INC -+ type IRAM_WR_ADDR_AUTO_INC; \ -+ type DMCU_ENABLE - - struct dce_dmcu_shift { - DMCU_REG_FIELD_LIST(uint8_t); -@@ -66,6 +70,7 @@ struct dce_dmcu_mask { - }; - - struct dce_dmcu_registers { -+ uint32_t DMCU_CTRL; - uint32_t DMCU_RAM_ACCESS_CTRL; - uint32_t DCI_MEM_PWR_STATUS; - uint32_t DMU_MEM_PWR_CNTL; -diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h -index 053f72b..8a07665 100644 ---- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h -+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h -@@ -39,18 +39,13 @@ - SRI(DC_HPD_CONTROL, HPD, id) - - #define LE_COMMON_REG_LIST_BASE(id) \ -- SR(BL_PWM_CNTL), \ -- SR(BL_PWM_GRP1_REG_LOCK), \ -- SR(BL_PWM_PERIOD_CNTL), \ -- SR(LVTMA_PWRSEQ_CNTL), \ -- SR(LVTMA_PWRSEQ_STATE), \ -- SR(BL_PWM_CNTL2), \ -- SR(LVTMA_PWRSEQ_REF_DIV), \ - SR(MASTER_COMM_DATA_REG1), \ - SR(MASTER_COMM_DATA_REG2), \ - SR(MASTER_COMM_DATA_REG3), \ - SR(MASTER_COMM_CMD_REG), \ - SR(MASTER_COMM_CNTL_REG), \ -+ SR(LVTMA_PWRSEQ_CNTL), \ -+ SR(LVTMA_PWRSEQ_STATE), \ - SR(DMCU_RAM_ACCESS_CTRL), \ - SR(DMCU_IRAM_RD_CTRL), \ - SR(DMCU_IRAM_RD_DATA), \ -@@ -81,22 +76,16 @@ - LE_COMMON_REG_LIST_BASE(id), \ - SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \ - SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \ -- SR(BIOS_SCRATCH_2), \ -- SR(BL1_PWM_USER_LEVEL), \ - SR(DCI_MEM_PWR_STATUS) - - #define LE_DCE110_REG_LIST(id)\ - LE_COMMON_REG_LIST_BASE(id), \ - SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \ - SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \ -- SR(BIOS_SCRATCH_2), \ -- SR(BL1_PWM_USER_LEVEL), \ - SR(DCI_MEM_PWR_STATUS) - - #define LE_DCE80_REG_LIST(id)\ -- SR(BIOS_SCRATCH_2), \ - SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \ -- SR(BL1_PWM_USER_LEVEL), \ - LE_COMMON_REG_LIST_BASE(id) - - -@@ -110,24 +99,16 @@ struct dce110_link_enc_hpd_registers { - }; - - struct dce110_link_enc_registers { -- /* BL registers */ -- uint32_t BL_PWM_CNTL; -- uint32_t BL_PWM_GRP1_REG_LOCK; -- uint32_t BL_PWM_PERIOD_CNTL; -+ /* Backlight registers */ - uint32_t LVTMA_PWRSEQ_CNTL; - uint32_t LVTMA_PWRSEQ_STATE; -- uint32_t BL_PWM_CNTL2; -- uint32_t LVTMA_PWRSEQ_REF_DIV; - - /* DMCU registers */ -- uint32_t BL1_PWM_USER_LEVEL; -- uint32_t ABM0_BL1_PWM_USER_LEVEL; - uint32_t MASTER_COMM_DATA_REG1; - uint32_t MASTER_COMM_DATA_REG2; - uint32_t MASTER_COMM_DATA_REG3; - uint32_t MASTER_COMM_CMD_REG; - uint32_t MASTER_COMM_CNTL_REG; -- uint32_t BIOS_SCRATCH_2; - uint32_t DMCU_RAM_ACCESS_CTRL; - uint32_t DCI_MEM_PWR_STATUS; - uint32_t DMU_MEM_PWR_CNTL; -@@ -136,7 +117,6 @@ struct dce110_link_enc_registers { - uint32_t DMCU_INTERRUPT_TO_UC_EN_MASK; - uint32_t SMU_INTERRUPT_CONTROL; - -- - /* Common DP registers */ - uint32_t DIG_BE_CNTL; - uint32_t DIG_BE_EN_CNTL; --- -2.7.4 - |