diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/0158-drm-amd-display-refactor-clk_resync-to-avoid-asserti.patch')
-rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.14.71/0158-drm-amd-display-refactor-clk_resync-to-avoid-asserti.patch | 95 |
1 files changed, 0 insertions, 95 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/0158-drm-amd-display-refactor-clk_resync-to-avoid-asserti.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/0158-drm-amd-display-refactor-clk_resync-to-avoid-asserti.patch deleted file mode 100644 index d59ce4d4..00000000 --- a/common/recipes-kernel/linux/linux-yocto-4.14.71/0158-drm-amd-display-refactor-clk_resync-to-avoid-asserti.patch +++ /dev/null @@ -1,95 +0,0 @@ -From 1e8da121974d0236b13d2017ea105bd72ab40b5c Mon Sep 17 00:00:00 2001 -From: Tony Cheng <tony.cheng@amd.com> -Date: Mon, 16 Jan 2017 20:37:08 -0500 -Subject: [PATCH 0158/4131] drm/amd/display: refactor clk_resync to avoid - assertion - -- not all DCE has PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE bit defined. - -Signed-off-by: Tony Cheng <tony.cheng@amd.com> -Acked-by: Harry Wentland <Harry.Wentland@amd.com> -Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com> -Signed-off-by: Alex Deucher <alexander.deucher@amd.com> ---- - .../gpu/drm/amd/display/dc/dce/dce_clock_source.c | 57 ++++++++++++---------- - 1 file changed, 30 insertions(+), 27 deletions(-) - -diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c -index a38172b..78f4327 100644 ---- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c -+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c -@@ -767,41 +767,44 @@ static void dce112_program_pixel_clk_resync( - enum dc_color_depth colordepth, - bool enable_ycbcr420) - { -- REG_UPDATE(PIXCLK_RESYNC_CNTL, -- PHYPLLA_DCCG_DEEP_COLOR_CNTL, 0); -+ uint32_t deep_color_cntl = 0; -+ uint32_t double_rate_enable = 0; -+ - /* - 24 bit mode: TMDS clock = 1.0 x pixel clock (1:1) - 30 bit mode: TMDS clock = 1.25 x pixel clock (5:4) - 36 bit mode: TMDS clock = 1.5 x pixel clock (3:2) - 48 bit mode: TMDS clock = 2 x pixel clock (2:1) - */ -- if (signal_type != SIGNAL_TYPE_HDMI_TYPE_A) -- return; -+ if (signal_type == SIGNAL_TYPE_HDMI_TYPE_A) { -+ double_rate_enable = enable_ycbcr420 ? 1 : 0; - -- switch (colordepth) { -- case COLOR_DEPTH_888: -- REG_UPDATE_2(PIXCLK_RESYNC_CNTL, -- PHYPLLA_DCCG_DEEP_COLOR_CNTL, 0, -- PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE, enable_ycbcr420); -- break; -- case COLOR_DEPTH_101010: -- REG_UPDATE_2(PIXCLK_RESYNC_CNTL, -- PHYPLLA_DCCG_DEEP_COLOR_CNTL, 1, -- PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE, enable_ycbcr420); -- break; -- case COLOR_DEPTH_121212: -- REG_UPDATE_2(PIXCLK_RESYNC_CNTL, -- PHYPLLA_DCCG_DEEP_COLOR_CNTL, 2, -- PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE, enable_ycbcr420); -- break; -- case COLOR_DEPTH_161616: -- REG_UPDATE_2(PIXCLK_RESYNC_CNTL, -- PHYPLLA_DCCG_DEEP_COLOR_CNTL, 3, -- PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE, enable_ycbcr420); -- break; -- default: -- break; -+ switch (colordepth) { -+ case COLOR_DEPTH_888: -+ deep_color_cntl = 0; -+ break; -+ case COLOR_DEPTH_101010: -+ deep_color_cntl = 1; -+ break; -+ case COLOR_DEPTH_121212: -+ deep_color_cntl = 2; -+ break; -+ case COLOR_DEPTH_161616: -+ deep_color_cntl = 3; -+ break; -+ default: -+ break; -+ } - } -+ -+ if (clk_src->cs_mask->PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE) -+ REG_UPDATE_2(PIXCLK_RESYNC_CNTL, -+ PHYPLLA_DCCG_DEEP_COLOR_CNTL, deep_color_cntl, -+ PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE, double_rate_enable); -+ else -+ REG_UPDATE(PIXCLK_RESYNC_CNTL, -+ PHYPLLA_DCCG_DEEP_COLOR_CNTL, deep_color_cntl); -+ - } - - static bool dce110_program_pix_clk( --- -2.7.4 - |