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Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/0089-drm-amd-display-minor-clock-source-refactor.patch')
-rw-r--r--common/recipes-kernel/linux/linux-yocto-4.14.71/0089-drm-amd-display-minor-clock-source-refactor.patch197
1 files changed, 0 insertions, 197 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/0089-drm-amd-display-minor-clock-source-refactor.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/0089-drm-amd-display-minor-clock-source-refactor.patch
deleted file mode 100644
index c6e00727..00000000
--- a/common/recipes-kernel/linux/linux-yocto-4.14.71/0089-drm-amd-display-minor-clock-source-refactor.patch
+++ /dev/null
@@ -1,197 +0,0 @@
-From b281724a9f31725d4c483735061ba8631cfbdb25 Mon Sep 17 00:00:00 2001
-From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Date: Mon, 19 Dec 2016 15:41:49 -0500
-Subject: [PATCH 0089/4131] drm/amd/display: minor clock source refactor
-
-This should make it easier to share code with newer ASICs
-
-Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
-Acked-by: Harry Wentland <Harry.Wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- .../gpu/drm/amd/display/dc/dce/dce_clock_source.c | 68 +++++++++++-----------
- .../gpu/drm/amd/display/dc/dce/dce_clock_source.h | 9 ++-
- 2 files changed, 40 insertions(+), 37 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
-index 3d1c321..a38172b 100644
---- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
-+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
-@@ -465,7 +465,6 @@ static uint32_t dce110_get_pix_clk_dividers_helper (
- struct pll_settings *pll_settings,
- struct pixel_clk_params *pix_clk_params)
- {
-- uint32_t value = 0;
- uint32_t field = 0;
- uint32_t pll_calc_error = MAX_PLL_CALC_ERROR;
-
-@@ -473,7 +472,6 @@ static uint32_t dce110_get_pix_clk_dividers_helper (
- * HW Dce80 spec:
- * 00 - PCIE_REFCLK, 01 - XTALIN, 02 - GENERICA, 03 - GENERICB
- * 04 - HSYNCA, 05 - GENLK_CLK, 06 - PCIE_REFCLK, 07 - DVOCLK0 */
-- value = REG_READ(PLL_CNTL);
- REG_GET(PLL_CNTL, PLL_REF_DIV_SRC, &field);
- pll_settings->use_external_clk = (field > 1);
-
-@@ -807,51 +805,30 @@ static void dce112_program_pixel_clk_resync(
- }
-
- static bool dce110_program_pix_clk(
-- struct clock_source *clk_src,
-+ struct clock_source *clock_source,
- struct pixel_clk_params *pix_clk_params,
- struct pll_settings *pll_settings)
- {
-- struct dce110_clk_src *dce110_clk_src = TO_DCE110_CLK_SRC(clk_src);
-+ struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source);
- struct bp_pixel_clock_parameters bp_pc_params = {0};
-
- /* First disable SS
- * ATOMBIOS will enable by default SS on PLL for DP,
- * do not disable it here
- */
-- if (clk_src->id != CLOCK_SOURCE_ID_EXTERNAL &&
-+ if (clock_source->id != CLOCK_SOURCE_ID_EXTERNAL &&
- !dc_is_dp_signal(pix_clk_params->signal_type) &&
-- clk_src->ctx->dce_version <= DCE_VERSION_11_0)
-- disable_spread_spectrum(dce110_clk_src);
-+ clock_source->ctx->dce_version <= DCE_VERSION_11_0)
-+ disable_spread_spectrum(clk_src);
-
- /*ATOMBIOS expects pixel rate adjusted by deep color ratio)*/
- bp_pc_params.controller_id = pix_clk_params->controller_id;
-- bp_pc_params.pll_id = clk_src->id;
-+ bp_pc_params.pll_id = clock_source->id;
- bp_pc_params.target_pixel_clock = pll_settings->actual_pix_clk;
- bp_pc_params.encoder_object_id = pix_clk_params->encoder_object_id;
- bp_pc_params.signal_type = pix_clk_params->signal_type;
-
-- switch (clk_src->ctx->dce_version) {
-- case DCE_VERSION_11_2:
-- if (clk_src->id != CLOCK_SOURCE_ID_DP_DTO) {
-- bp_pc_params.flags.SET_GENLOCK_REF_DIV_SRC =
-- pll_settings->use_external_clk;
-- bp_pc_params.flags.SET_XTALIN_REF_SRC =
-- !pll_settings->use_external_clk;
-- if (pix_clk_params->flags.SUPPORT_YCBCR420) {
-- bp_pc_params.target_pixel_clock = pll_settings->actual_pix_clk / 2;
-- bp_pc_params.flags.SUPPORT_YUV_420 = 1;
-- }
-- }
-- if (dce110_clk_src->bios->funcs->set_pixel_clock(
-- dce110_clk_src->bios, &bp_pc_params) != BP_RESULT_OK)
-- return false;
-- /* Resync deep color DTO */
-- if (clk_src->id != CLOCK_SOURCE_ID_DP_DTO)
-- dce112_program_pixel_clk_resync(dce110_clk_src,
-- pix_clk_params->signal_type,
-- pix_clk_params->color_depth,
-- pix_clk_params->flags.SUPPORT_YCBCR420);
-- break;
-+ switch (clock_source->ctx->dce_version) {
- case DCE_VERSION_8_0:
- case DCE_VERSION_10_0:
- case DCE_VERSION_11_0:
-@@ -864,28 +841,49 @@ static bool dce110_program_pix_clk(
- bp_pc_params.flags.SET_EXTERNAL_REF_DIV_SRC =
- pll_settings->use_external_clk;
-
-- if (dce110_clk_src->bios->funcs->set_pixel_clock(
-- dce110_clk_src->bios, &bp_pc_params) != BP_RESULT_OK)
-+ if (clk_src->bios->funcs->set_pixel_clock(
-+ clk_src->bios, &bp_pc_params) != BP_RESULT_OK)
- return false;
- /* Enable SS
- * ATOMBIOS will enable by default SS for DP on PLL ( DP ID clock),
- * based on HW display PLL team, SS control settings should be programmed
- * during PLL Reset, but they do not have effect
- * until SS_EN is asserted.*/
-- if (clk_src->id != CLOCK_SOURCE_ID_EXTERNAL
-+ if (clock_source->id != CLOCK_SOURCE_ID_EXTERNAL
- && pix_clk_params->flags.ENABLE_SS && !dc_is_dp_signal(
- pix_clk_params->signal_type)) {
-
-- if (!enable_spread_spectrum(dce110_clk_src,
-+ if (!enable_spread_spectrum(clk_src,
- pix_clk_params->signal_type,
- pll_settings))
- return false;
- /* Resync deep color DTO */
-- dce110_program_pixel_clk_resync(dce110_clk_src,
-+ dce110_program_pixel_clk_resync(clk_src,
- pix_clk_params->signal_type,
- pix_clk_params->color_depth);
- }
- break;
-+ case DCE_VERSION_11_2:
-+ if (clock_source->id != CLOCK_SOURCE_ID_DP_DTO) {
-+ bp_pc_params.flags.SET_GENLOCK_REF_DIV_SRC =
-+ pll_settings->use_external_clk;
-+ bp_pc_params.flags.SET_XTALIN_REF_SRC =
-+ !pll_settings->use_external_clk;
-+ if (pix_clk_params->flags.SUPPORT_YCBCR420) {
-+ bp_pc_params.target_pixel_clock = pll_settings->actual_pix_clk / 2;
-+ bp_pc_params.flags.SUPPORT_YUV_420 = 1;
-+ }
-+ }
-+ if (clk_src->bios->funcs->set_pixel_clock(
-+ clk_src->bios, &bp_pc_params) != BP_RESULT_OK)
-+ return false;
-+ /* Resync deep color DTO */
-+ if (clock_source->id != CLOCK_SOURCE_ID_DP_DTO)
-+ dce112_program_pixel_clk_resync(clk_src,
-+ pix_clk_params->signal_type,
-+ pix_clk_params->color_depth,
-+ pix_clk_params->flags.SUPPORT_YCBCR420);
-+ break;
- default:
- break;
- }
-diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
-index 067e4ac..8ee0071 100644
---- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
-+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
-@@ -41,6 +41,7 @@
- #define CS_COMMON_REG_LIST_DCE_112(id) \
- SRI(PIXCLK_RESYNC_CNTL, PHYPLL, id)
-
-+
- #define CS_SF(reg_name, field_name, post_fix)\
- .field_name = reg_name ## __ ## field_name ## post_fix
-
-@@ -48,11 +49,11 @@
- CS_SF(PLL_CNTL, PLL_REF_DIV_SRC, mask_sh),\
- CS_SF(PIXCLK1_RESYNC_CNTL, DCCG_DEEP_COLOR_CNTL1, mask_sh),\
- CS_SF(PLL_POST_DIV, PLL_POST_DIV_PIXCLK, mask_sh),\
-- CS_SF(PLL_REF_DIV, PLL_REF_DIV, mask_sh),\
-+ CS_SF(PLL_REF_DIV, PLL_REF_DIV, mask_sh)
-
- #define CS_COMMON_MASK_SH_LIST_DCE_112(mask_sh)\
- CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\
-- CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE, mask_sh),\
-+ CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE, mask_sh)
-
- #define CS_REG_FIELD_LIST(type) \
- type PLL_REF_DIV_SRC; \
-@@ -61,6 +62,7 @@
- type PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE; \
- type PLL_POST_DIV_PIXCLK; \
- type PLL_REF_DIV; \
-+ type DP_DTO0_ENABLE;
-
- struct dce110_clk_src_shift {
- CS_REG_FIELD_LIST(uint8_t)
-@@ -74,6 +76,9 @@ struct dce110_clk_src_regs {
- uint32_t RESYNC_CNTL;
- uint32_t PIXCLK_RESYNC_CNTL;
- uint32_t PLL_CNTL;
-+ uint32_t PHASE;
-+ uint32_t MODULO;
-+ uint32_t PIXEL_RATE_CNTL;
- };
-
- struct dce110_clk_src {
---
-2.7.4
-
generated by cgit 1.2.3-korg (git 2.39.0) at 2024-04-24 22:54:56 +0000