diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-amd/0022-drm-radeon-cik-Add-macrotile-mode-array-query.patch')
| -rw-r--r-- | common/recipes-kernel/linux/linux-amd/0022-drm-radeon-cik-Add-macrotile-mode-array-query.patch | 113 |
1 files changed, 113 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-amd/0022-drm-radeon-cik-Add-macrotile-mode-array-query.patch b/common/recipes-kernel/linux/linux-amd/0022-drm-radeon-cik-Add-macrotile-mode-array-query.patch new file mode 100644 index 00000000..f71ad69d --- /dev/null +++ b/common/recipes-kernel/linux/linux-amd/0022-drm-radeon-cik-Add-macrotile-mode-array-query.patch @@ -0,0 +1,113 @@ +From c264fd5d63ea30124efe2af14fa1fca5b171a113 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Michel=20D=C3=A4nzer?= <michel.daenzer@amd.com> +Date: Mon, 18 Nov 2013 18:26:00 +0900 +Subject: [PATCH 22/60] drm/radeon/cik: Add macrotile mode array query +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +This is required to properly calculate the tiling parameters +in userspace. + +Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/radeon/cik.c | 3 +++ + drivers/gpu/drm/radeon/radeon.h | 1 + + drivers/gpu/drm/radeon/radeon_drv.c | 3 ++- + drivers/gpu/drm/radeon/radeon_kms.c | 9 +++++++++ + include/uapi/drm/radeon_drm.h | 2 ++ + 5 files changed, 17 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c +index 3741a68..17bbdfd 100644 +--- a/drivers/gpu/drm/radeon/cik.c ++++ b/drivers/gpu/drm/radeon/cik.c +@@ -1981,6 +1981,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) + gb_tile_moden = 0; + break; + } ++ rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden; + WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden); + } + } else if (num_pipe_configs == 4) { +@@ -2327,6 +2328,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) + gb_tile_moden = 0; + break; + } ++ rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden; + WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden); + } + } else if (num_pipe_configs == 2) { +@@ -2544,6 +2546,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) + gb_tile_moden = 0; + break; + } ++ rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden; + WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden); + } + } else +diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h +index 6ad3fb2..af893e3 100644 +--- a/drivers/gpu/drm/radeon/radeon.h ++++ b/drivers/gpu/drm/radeon/radeon.h +@@ -1997,6 +1997,7 @@ struct cik_asic { + + unsigned tile_config; + uint32_t tile_mode_array[32]; ++ uint32_t macrotile_mode_array[16]; + }; + + union radeon_asic_config { +diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c +index 9c14a1b..51b3214 100644 +--- a/drivers/gpu/drm/radeon/radeon_drv.c ++++ b/drivers/gpu/drm/radeon/radeon_drv.c +@@ -75,9 +75,10 @@ + * 2.32.0 - new info request for rings working + * 2.33.0 - Add SI tiling mode array query + * 2.34.0 - Add CIK tiling mode array query ++ * 2.35.0 - Add CIK macrotile mode array query + */ + #define KMS_DRIVER_MAJOR 2 +-#define KMS_DRIVER_MINOR 34 ++#define KMS_DRIVER_MINOR 35 + #define KMS_DRIVER_PATCHLEVEL 0 + int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags); + int radeon_driver_unload_kms(struct drm_device *dev); +diff --git a/drivers/gpu/drm/radeon/radeon_kms.c b/drivers/gpu/drm/radeon/radeon_kms.c +index 39f3a12..e90c42b 100644 +--- a/drivers/gpu/drm/radeon/radeon_kms.c ++++ b/drivers/gpu/drm/radeon/radeon_kms.c +@@ -433,6 +433,15 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) + return -EINVAL; + } + break; ++ case RADEON_INFO_CIK_MACROTILE_MODE_ARRAY: ++ if (rdev->family >= CHIP_BONAIRE) { ++ value = rdev->config.cik.macrotile_mode_array; ++ value_size = sizeof(uint32_t)*16; ++ } else { ++ DRM_DEBUG_KMS("macrotile mode array is cik+ only!\n"); ++ return -EINVAL; ++ } ++ break; + case RADEON_INFO_SI_CP_DMA_COMPUTE: + *value = 1; + break; +diff --git a/include/uapi/drm/radeon_drm.h b/include/uapi/drm/radeon_drm.h +index a71442b..fe421e8a 100644 +--- a/include/uapi/drm/radeon_drm.h ++++ b/include/uapi/drm/radeon_drm.h +@@ -981,6 +981,8 @@ struct drm_radeon_cs { + #define RADEON_INFO_SI_TILE_MODE_ARRAY 0x16 + /* query if CP DMA is supported on the compute ring */ + #define RADEON_INFO_SI_CP_DMA_COMPUTE 0x17 ++/* CIK macrotile mode array */ ++#define RADEON_INFO_CIK_MACROTILE_MODE_ARRAY 0x18 + /* query the number of render backends */ + #define RADEON_INFO_SI_BACKEND_ENABLED_MASK 0x19 + +-- +1.9.1 + |