diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-amd/0019-drm-radeon-add-proper-support-for-RADEON_VM_BLOCK_SI.patch')
| -rw-r--r-- | common/recipes-kernel/linux/linux-amd/0019-drm-radeon-add-proper-support-for-RADEON_VM_BLOCK_SI.patch | 132 |
1 files changed, 132 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-amd/0019-drm-radeon-add-proper-support-for-RADEON_VM_BLOCK_SI.patch b/common/recipes-kernel/linux/linux-amd/0019-drm-radeon-add-proper-support-for-RADEON_VM_BLOCK_SI.patch new file mode 100644 index 00000000..f1750572 --- /dev/null +++ b/common/recipes-kernel/linux/linux-amd/0019-drm-radeon-add-proper-support-for-RADEON_VM_BLOCK_SI.patch @@ -0,0 +1,132 @@ +From cb32f1bcbf6f50c751d86b4527b1b01b2549ea11 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com> +Date: Tue, 29 Oct 2013 09:30:16 +0100 +Subject: [PATCH 19/60] drm/radeon: add proper support for RADEON_VM_BLOCK_SIZE +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +This patch makes it possible to decide how many address +bits are spend on the page directory vs the page tables. + +Signed-off-by: Christian König <christian.koenig@amd.com> +--- + drivers/gpu/drm/radeon/cik.c | 1 + + drivers/gpu/drm/radeon/cikd.h | 1 + + drivers/gpu/drm/radeon/ni.c | 1 + + drivers/gpu/drm/radeon/nid.h | 1 + + drivers/gpu/drm/radeon/radeon.h | 2 +- + drivers/gpu/drm/radeon/radeon_gart.c | 3 ++- + drivers/gpu/drm/radeon/si.c | 1 + + drivers/gpu/drm/radeon/sid.h | 1 + + 8 files changed, 9 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c +index e84005a..3741a68 100644 +--- a/drivers/gpu/drm/radeon/cik.c ++++ b/drivers/gpu/drm/radeon/cik.c +@@ -4576,6 +4576,7 @@ static int cik_pcie_gart_enable(struct radeon_device *rdev) + (u32)(rdev->dummy_page.addr >> 12)); + WREG32(VM_CONTEXT1_CNTL2, 4); + WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) | ++ PAGE_TABLE_BLOCK_SIZE(RADEON_VM_BLOCK_SIZE - 9) | + RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT | + RANGE_PROTECTION_FAULT_ENABLE_DEFAULT | + DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT | +diff --git a/drivers/gpu/drm/radeon/cikd.h b/drivers/gpu/drm/radeon/cikd.h +index 9c8ef20..c4738bc 100644 +--- a/drivers/gpu/drm/radeon/cikd.h ++++ b/drivers/gpu/drm/radeon/cikd.h +@@ -474,6 +474,7 @@ + #define READ_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 16) + #define WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 18) + #define WRITE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 19) ++#define PAGE_TABLE_BLOCK_SIZE(x) (((x) & 0xF) << 24) + #define VM_CONTEXT1_CNTL 0x1414 + #define VM_CONTEXT0_CNTL2 0x1430 + #define VM_CONTEXT1_CNTL2 0x1434 +diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c +index a3c7826..4317e57 100644 +--- a/drivers/gpu/drm/radeon/ni.c ++++ b/drivers/gpu/drm/radeon/ni.c +@@ -1267,6 +1267,7 @@ static int cayman_pcie_gart_enable(struct radeon_device *rdev) + (u32)(rdev->dummy_page.addr >> 12)); + WREG32(VM_CONTEXT1_CNTL2, 4); + WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) | ++ PAGE_TABLE_BLOCK_SIZE(RADEON_VM_BLOCK_SIZE - 9) | + RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT | + RANGE_PROTECTION_FAULT_ENABLE_DEFAULT | + DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT | +diff --git a/drivers/gpu/drm/radeon/nid.h b/drivers/gpu/drm/radeon/nid.h +index d996033..2e12e4d 100644 +--- a/drivers/gpu/drm/radeon/nid.h ++++ b/drivers/gpu/drm/radeon/nid.h +@@ -128,6 +128,7 @@ + #define READ_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 16) + #define WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 18) + #define WRITE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 19) ++#define PAGE_TABLE_BLOCK_SIZE(x) (((x) & 0xF) << 24) + #define VM_CONTEXT1_CNTL 0x1414 + #define VM_CONTEXT0_CNTL2 0x1430 + #define VM_CONTEXT1_CNTL2 0x1434 +diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h +index e796f9a..6ad3fb2 100644 +--- a/drivers/gpu/drm/radeon/radeon.h ++++ b/drivers/gpu/drm/radeon/radeon.h +@@ -836,7 +836,7 @@ struct radeon_mec { + /* defines number of bits in page table versus page directory, + * a page is 4KB so we have 12 bits offset, 9 bits in the page + * table and the remaining 19 bits are in the page directory */ +-#define RADEON_VM_BLOCK_SIZE 9 ++#define RADEON_VM_BLOCK_SIZE 12 + + /* number of entries in page table */ + #define RADEON_VM_PTE_COUNT (1 << RADEON_VM_BLOCK_SIZE) +diff --git a/drivers/gpu/drm/radeon/radeon_gart.c b/drivers/gpu/drm/radeon/radeon_gart.c +index f960ce6..34b09ac 100644 +--- a/drivers/gpu/drm/radeon/radeon_gart.c ++++ b/drivers/gpu/drm/radeon/radeon_gart.c +@@ -959,6 +959,7 @@ static int radeon_vm_update_pdes(struct radeon_device *rdev, + uint64_t start, uint64_t end) + { + static const uint32_t incr = RADEON_VM_PTE_COUNT * 8; ++ const unsigned align = min((uint32_t)RADEON_VM_PTB_ALIGN_SIZE, incr); + + uint64_t last_pde = ~0, last_pt = ~0; + unsigned count = 0; +@@ -979,7 +980,7 @@ retry: + r = radeon_sa_bo_new(rdev, &rdev->vm_manager.sa_manager, + &vm->page_tables[pt_idx], + RADEON_VM_PTE_COUNT * 8, +- RADEON_GPU_PAGE_SIZE, false); ++ align, false); + + if (r == -ENOMEM) { + r = radeon_vm_evict(rdev, vm); +diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c +index 46b57e1..48ad0ae 100644 +--- a/drivers/gpu/drm/radeon/si.c ++++ b/drivers/gpu/drm/radeon/si.c +@@ -3993,6 +3993,7 @@ static int si_pcie_gart_enable(struct radeon_device *rdev) + (u32)(rdev->dummy_page.addr >> 12)); + WREG32(VM_CONTEXT1_CNTL2, 4); + WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) | ++ PAGE_TABLE_BLOCK_SIZE(RADEON_VM_BLOCK_SIZE - 9) | + RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT | + RANGE_PROTECTION_FAULT_ENABLE_DEFAULT | + DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT | +diff --git a/drivers/gpu/drm/radeon/sid.h b/drivers/gpu/drm/radeon/sid.h +index 205a961..940e36b 100644 +--- a/drivers/gpu/drm/radeon/sid.h ++++ b/drivers/gpu/drm/radeon/sid.h +@@ -357,6 +357,7 @@ + #define READ_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 16) + #define WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 18) + #define WRITE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 19) ++#define PAGE_TABLE_BLOCK_SIZE(x) (((x) & 0xF) << 24) + #define VM_CONTEXT1_CNTL 0x1414 + #define VM_CONTEXT0_CNTL2 0x1430 + #define VM_CONTEXT1_CNTL2 0x1434 +-- +1.9.1 + |