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-rw-r--r--common/recipes-kernel/linux/linux-amd/0017-drm-radeon-drop-CP-page-table-updates-cleanup-v2.patch676
1 files changed, 676 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-amd/0017-drm-radeon-drop-CP-page-table-updates-cleanup-v2.patch b/common/recipes-kernel/linux/linux-amd/0017-drm-radeon-drop-CP-page-table-updates-cleanup-v2.patch
new file mode 100644
index 00000000..c0d7af20
--- /dev/null
+++ b/common/recipes-kernel/linux/linux-amd/0017-drm-radeon-drop-CP-page-table-updates-cleanup-v2.patch
@@ -0,0 +1,676 @@
+From 00110850672bf5b6bb10f7687b39574dbb2acee6 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
+Date: Wed, 30 Oct 2013 11:51:09 -0400
+Subject: [PATCH 17/60] drm/radeon: drop CP page table updates & cleanup v2
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The DMA ring seems to be stable now.
+
+v2: remove pt_ring_index as well
+
+Signed-off-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/radeon/cik.c | 56 --------------------------
+ drivers/gpu/drm/radeon/cik_sdma.c | 21 ++++------
+ drivers/gpu/drm/radeon/ni.c | 76 ------------------------------------
+ drivers/gpu/drm/radeon/ni_dma.c | 18 ++++-----
+ drivers/gpu/drm/radeon/radeon.h | 8 +++-
+ drivers/gpu/drm/radeon/radeon_asic.c | 15 +++----
+ drivers/gpu/drm/radeon/radeon_asic.h | 31 ++++++++-------
+ drivers/gpu/drm/radeon/radeon_gart.c | 29 +++++++++++---
+ drivers/gpu/drm/radeon/si.c | 60 ----------------------------
+ drivers/gpu/drm/radeon/si_dma.c | 21 ++++------
+ 10 files changed, 73 insertions(+), 262 deletions(-)
+
+diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
+index 54a62cf..e3bec288 100644
+--- a/drivers/gpu/drm/radeon/cik.c
++++ b/drivers/gpu/drm/radeon/cik.c
+@@ -4830,62 +4830,6 @@ void cik_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
+ }
+ }
+
+-/**
+- * cik_vm_set_page - update the page tables using sDMA
+- *
+- * @rdev: radeon_device pointer
+- * @ib: indirect buffer to fill with commands
+- * @pe: addr of the page entry
+- * @addr: dst addr to write into pe
+- * @count: number of page entries to update
+- * @incr: increase next addr by incr bytes
+- * @flags: access flags
+- *
+- * Update the page tables using CP or sDMA (CIK).
+- */
+-void cik_vm_set_page(struct radeon_device *rdev,
+- struct radeon_ib *ib,
+- uint64_t pe,
+- uint64_t addr, unsigned count,
+- uint32_t incr, uint32_t flags)
+-{
+- uint32_t r600_flags = cayman_vm_page_flags(rdev, flags);
+- uint64_t value;
+- unsigned ndw;
+-
+- if (rdev->asic->vm.pt_ring_index == RADEON_RING_TYPE_GFX_INDEX) {
+- /* CP */
+- while (count) {
+- ndw = 2 + count * 2;
+- if (ndw > 0x3FFE)
+- ndw = 0x3FFE;
+-
+- ib->ptr[ib->length_dw++] = PACKET3(PACKET3_WRITE_DATA, ndw);
+- ib->ptr[ib->length_dw++] = (WRITE_DATA_ENGINE_SEL(0) |
+- WRITE_DATA_DST_SEL(1));
+- ib->ptr[ib->length_dw++] = pe;
+- ib->ptr[ib->length_dw++] = upper_32_bits(pe);
+- for (; ndw > 2; ndw -= 2, --count, pe += 8) {
+- if (flags & RADEON_VM_PAGE_SYSTEM) {
+- value = radeon_vm_map_gart(rdev, addr);
+- value &= 0xFFFFFFFFFFFFF000ULL;
+- } else if (flags & RADEON_VM_PAGE_VALID) {
+- value = addr;
+- } else {
+- value = 0;
+- }
+- addr += incr;
+- value |= r600_flags;
+- ib->ptr[ib->length_dw++] = value;
+- ib->ptr[ib->length_dw++] = upper_32_bits(value);
+- }
+- }
+- } else {
+- /* DMA */
+- cik_sdma_vm_set_page(rdev, ib, pe, addr, count, incr, flags);
+- }
+-}
+-
+ /*
+ * RLC
+ * The RLC is a multi-purpose microengine that handles a
+diff --git a/drivers/gpu/drm/radeon/cik_sdma.c b/drivers/gpu/drm/radeon/cik_sdma.c
+index e73c49e..bbe0bc8 100644
+--- a/drivers/gpu/drm/radeon/cik_sdma.c
++++ b/drivers/gpu/drm/radeon/cik_sdma.c
+@@ -639,13 +639,12 @@ void cik_sdma_vm_set_page(struct radeon_device *rdev,
+ uint64_t addr, unsigned count,
+ uint32_t incr, uint32_t flags)
+ {
+- uint32_t r600_flags = cayman_vm_page_flags(rdev, flags);
+ uint64_t value;
+ unsigned ndw;
+
+- trace_radeon_vm_set_page(pe, addr, count, incr, r600_flags);
++ trace_radeon_vm_set_page(pe, addr, count, incr, flags);
+
+- if (flags & RADEON_VM_PAGE_SYSTEM) {
++ if (flags & R600_PTE_SYSTEM) {
+ while (count) {
+ ndw = count * 2;
+ if (ndw > 0xFFFFE)
+@@ -657,16 +656,10 @@ void cik_sdma_vm_set_page(struct radeon_device *rdev,
+ ib->ptr[ib->length_dw++] = upper_32_bits(pe);
+ ib->ptr[ib->length_dw++] = ndw;
+ for (; ndw > 0; ndw -= 2, --count, pe += 8) {
+- if (flags & RADEON_VM_PAGE_SYSTEM) {
+- value = radeon_vm_map_gart(rdev, addr);
+- value &= 0xFFFFFFFFFFFFF000ULL;
+- } else if (flags & RADEON_VM_PAGE_VALID) {
+- value = addr;
+- } else {
+- value = 0;
+- }
++ value = radeon_vm_map_gart(rdev, addr);
++ value &= 0xFFFFFFFFFFFFF000ULL;
+ addr += incr;
+- value |= r600_flags;
++ value |= flags;
+ ib->ptr[ib->length_dw++] = value;
+ ib->ptr[ib->length_dw++] = upper_32_bits(value);
+ }
+@@ -677,7 +670,7 @@ void cik_sdma_vm_set_page(struct radeon_device *rdev,
+ if (ndw > 0x7FFFF)
+ ndw = 0x7FFFF;
+
+- if (flags & RADEON_VM_PAGE_VALID)
++ if (flags & R600_PTE_VALID)
+ value = addr;
+ else
+ value = 0;
+@@ -685,7 +678,7 @@ void cik_sdma_vm_set_page(struct radeon_device *rdev,
+ ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_GENERATE_PTE_PDE, 0, 0);
+ ib->ptr[ib->length_dw++] = pe; /* dst addr */
+ ib->ptr[ib->length_dw++] = upper_32_bits(pe);
+- ib->ptr[ib->length_dw++] = r600_flags; /* mask */
++ ib->ptr[ib->length_dw++] = flags; /* mask */
+ ib->ptr[ib->length_dw++] = 0;
+ ib->ptr[ib->length_dw++] = value; /* value */
+ ib->ptr[ib->length_dw++] = upper_32_bits(value);
+diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
+index 474343a..2443d11 100644
+--- a/drivers/gpu/drm/radeon/ni.c
++++ b/drivers/gpu/drm/radeon/ni.c
+@@ -174,11 +174,6 @@ extern void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
+ extern void evergreen_program_aspm(struct radeon_device *rdev);
+ extern void sumo_rlc_fini(struct radeon_device *rdev);
+ extern int sumo_rlc_init(struct radeon_device *rdev);
+-extern void cayman_dma_vm_set_page(struct radeon_device *rdev,
+- struct radeon_ib *ib,
+- uint64_t pe,
+- uint64_t addr, unsigned count,
+- uint32_t incr, uint32_t flags);
+
+ /* Firmware Names */
+ MODULE_FIRMWARE("radeon/BARTS_pfp.bin");
+@@ -2412,77 +2407,6 @@ void cayman_vm_decode_fault(struct radeon_device *rdev,
+ block, mc_id);
+ }
+
+-#define R600_ENTRY_VALID (1 << 0)
+-#define R600_PTE_SYSTEM (1 << 1)
+-#define R600_PTE_SNOOPED (1 << 2)
+-#define R600_PTE_READABLE (1 << 5)
+-#define R600_PTE_WRITEABLE (1 << 6)
+-
+-uint32_t cayman_vm_page_flags(struct radeon_device *rdev, uint32_t flags)
+-{
+- uint32_t r600_flags = 0;
+- r600_flags |= (flags & RADEON_VM_PAGE_VALID) ? R600_ENTRY_VALID : 0;
+- r600_flags |= (flags & RADEON_VM_PAGE_READABLE) ? R600_PTE_READABLE : 0;
+- r600_flags |= (flags & RADEON_VM_PAGE_WRITEABLE) ? R600_PTE_WRITEABLE : 0;
+- if (flags & RADEON_VM_PAGE_SYSTEM) {
+- r600_flags |= R600_PTE_SYSTEM;
+- r600_flags |= (flags & RADEON_VM_PAGE_SNOOPED) ? R600_PTE_SNOOPED : 0;
+- }
+- return r600_flags;
+-}
+-
+-/**
+- * cayman_vm_set_page - update the page tables using the CP
+- *
+- * @rdev: radeon_device pointer
+- * @ib: indirect buffer to fill with commands
+- * @pe: addr of the page entry
+- * @addr: dst addr to write into pe
+- * @count: number of page entries to update
+- * @incr: increase next addr by incr bytes
+- * @flags: access flags
+- *
+- * Update the page tables using the CP (cayman/TN).
+- */
+-void cayman_vm_set_page(struct radeon_device *rdev,
+- struct radeon_ib *ib,
+- uint64_t pe,
+- uint64_t addr, unsigned count,
+- uint32_t incr, uint32_t flags)
+-{
+- uint32_t r600_flags = cayman_vm_page_flags(rdev, flags);
+- uint64_t value;
+- unsigned ndw;
+-
+- if (rdev->asic->vm.pt_ring_index == RADEON_RING_TYPE_GFX_INDEX) {
+- while (count) {
+- ndw = 1 + count * 2;
+- if (ndw > 0x3FFF)
+- ndw = 0x3FFF;
+-
+- ib->ptr[ib->length_dw++] = PACKET3(PACKET3_ME_WRITE, ndw);
+- ib->ptr[ib->length_dw++] = pe;
+- ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;
+- for (; ndw > 1; ndw -= 2, --count, pe += 8) {
+- if (flags & RADEON_VM_PAGE_SYSTEM) {
+- value = radeon_vm_map_gart(rdev, addr);
+- value &= 0xFFFFFFFFFFFFF000ULL;
+- } else if (flags & RADEON_VM_PAGE_VALID) {
+- value = addr;
+- } else {
+- value = 0;
+- }
+- addr += incr;
+- value |= r600_flags;
+- ib->ptr[ib->length_dw++] = value;
+- ib->ptr[ib->length_dw++] = upper_32_bits(value);
+- }
+- }
+- } else {
+- cayman_dma_vm_set_page(rdev, ib, pe, addr, count, incr, flags);
+- }
+-}
+-
+ /**
+ * cayman_vm_flush - vm flush using the CP
+ *
+diff --git a/drivers/gpu/drm/radeon/ni_dma.c b/drivers/gpu/drm/radeon/ni_dma.c
+index 599e87b..ddc946b 100644
+--- a/drivers/gpu/drm/radeon/ni_dma.c
++++ b/drivers/gpu/drm/radeon/ni_dma.c
+@@ -240,8 +240,7 @@ bool cayman_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
+ * @addr: dst addr to write into pe
+ * @count: number of page entries to update
+ * @incr: increase next addr by incr bytes
+- * @flags: access flags
+- * @r600_flags: hw access flags
++ * @flags: hw access flags
+ *
+ * Update the page tables using the DMA (cayman/TN).
+ */
+@@ -251,13 +250,12 @@ void cayman_dma_vm_set_page(struct radeon_device *rdev,
+ uint64_t addr, unsigned count,
+ uint32_t incr, uint32_t flags)
+ {
+- uint32_t r600_flags = cayman_vm_page_flags(rdev, flags);
+ uint64_t value;
+ unsigned ndw;
+
+- trace_radeon_vm_set_page(pe, addr, count, incr, r600_flags);
++ trace_radeon_vm_set_page(pe, addr, count, incr, flags);
+
+- if ((flags & RADEON_VM_PAGE_SYSTEM) || (count == 1)) {
++ if ((flags & R600_PTE_SYSTEM) || (count == 1)) {
+ while (count) {
+ ndw = count * 2;
+ if (ndw > 0xFFFFE)
+@@ -268,16 +266,16 @@ void cayman_dma_vm_set_page(struct radeon_device *rdev,
+ ib->ptr[ib->length_dw++] = pe;
+ ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;
+ for (; ndw > 0; ndw -= 2, --count, pe += 8) {
+- if (flags & RADEON_VM_PAGE_SYSTEM) {
++ if (flags & R600_PTE_SYSTEM) {
+ value = radeon_vm_map_gart(rdev, addr);
+ value &= 0xFFFFFFFFFFFFF000ULL;
+- } else if (flags & RADEON_VM_PAGE_VALID) {
++ } else if (flags & R600_PTE_VALID) {
+ value = addr;
+ } else {
+ value = 0;
+ }
+ addr += incr;
+- value |= r600_flags;
++ value |= flags;
+ ib->ptr[ib->length_dw++] = value;
+ ib->ptr[ib->length_dw++] = upper_32_bits(value);
+ }
+@@ -288,7 +286,7 @@ void cayman_dma_vm_set_page(struct radeon_device *rdev,
+ if (ndw > 0xFFFFE)
+ ndw = 0xFFFFE;
+
+- if (flags & RADEON_VM_PAGE_VALID)
++ if (flags & R600_PTE_VALID)
+ value = addr;
+ else
+ value = 0;
+@@ -296,7 +294,7 @@ void cayman_dma_vm_set_page(struct radeon_device *rdev,
+ ib->ptr[ib->length_dw++] = DMA_PTE_PDE_PACKET(ndw);
+ ib->ptr[ib->length_dw++] = pe; /* dst addr */
+ ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;
+- ib->ptr[ib->length_dw++] = r600_flags; /* mask */
++ ib->ptr[ib->length_dw++] = flags; /* mask */
+ ib->ptr[ib->length_dw++] = 0;
+ ib->ptr[ib->length_dw++] = value; /* value */
+ ib->ptr[ib->length_dw++] = upper_32_bits(value);
+diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
+index 6bc42c6..d478c28 100644
+--- a/drivers/gpu/drm/radeon/radeon.h
++++ b/drivers/gpu/drm/radeon/radeon.h
+@@ -846,6 +846,12 @@ struct radeon_mec {
+ #define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
+ #define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
+
++#define R600_PTE_VALID (1 << 0)
++#define R600_PTE_SYSTEM (1 << 1)
++#define R600_PTE_SNOOPED (1 << 2)
++#define R600_PTE_READABLE (1 << 5)
++#define R600_PTE_WRITEABLE (1 << 6)
++
+ struct radeon_vm {
+ struct list_head list;
+ struct list_head va;
+@@ -1691,8 +1697,6 @@ struct radeon_asic {
+ struct {
+ int (*init)(struct radeon_device *rdev);
+ void (*fini)(struct radeon_device *rdev);
+-
+- u32 pt_ring_index;
+ void (*set_page)(struct radeon_device *rdev,
+ struct radeon_ib *ib,
+ uint64_t pe,
+diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c
+index 5720e66..123adfe 100644
+--- a/drivers/gpu/drm/radeon/radeon_asic.c
++++ b/drivers/gpu/drm/radeon/radeon_asic.c
+@@ -1622,8 +1622,7 @@ static struct radeon_asic cayman_asic = {
+ .vm = {
+ .init = &cayman_vm_init,
+ .fini = &cayman_vm_fini,
+- .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
+- .set_page = &cayman_vm_set_page,
++ .set_page = &cayman_dma_vm_set_page,
+ },
+ .ring = {
+ [RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring,
+@@ -1723,8 +1722,7 @@ static struct radeon_asic trinity_asic = {
+ .vm = {
+ .init = &cayman_vm_init,
+ .fini = &cayman_vm_fini,
+- .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
+- .set_page = &cayman_vm_set_page,
++ .set_page = &cayman_dma_vm_set_page,
+ },
+ .ring = {
+ [RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring,
+@@ -1854,8 +1852,7 @@ static struct radeon_asic si_asic = {
+ .vm = {
+ .init = &si_vm_init,
+ .fini = &si_vm_fini,
+- .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
+- .set_page = &si_vm_set_page,
++ .set_page = &si_dma_vm_set_page,
+ },
+ .ring = {
+ [RADEON_RING_TYPE_GFX_INDEX] = &si_gfx_ring,
+@@ -2000,8 +1997,7 @@ static struct radeon_asic ci_asic = {
+ .vm = {
+ .init = &cik_vm_init,
+ .fini = &cik_vm_fini,
+- .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
+- .set_page = &cik_vm_set_page,
++ .set_page = &cik_sdma_vm_set_page,
+ },
+ .ring = {
+ [RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring,
+@@ -2102,8 +2098,7 @@ static struct radeon_asic kv_asic = {
+ .vm = {
+ .init = &cik_vm_init,
+ .fini = &cik_vm_fini,
+- .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
+- .set_page = &cik_vm_set_page,
++ .set_page = &cik_sdma_vm_set_page,
+ },
+ .ring = {
+ [RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring,
+diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h
+index 8588670..8939cb3 100644
+--- a/drivers/gpu/drm/radeon/radeon_asic.h
++++ b/drivers/gpu/drm/radeon/radeon_asic.h
+@@ -577,17 +577,18 @@ int cayman_vm_init(struct radeon_device *rdev);
+ void cayman_vm_fini(struct radeon_device *rdev);
+ void cayman_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
+ uint32_t cayman_vm_page_flags(struct radeon_device *rdev, uint32_t flags);
+-void cayman_vm_set_page(struct radeon_device *rdev,
+- struct radeon_ib *ib,
+- uint64_t pe,
+- uint64_t addr, unsigned count,
+- uint32_t incr, uint32_t flags);
+ int evergreen_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
+ int evergreen_dma_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
+ void cayman_dma_ring_ib_execute(struct radeon_device *rdev,
+ struct radeon_ib *ib);
+ bool cayman_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
+ bool cayman_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
++void cayman_dma_vm_set_page(struct radeon_device *rdev,
++ struct radeon_ib *ib,
++ uint64_t pe,
++ uint64_t addr, unsigned count,
++ uint32_t incr, uint32_t flags);
++
+ void cayman_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
+
+ int ni_dpm_init(struct radeon_device *rdev);
+@@ -649,17 +650,17 @@ int si_irq_set(struct radeon_device *rdev);
+ int si_irq_process(struct radeon_device *rdev);
+ int si_vm_init(struct radeon_device *rdev);
+ void si_vm_fini(struct radeon_device *rdev);
+-void si_vm_set_page(struct radeon_device *rdev,
+- struct radeon_ib *ib,
+- uint64_t pe,
+- uint64_t addr, unsigned count,
+- uint32_t incr, uint32_t flags);
+ void si_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
+ int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
+ int si_copy_dma(struct radeon_device *rdev,
+ uint64_t src_offset, uint64_t dst_offset,
+ unsigned num_gpu_pages,
+ struct radeon_fence **fence);
++void si_dma_vm_set_page(struct radeon_device *rdev,
++ struct radeon_ib *ib,
++ uint64_t pe,
++ uint64_t addr, unsigned count,
++ uint32_t incr, uint32_t flags);
+ void si_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
+ u32 si_get_xclk(struct radeon_device *rdev);
+ uint64_t si_get_gpu_clock_counter(struct radeon_device *rdev);
+@@ -727,11 +728,11 @@ int cik_irq_process(struct radeon_device *rdev);
+ int cik_vm_init(struct radeon_device *rdev);
+ void cik_vm_fini(struct radeon_device *rdev);
+ void cik_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
+-void cik_vm_set_page(struct radeon_device *rdev,
+- struct radeon_ib *ib,
+- uint64_t pe,
+- uint64_t addr, unsigned count,
+- uint32_t incr, uint32_t flags);
++void cik_sdma_vm_set_page(struct radeon_device *rdev,
++ struct radeon_ib *ib,
++ uint64_t pe,
++ uint64_t addr, unsigned count,
++ uint32_t incr, uint32_t flags);
+ void cik_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
+ int cik_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
+ u32 cik_compute_ring_get_rptr(struct radeon_device *rdev,
+diff --git a/drivers/gpu/drm/radeon/radeon_gart.c b/drivers/gpu/drm/radeon/radeon_gart.c
+index 33bd02e..9ceabdf 100644
+--- a/drivers/gpu/drm/radeon/radeon_gart.c
++++ b/drivers/gpu/drm/radeon/radeon_gart.c
+@@ -920,6 +920,26 @@ uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr)
+ }
+
+ /**
++ * radeon_vm_page_flags - translate page flags to what the hw uses
++ *
++ * @flags: flags comming from userspace
++ *
++ * Translate the flags the userspace ABI uses to hw flags.
++ */
++static uint32_t radeon_vm_page_flags(uint32_t flags)
++{
++ uint32_t hw_flags = 0;
++ hw_flags |= (flags & RADEON_VM_PAGE_VALID) ? R600_PTE_VALID : 0;
++ hw_flags |= (flags & RADEON_VM_PAGE_READABLE) ? R600_PTE_READABLE : 0;
++ hw_flags |= (flags & RADEON_VM_PAGE_WRITEABLE) ? R600_PTE_WRITEABLE : 0;
++ if (flags & RADEON_VM_PAGE_SYSTEM) {
++ hw_flags |= R600_PTE_SYSTEM;
++ hw_flags |= (flags & RADEON_VM_PAGE_SNOOPED) ? R600_PTE_SNOOPED : 0;
++ }
++ return hw_flags;
++}
++
++/**
+ * radeon_vm_update_pdes - make sure that page directory is valid
+ *
+ * @rdev: radeon_device pointer
+@@ -980,7 +1000,7 @@ retry:
+ if (count) {
+ radeon_asic_vm_set_page(rdev, ib, last_pde,
+ last_pt, count, incr,
+- RADEON_VM_PAGE_VALID);
++ R600_PTE_VALID);
+ }
+
+ count = 1;
+@@ -993,7 +1013,7 @@ retry:
+
+ if (count) {
+ radeon_asic_vm_set_page(rdev, ib, last_pde, last_pt, count,
+- incr, RADEON_VM_PAGE_VALID);
++ incr, R600_PTE_VALID);
+
+ }
+
+@@ -1088,7 +1108,6 @@ int radeon_vm_bo_update(struct radeon_device *rdev,
+ struct radeon_bo *bo,
+ struct ttm_mem_reg *mem)
+ {
+- unsigned ridx = rdev->asic->vm.pt_ring_index;
+ struct radeon_ib ib;
+ struct radeon_bo_va *bo_va;
+ unsigned nptes, npdes, ndw;
+@@ -1163,7 +1182,7 @@ int radeon_vm_bo_update(struct radeon_device *rdev,
+ if (ndw > 0xfffff)
+ return -ENOMEM;
+
+- r = radeon_ib_get(rdev, ridx, &ib, NULL, ndw * 4);
++ r = radeon_ib_get(rdev, R600_RING_TYPE_DMA_INDEX, &ib, NULL, ndw * 4);
+ if (r)
+ return r;
+ ib.length_dw = 0;
+@@ -1175,7 +1194,7 @@ int radeon_vm_bo_update(struct radeon_device *rdev,
+ }
+
+ radeon_vm_update_ptes(rdev, vm, &ib, bo_va->soffset, bo_va->eoffset,
+- addr, bo_va->flags);
++ addr, radeon_vm_page_flags(bo_va->flags));
+
+ radeon_semaphore_sync_to(ib.semaphore, vm->fence);
+ r = radeon_ib_schedule(rdev, &ib, NULL);
+diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
+index 50482e7..8a0bc79 100644
+--- a/drivers/gpu/drm/radeon/si.c
++++ b/drivers/gpu/drm/radeon/si.c
+@@ -83,11 +83,6 @@ extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_
+ extern u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev);
+ extern void evergreen_print_gpu_status_regs(struct radeon_device *rdev);
+ extern bool evergreen_is_display_hung(struct radeon_device *rdev);
+-extern void si_dma_vm_set_page(struct radeon_device *rdev,
+- struct radeon_ib *ib,
+- uint64_t pe,
+- uint64_t addr, unsigned count,
+- uint32_t incr, uint32_t flags);
+ static void si_enable_gui_idle_interrupt(struct radeon_device *rdev,
+ bool enable);
+ static void si_fini_pg(struct radeon_device *rdev);
+@@ -4696,61 +4691,6 @@ static void si_vm_decode_fault(struct radeon_device *rdev,
+ block, mc_id);
+ }
+
+-/**
+- * si_vm_set_page - update the page tables using the CP
+- *
+- * @rdev: radeon_device pointer
+- * @ib: indirect buffer to fill with commands
+- * @pe: addr of the page entry
+- * @addr: dst addr to write into pe
+- * @count: number of page entries to update
+- * @incr: increase next addr by incr bytes
+- * @flags: access flags
+- *
+- * Update the page tables using the CP (SI).
+- */
+-void si_vm_set_page(struct radeon_device *rdev,
+- struct radeon_ib *ib,
+- uint64_t pe,
+- uint64_t addr, unsigned count,
+- uint32_t incr, uint32_t flags)
+-{
+- uint32_t r600_flags = cayman_vm_page_flags(rdev, flags);
+- uint64_t value;
+- unsigned ndw;
+-
+- if (rdev->asic->vm.pt_ring_index == RADEON_RING_TYPE_GFX_INDEX) {
+- while (count) {
+- ndw = 2 + count * 2;
+- if (ndw > 0x3FFE)
+- ndw = 0x3FFE;
+-
+- ib->ptr[ib->length_dw++] = PACKET3(PACKET3_WRITE_DATA, ndw);
+- ib->ptr[ib->length_dw++] = (WRITE_DATA_ENGINE_SEL(0) |
+- WRITE_DATA_DST_SEL(1));
+- ib->ptr[ib->length_dw++] = pe;
+- ib->ptr[ib->length_dw++] = upper_32_bits(pe);
+- for (; ndw > 2; ndw -= 2, --count, pe += 8) {
+- if (flags & RADEON_VM_PAGE_SYSTEM) {
+- value = radeon_vm_map_gart(rdev, addr);
+- value &= 0xFFFFFFFFFFFFF000ULL;
+- } else if (flags & RADEON_VM_PAGE_VALID) {
+- value = addr;
+- } else {
+- value = 0;
+- }
+- addr += incr;
+- value |= r600_flags;
+- ib->ptr[ib->length_dw++] = value;
+- ib->ptr[ib->length_dw++] = upper_32_bits(value);
+- }
+- }
+- } else {
+- /* DMA */
+- si_dma_vm_set_page(rdev, ib, pe, addr, count, incr, flags);
+- }
+-}
+-
+ void si_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
+ {
+ struct radeon_ring *ring = &rdev->ring[ridx];
+diff --git a/drivers/gpu/drm/radeon/si_dma.c b/drivers/gpu/drm/radeon/si_dma.c
+index 97af34c..59be2cf 100644
+--- a/drivers/gpu/drm/radeon/si_dma.c
++++ b/drivers/gpu/drm/radeon/si_dma.c
+@@ -76,13 +76,12 @@ void si_dma_vm_set_page(struct radeon_device *rdev,
+ uint64_t addr, unsigned count,
+ uint32_t incr, uint32_t flags)
+ {
+- uint32_t r600_flags = cayman_vm_page_flags(rdev, flags);
+ uint64_t value;
+ unsigned ndw;
+
+- trace_radeon_vm_set_page(pe, addr, count, incr, r600_flags);
++ trace_radeon_vm_set_page(pe, addr, count, incr, flags);
+
+- if (flags & RADEON_VM_PAGE_SYSTEM) {
++ if (flags & R600_PTE_SYSTEM) {
+ while (count) {
+ ndw = count * 2;
+ if (ndw > 0xFFFFE)
+@@ -93,16 +92,10 @@ void si_dma_vm_set_page(struct radeon_device *rdev,
+ ib->ptr[ib->length_dw++] = pe;
+ ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;
+ for (; ndw > 0; ndw -= 2, --count, pe += 8) {
+- if (flags & RADEON_VM_PAGE_SYSTEM) {
+- value = radeon_vm_map_gart(rdev, addr);
+- value &= 0xFFFFFFFFFFFFF000ULL;
+- } else if (flags & RADEON_VM_PAGE_VALID) {
+- value = addr;
+- } else {
+- value = 0;
+- }
++ value = radeon_vm_map_gart(rdev, addr);
++ value &= 0xFFFFFFFFFFFFF000ULL;
+ addr += incr;
+- value |= r600_flags;
++ value |= flags;
+ ib->ptr[ib->length_dw++] = value;
+ ib->ptr[ib->length_dw++] = upper_32_bits(value);
+ }
+@@ -113,7 +106,7 @@ void si_dma_vm_set_page(struct radeon_device *rdev,
+ if (ndw > 0xFFFFE)
+ ndw = 0xFFFFE;
+
+- if (flags & RADEON_VM_PAGE_VALID)
++ if (flags & R600_PTE_VALID)
+ value = addr;
+ else
+ value = 0;
+@@ -121,7 +114,7 @@ void si_dma_vm_set_page(struct radeon_device *rdev,
+ ib->ptr[ib->length_dw++] = DMA_PTE_PDE_PACKET(ndw);
+ ib->ptr[ib->length_dw++] = pe; /* dst addr */
+ ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;
+- ib->ptr[ib->length_dw++] = r600_flags; /* mask */
++ ib->ptr[ib->length_dw++] = flags; /* mask */
+ ib->ptr[ib->length_dw++] = 0;
+ ib->ptr[ib->length_dw++] = value; /* value */
+ ib->ptr[ib->length_dw++] = upper_32_bits(value);
+--
+1.9.1
+
generated by cgit 1.2.3-korg (git 2.39.0) at 2024-04-20 01:26:56 +0000