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-rw-r--r--common/recipes-kernel/linux/files/1148-refine-pg-code-for-gfx_v8.patch204
1 files changed, 0 insertions, 204 deletions
diff --git a/common/recipes-kernel/linux/files/1148-refine-pg-code-for-gfx_v8.patch b/common/recipes-kernel/linux/files/1148-refine-pg-code-for-gfx_v8.patch
deleted file mode 100644
index 4416497c..00000000
--- a/common/recipes-kernel/linux/files/1148-refine-pg-code-for-gfx_v8.patch
+++ /dev/null
@@ -1,204 +0,0 @@
-From c5ef870413c64c25cfe2a646c395b0c0d293a4f5 Mon Sep 17 00:00:00 2001
-From: Ravi Patlegar <ravi.patlegar@amd.com>
-Date: Tue, 13 Dec 2016 16:28:54 +0530
-Subject: [PATCH 10/10] refine pg code for gfx_v8.
-
-1. bit CP_PG_DISABLE was reversed.
-2. load RLC_SRM_INDEX_CNTL_ADDR/DATA_x pairs
- with valid addr/data.
-3. always init gfx pg.
-4. delete repeated check for pg mask.
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Signed-off-by: Ravi Patlegar <ravi.patlegar@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 +
- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 118 ++++++++++++----------------------
- 2 files changed, 44 insertions(+), 76 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index 40497c2..af04d3b 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -2211,6 +2211,8 @@ bool amdgpu_device_has_dal_support(struct amdgpu_device *adev);
- #define REG_GET_FIELD(value, reg, field) \
- (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
-
-+#define WREG32_FIELD(reg, field, val) \
-+ WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
- /*
- * BIOS helpers.
- */
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-index d1cb4db..b4c41f9 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-@@ -3934,8 +3934,10 @@ static int gfx_v8_0_init_save_restore_list(struct amdgpu_device *adev)
- temp = mmRLC_SRM_INDEX_CNTL_ADDR_0;
- data = mmRLC_SRM_INDEX_CNTL_DATA_0;
- for (i = 0; i < sizeof(unique_indices) / sizeof(int); i++) {
-- amdgpu_mm_wreg(adev, temp + i, unique_indices[i] & 0x3FFFF, false);
-- amdgpu_mm_wreg(adev, data + i, unique_indices[i] >> 20, false);
-+ if (unique_indices[i] != 0) {
-+ amdgpu_mm_wreg(adev, temp + i, unique_indices[i] & 0x3FFFF, false);
-+ amdgpu_mm_wreg(adev, data + i, unique_indices[i] >> 20, false);
-+ }
- }
- kfree(register_list_format);
-
-@@ -3955,32 +3957,17 @@ static void gfx_v8_0_init_power_gating(struct amdgpu_device *adev)
- {
- uint32_t data;
-
-- if (adev->pg_flags & (AMDGPU_PG_SUPPORT_GFX_PG |
-- AMDGPU_PG_SUPPORT_GFX_SMG |
-- AMDGPU_PG_SUPPORT_GFX_DMG)) {
-- data = RREG32(mmCP_RB_WPTR_POLL_CNTL);
-- data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK;
-- data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
-- WREG32(mmCP_RB_WPTR_POLL_CNTL, data);
--
-- data = 0;
-- data |= (0x10 << RLC_PG_DELAY__POWER_UP_DELAY__SHIFT);
-- data |= (0x10 << RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT);
-- data |= (0x10 << RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT);
-- data |= (0x10 << RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT);
-- WREG32(mmRLC_PG_DELAY, data);
--
-- data = RREG32(mmRLC_PG_DELAY_2);
-- data &= ~RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK;
-- data |= (0x3 << RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT);
-- WREG32(mmRLC_PG_DELAY_2, data);
--
-- data = RREG32(mmRLC_AUTO_PG_CTRL);
-- data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;
-- data |= (0x55f0 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
-- WREG32(mmRLC_AUTO_PG_CTRL, data);
-- }
-- }
-+ WREG32_FIELD(CP_RB_WPTR_POLL_CNTL, IDLE_POLL_COUNT, 0x60);
-+
-+ data = REG_SET_FIELD(0, RLC_PG_DELAY, POWER_UP_DELAY, 0x10);
-+ data = REG_SET_FIELD(data, RLC_PG_DELAY, POWER_DOWN_DELAY, 0x10);
-+ data = REG_SET_FIELD(data, RLC_PG_DELAY, CMD_PROPAGATE_DELAY, 0x10);
-+ data = REG_SET_FIELD(data, RLC_PG_DELAY, MEM_SLEEP_DELAY, 0x10);
-+ WREG32(mmRLC_PG_DELAY, data);
-+
-+ WREG32_FIELD(RLC_PG_DELAY_2, SERDES_CMD_DELAY, 0x3);
-+ WREG32_FIELD(RLC_AUTO_PG_CTRL, GRBM_REG_SAVE_GFX_IDLE_THRESHOLD, 0x55f0);
-+}
-
- static void cz_enable_sck_slow_down_on_power_up(struct amdgpu_device *adev,
- bool enable)
-@@ -4016,18 +4003,8 @@ static void cz_enable_sck_slow_down_on_power_down(struct amdgpu_device *adev,
-
- static void cz_enable_cp_power_gating(struct amdgpu_device *adev, bool enable)
- {
-- u32 data, orig;
--
-- orig = data = RREG32(mmRLC_PG_CNTL);
--
-- if (enable)
-- data &= ~RLC_PG_CNTL__CP_PG_DISABLE_MASK;
-- else
-- data |= RLC_PG_CNTL__CP_PG_DISABLE_MASK;
--
-- if (orig != data)
-- WREG32(mmRLC_PG_CNTL, data);
-- }
-+ WREG32_FIELD(RLC_PG_CNTL, CP_PG_DISABLE, enable ? 0 : 1);
-+}
-
- static void polaris11_init_power_gating(struct amdgpu_device *adev)
- {
-@@ -4062,39 +4039,30 @@ static void polaris11_init_power_gating(struct amdgpu_device *adev)
-
- static void gfx_v8_0_init_pg(struct amdgpu_device *adev)
- {
-- if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
-- AMD_PG_SUPPORT_GFX_SMG |
-- AMD_PG_SUPPORT_GFX_DMG |
-- AMD_PG_SUPPORT_CP |
-- AMD_PG_SUPPORT_GDS |
-- AMD_PG_SUPPORT_RLC_SMU_HS)) {
-- gfx_v8_0_init_csb(adev);
-- gfx_v8_0_init_save_restore_list(adev);
-- gfx_v8_0_enable_save_restore_machine(adev);
-+ gfx_v8_0_init_csb(adev);
-+ gfx_v8_0_init_save_restore_list(adev);
-+ gfx_v8_0_enable_save_restore_machine(adev);
-
-- if ((adev->asic_type == CHIP_CARRIZO) ||
-- (adev->asic_type == CHIP_STONEY)) {
-- struct amdgpu_cu_info cu_info;
--
-- gfx_v8_0_get_cu_info(adev, &cu_info);
--
-- WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8);
-- gfx_v8_0_init_power_gating(adev);
-- WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, cu_info.ao_cu_mask);
-- if (adev->pg_flags & AMDGPU_PG_SUPPORT_RLC_SMU_HS) {
-- cz_enable_sck_slow_down_on_power_up(adev, true);
-- cz_enable_sck_slow_down_on_power_down(adev, true);
-- } else {
-- cz_enable_sck_slow_down_on_power_up(adev, false);
-- cz_enable_sck_slow_down_on_power_down(adev, false);
-- }
-- if (adev->pg_flags & AMDGPU_PG_SUPPORT_CP)
-- cz_enable_cp_power_gating(adev, true);
-- else
-- cz_enable_cp_power_gating(adev, false);
-- } else if (adev->asic_type == CHIP_POLARIS11) {
-- polaris11_init_power_gating(adev);
-+ if ((adev->asic_type == CHIP_CARRIZO) ||
-+ (adev->asic_type == CHIP_STONEY)) {
-+ struct amdgpu_cu_info cu_info;
-+ gfx_v8_0_get_cu_info(adev, &cu_info);
-+ WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8);
-+ gfx_v8_0_init_power_gating(adev);
-+ WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, cu_info.ao_cu_mask);
-+ if (adev->pg_flags & AMDGPU_PG_SUPPORT_RLC_SMU_HS) {
-+ cz_enable_sck_slow_down_on_power_up(adev, true);
-+ cz_enable_sck_slow_down_on_power_down(adev, true);
-+ } else {
-+ cz_enable_sck_slow_down_on_power_up(adev, false);
-+ cz_enable_sck_slow_down_on_power_down(adev, false);
- }
-+ if (adev->pg_flags & AMDGPU_PG_SUPPORT_CP)
-+ cz_enable_cp_power_gating(adev, true);
-+ else
-+ cz_enable_cp_power_gating(adev, false);
-+ } else if (adev->asic_type == CHIP_POLARIS11) {
-+ polaris11_init_power_gating(adev);
- }
- }
-
-@@ -5513,7 +5481,7 @@ static void cz_update_gfx_cg_power_gating(struct amdgpu_device *adev,
- if (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_PIPELINE)
- cz_enable_gfx_pipeline_power_gating(adev, true);
- } else {
-- cz_enable_gfx_cg_power_gating(adev, false);
-+ cz_enable_gfx_cg_power_gating(adev, true);
- cz_enable_gfx_pipeline_power_gating(adev, false);
- }
- }
-@@ -5524,14 +5492,12 @@ static int gfx_v8_0_set_powergating_state(void *handle,
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- bool enable = (state == AMD_PG_STATE_GATE) ? true : false;
-
-- if (!(adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_PG))
-- return 0;
-
- switch (adev->asic_type) {
- case CHIP_CARRIZO:
- case CHIP_STONEY:
-- if (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_PG)
-- cz_update_gfx_cg_power_gating(adev, enable);
-+
-+ cz_update_gfx_cg_power_gating(adev, enable);
-
- if ((adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_SMG) && enable)
- gfx_v8_0_enable_gfx_static_mg_power_gating(adev, true);
---
-2.7.4
-
generated by cgit 1.2.3-korg (git 2.39.0) at 2024-04-25 00:53:19 +0000