diff options
Diffstat (limited to 'common/recipes-kernel/linux/files/1084-drm-amdgpu-gfx8-add-state-setup-for-CZ-ST-GFX-power-.patch')
-rw-r--r-- | common/recipes-kernel/linux/files/1084-drm-amdgpu-gfx8-add-state-setup-for-CZ-ST-GFX-power-.patch | 240 |
1 files changed, 0 insertions, 240 deletions
diff --git a/common/recipes-kernel/linux/files/1084-drm-amdgpu-gfx8-add-state-setup-for-CZ-ST-GFX-power-.patch b/common/recipes-kernel/linux/files/1084-drm-amdgpu-gfx8-add-state-setup-for-CZ-ST-GFX-power-.patch deleted file mode 100644 index f937fa7e..00000000 --- a/common/recipes-kernel/linux/files/1084-drm-amdgpu-gfx8-add-state-setup-for-CZ-ST-GFX-power-.patch +++ /dev/null @@ -1,240 +0,0 @@ -From ec6230410b55c2f2aae42b8c7e693653b71af6c2 Mon Sep 17 00:00:00 2001 -From: Alex Deucher <alexander.deucher@amd.com> -Date: Fri, 1 Jul 2016 15:49:29 +0530 -Subject: [PATCH 1084/1110] drm/amdgpu/gfx8: add state setup for CZ/ST GFX - power gating - -This sets up the CP jump table and GDS buffer and sets the -PG state registers. - -Signed-off-by: Alex Deucher <alexander.deucher@amd.com> -Acked-by: Tom St Denis <tom.stdenis@amd.com> -Signed-off-by: Kalyan Alle <kalyan.alle@amd.com> ---- - drivers/gpu/drm/amd/amdgpu/amdgpu.h | 4 + - drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 159 ++++++++++++++++++++++++++++++++++ - 2 files changed, 163 insertions(+) - -diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h -index 0f7de1b..8127e81 100644 ---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h -+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h -@@ -131,6 +131,10 @@ extern unsigned amdgpu_pcie_lane_cap; - #define AMDGPU_RESET_VCE (1 << 13) - #define AMDGPU_RESET_VCE1 (1 << 14) - -+#define AMDGPU_PG_SUPPORT_GFX_PG (1 << 0) -+#define AMDGPU_PG_SUPPORT_GFX_SMG (1 << 1) -+#define AMDGPU_PG_SUPPORT_GFX_DMG (1 << 2) -+ - /* GFX current status */ - #define AMDGPU_GFX_NORMAL_MODE 0x00000000L - #define AMDGPU_GFX_SAFE_MODE 0x00000001L -diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c -index d35fa43..951381c 100644 ---- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c -+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c -@@ -29,6 +29,7 @@ - #include "amdgpu_ucode.h" - #include "amdgpu_atombios.h" - #include "clearstate_vi.h" -+#include "gfx_v8_0.h" - - #include "gmc/gmc_8_2_d.h" - #include "gmc/gmc_8_2_sh_mask.h" -@@ -1126,6 +1127,71 @@ static void gfx_v8_0_get_csb_buffer(struct amdgpu_device *adev, - buffer[count++] = cpu_to_le32(0); - } - -+static void cz_init_cp_jump_table(struct amdgpu_device *adev) -+{ -+ const __le32 *fw_data; -+ volatile u32 *dst_ptr; -+ int me, i, max_me = 4; -+ u32 bo_offset = 0; -+ u32 table_offset, table_size; -+ -+ if (adev->asic_type == CHIP_CARRIZO) -+ max_me = 5; -+ -+ /* write the cp table buffer */ -+ dst_ptr = adev->gfx.rlc.cp_table_ptr; -+ for (me = 0; me < max_me; me++) { -+ if (me == 0) { -+ const struct gfx_firmware_header_v1_0 *hdr = -+ (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; -+ fw_data = (const __le32 *) -+ (adev->gfx.ce_fw->data + -+ le32_to_cpu(hdr->header.ucode_array_offset_bytes)); -+ table_offset = le32_to_cpu(hdr->jt_offset); -+ table_size = le32_to_cpu(hdr->jt_size); -+ } else if (me == 1) { -+ const struct gfx_firmware_header_v1_0 *hdr = -+ (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; -+ fw_data = (const __le32 *) -+ (adev->gfx.pfp_fw->data + -+ le32_to_cpu(hdr->header.ucode_array_offset_bytes)); -+ table_offset = le32_to_cpu(hdr->jt_offset); -+ table_size = le32_to_cpu(hdr->jt_size); -+ } else if (me == 2) { -+ const struct gfx_firmware_header_v1_0 *hdr = -+ (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; -+ fw_data = (const __le32 *) -+ (adev->gfx.me_fw->data + -+ le32_to_cpu(hdr->header.ucode_array_offset_bytes)); -+ table_offset = le32_to_cpu(hdr->jt_offset); -+ table_size = le32_to_cpu(hdr->jt_size); -+ } else if (me == 3) { -+ const struct gfx_firmware_header_v1_0 *hdr = -+ (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; -+ fw_data = (const __le32 *) -+ (adev->gfx.mec_fw->data + -+ le32_to_cpu(hdr->header.ucode_array_offset_bytes)); -+ table_offset = le32_to_cpu(hdr->jt_offset); -+ table_size = le32_to_cpu(hdr->jt_size); -+ } else if (me == 4) { -+ const struct gfx_firmware_header_v1_0 *hdr = -+ (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data; -+ fw_data = (const __le32 *) -+ (adev->gfx.mec2_fw->data + -+ le32_to_cpu(hdr->header.ucode_array_offset_bytes)); -+ table_offset = le32_to_cpu(hdr->jt_offset); -+ table_size = le32_to_cpu(hdr->jt_size); -+ } -+ -+ for (i = 0; i < table_size; i ++) { -+ dst_ptr[bo_offset + i] = -+ cpu_to_le32(le32_to_cpu(fw_data[table_offset + i])); -+ } -+ -+ bo_offset += table_size; -+ } -+} -+ - static void gfx_v8_0_rlc_fini(struct amdgpu_device *adev) - { - int r; -@@ -1141,6 +1207,18 @@ static void gfx_v8_0_rlc_fini(struct amdgpu_device *adev) - amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj); - adev->gfx.rlc.clear_state_obj = NULL; - } -+ -+ /* jump table block */ -+ if (adev->gfx.rlc.cp_table_obj) { -+ r = amdgpu_bo_reserve(adev->gfx.rlc.cp_table_obj, false); -+ if (unlikely(r != 0)) -+ dev_warn(adev->dev, "(%d) reserve RLC cp table bo failed\n", r); -+ amdgpu_bo_unpin(adev->gfx.rlc.cp_table_obj); -+ amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj); -+ -+ amdgpu_bo_unref(&adev->gfx.rlc.cp_table_obj); -+ adev->gfx.rlc.cp_table_obj = NULL; -+ } - } - - static int gfx_v8_0_rlc_init(struct amdgpu_device *adev) -@@ -1197,6 +1275,45 @@ static int gfx_v8_0_rlc_init(struct amdgpu_device *adev) - amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); - } - -+ if ((adev->asic_type == CHIP_CARRIZO) || -+ (adev->asic_type == CHIP_STONEY)) { -+ adev->gfx.rlc.cp_table_size = (96 * 5 * 4) + (64 * 1024); /* JT + GDS */ -+ if (adev->gfx.rlc.cp_table_obj == NULL) { -+ r = amdgpu_bo_create(adev, adev->gfx.rlc.cp_table_size, PAGE_SIZE, true, -+ AMDGPU_GEM_DOMAIN_VRAM, -+ AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, -+ NULL, NULL, -+ &adev->gfx.rlc.cp_table_obj); -+ if (r) { -+ dev_warn(adev->dev, "(%d) create RLC cp table bo failed\n", r); -+ return r; -+ } -+ } -+ -+ r = amdgpu_bo_reserve(adev->gfx.rlc.cp_table_obj, false); -+ if (unlikely(r != 0)) { -+ dev_warn(adev->dev, "(%d) reserve RLC cp table bo failed\n", r); -+ return r; -+ } -+ r = amdgpu_bo_pin(adev->gfx.rlc.cp_table_obj, AMDGPU_GEM_DOMAIN_VRAM, -+ &adev->gfx.rlc.cp_table_gpu_addr); -+ if (r) { -+ amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj); -+ dev_warn(adev->dev, "(%d) pin RLC cp_table bo failed\n", r); -+ return r; -+ } -+ r = amdgpu_bo_kmap(adev->gfx.rlc.cp_table_obj, (void **)&adev->gfx.rlc.cp_table_ptr); -+ if (r) { -+ dev_warn(adev->dev, "(%d) map RLC cp table bo failed\n", r); -+ return r; -+ } -+ -+ cz_init_cp_jump_table(adev); -+ -+ amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj); -+ amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj); -+ } -+ - return 0; - } - -@@ -3658,6 +3775,37 @@ static void gfx_v8_0_enable_save_restore_machine(struct amdgpu_device *adev) - WREG32(mmRLC_SRM_CNTL, data); - } - -+static void gfx_v8_0_init_power_gating(struct amdgpu_device *adev) -+{ -+ uint32_t data; -+ -+ if (adev->pg_flags & (AMDGPU_PG_SUPPORT_GFX_PG | -+ AMDGPU_PG_SUPPORT_GFX_SMG | -+ AMDGPU_PG_SUPPORT_GFX_DMG)) { -+ data = RREG32(mmCP_RB_WPTR_POLL_CNTL); -+ data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK; -+ data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); -+ WREG32(mmCP_RB_WPTR_POLL_CNTL, data); -+ -+ data = 0; -+ data |= (0x10 << RLC_PG_DELAY__POWER_UP_DELAY__SHIFT); -+ data |= (0x10 << RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT); -+ data |= (0x10 << RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT); -+ data |= (0x10 << RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT); -+ WREG32(mmRLC_PG_DELAY, data); -+ -+ data = RREG32(mmRLC_PG_DELAY_2); -+ data &= ~RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK; -+ data |= (0x3 << RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT); -+ WREG32(mmRLC_PG_DELAY_2, data); -+ -+ data = RREG32(mmRLC_AUTO_PG_CTRL); -+ data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK; -+ data |= (0x55f0 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT); -+ WREG32(mmRLC_AUTO_PG_CTRL, data); -+ } -+ } -+ - static void polaris11_init_power_gating(struct amdgpu_device *adev) - { - uint32_t data; -@@ -3700,6 +3848,17 @@ static void gfx_v8_0_init_pg(struct amdgpu_device *adev) - gfx_v8_0_init_csb(adev); - gfx_v8_0_init_save_restore_list(adev); - gfx_v8_0_enable_save_restore_machine(adev); -+ -+ if ((adev->asic_type == CHIP_CARRIZO) || -+ (adev->asic_type == CHIP_STONEY)) { -+ struct amdgpu_cu_info cu_info; -+ -+ gfx_v8_0_get_cu_info(adev, &cu_info); -+ -+ WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8); -+ gfx_v8_0_init_power_gating(adev); -+ WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, cu_info.ao_cu_mask); -+ } - - if (adev->asic_type == CHIP_POLARIS11) - polaris11_init_power_gating(adev); --- -2.7.4 - |