diff options
Diffstat (limited to 'common/recipes-kernel/linux/files/1065-drm-amdgpu-uvd6-add-bypass-support-for-fiji-v2.patch')
| -rw-r--r-- | common/recipes-kernel/linux/files/1065-drm-amdgpu-uvd6-add-bypass-support-for-fiji-v2.patch | 63 |
1 files changed, 0 insertions, 63 deletions
diff --git a/common/recipes-kernel/linux/files/1065-drm-amdgpu-uvd6-add-bypass-support-for-fiji-v2.patch b/common/recipes-kernel/linux/files/1065-drm-amdgpu-uvd6-add-bypass-support-for-fiji-v2.patch deleted file mode 100644 index 953a2687..00000000 --- a/common/recipes-kernel/linux/files/1065-drm-amdgpu-uvd6-add-bypass-support-for-fiji-v2.patch +++ /dev/null @@ -1,63 +0,0 @@ -From c97288faffbb08ce5ae43bcbe32f06c8ba7be0f6 Mon Sep 17 00:00:00 2001 -From: Alex Deucher <alexander.deucher@amd.com> -Date: Fri, 29 Apr 2016 11:44:32 -0400 -Subject: [PATCH 1065/1110] drm/amdgpu/uvd6: add bypass support for fiji (v2) - -Handle uvd clock bypass settings as part of clockgating -setup. - -v2: fix gate logic - -Signed-off-by: Alex Deucher <alexander.deucher@amd.com> -Reviewed-by: Eric Huang <JinHuiEric.Huang@amd.com> ---- - drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 19 +++++++++++++++++++ - 1 file changed, 19 insertions(+) - -diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c -index 5665a4f..d015cb0 100644 ---- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c -+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c -@@ -31,6 +31,8 @@ - #include "uvd/uvd_6_0_sh_mask.h" - #include "oss/oss_2_0_d.h" - #include "oss/oss_2_0_sh_mask.h" -+#include "smu/smu_7_1_3_d.h" -+#include "smu/smu_7_1_3_sh_mask.h" - #include "vi.h" - - static void uvd_v6_0_set_ring_funcs(struct amdgpu_device *adev); -@@ -823,6 +825,20 @@ static void uvd_v6_0_set_hw_clock_gating(struct amdgpu_device *adev) - } - #endif - -+static void uvd_v6_set_bypass_mode(struct amdgpu_device *adev, bool enable) -+{ -+ u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL); -+ -+ if (enable) -+ tmp |= (GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK | -+ GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK); -+ else -+ tmp &= ~(GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK | -+ GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK); -+ -+ WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp); -+} -+ - static int uvd_v6_0_set_clockgating_state(void *handle, - enum amd_clockgating_state state) - { -@@ -830,6 +846,9 @@ static int uvd_v6_0_set_clockgating_state(void *handle, - bool enable = (state == AMD_CG_STATE_GATE) ? true : false; - static int curstate = -1; - -+ if (adev->asic_type == CHIP_FIJI) -+ uvd_v6_set_bypass_mode(adev, enable); -+ - if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) - return 0; - --- -2.7.4 - |