diff options
Diffstat (limited to 'common/recipes-kernel/linux/files/1022-drm-amd-amdgpu-Drop-print_status-callbacks.patch')
| -rw-r--r-- | common/recipes-kernel/linux/files/1022-drm-amd-amdgpu-Drop-print_status-callbacks.patch | 2641 |
1 files changed, 0 insertions, 2641 deletions
diff --git a/common/recipes-kernel/linux/files/1022-drm-amd-amdgpu-Drop-print_status-callbacks.patch b/common/recipes-kernel/linux/files/1022-drm-amd-amdgpu-Drop-print_status-callbacks.patch deleted file mode 100644 index 9f20c469..00000000 --- a/common/recipes-kernel/linux/files/1022-drm-amd-amdgpu-Drop-print_status-callbacks.patch +++ /dev/null @@ -1,2641 +0,0 @@ -From c30a6205fb4acb98c44d6529c58c160f77dead49 Mon Sep 17 00:00:00 2001 -From: Tom St Denis <tom.stdenis@amd.com> -Date: Fri, 15 Apr 2016 10:50:50 -0400 -Subject: [PATCH 1022/1110] drm/amd/amdgpu: Drop print_status callbacks. - -First patch in series to move to user mode -debug tools we're removing the print_status callbacks. - -Signed-off-by: Tom St Denis <tom.stdenis@amd.com> -Reviewed-by: Alex Deucher <alexander.deucher@amd.com> ---- - drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c | 8 - - drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 42 ----- - drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c | 10 - - drivers/gpu/drm/amd/amdgpu/ci_dpm.c | 210 --------------------- - drivers/gpu/drm/amd/amdgpu/cik.c | 6 - - drivers/gpu/drm/amd/amdgpu/cik_ih.c | 34 ---- - drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 56 ------ - drivers/gpu/drm/amd/amdgpu/cz_dpm.c | 1 - - drivers/gpu/drm/amd/amdgpu/cz_ih.c | 34 ---- - drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 12 -- - drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 12 -- - drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 12 -- - drivers/gpu/drm/amd/amdgpu/fiji_dpm.c | 1 - - drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 253 -------------------------- - drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 182 ------------------ - drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 113 ------------ - drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 110 ----------- - drivers/gpu/drm/amd/amdgpu/iceland_dpm.c | 1 - - drivers/gpu/drm/amd/amdgpu/iceland_ih.c | 34 ---- - drivers/gpu/drm/amd/amdgpu/kv_dpm.c | 57 ------ - drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 54 ------ - drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 56 ------ - drivers/gpu/drm/amd/amdgpu/tonga_dpm.c | 1 - - drivers/gpu/drm/amd/amdgpu/tonga_ih.c | 34 ---- - drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 112 ------------ - drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 115 ------------ - drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 107 ----------- - drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 70 ------- - drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 68 ------- - drivers/gpu/drm/amd/amdgpu/vi.c | 6 - - drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c | 8 - - drivers/gpu/drm/amd/include/amd_shared.h | 2 - - drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 5 - - 33 files changed, 1826 deletions(-) - -diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c -index b7b583c..49838df 100644 ---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c -+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c -@@ -467,13 +467,6 @@ static int acp_soft_reset(void *handle) - return 0; - } - --static void acp_print_status(void *handle) --{ -- struct amdgpu_device *adev = (struct amdgpu_device *)handle; -- -- dev_info(adev->dev, "ACP STATUS\n"); --} -- - static int acp_set_clockgating_state(void *handle, - enum amd_clockgating_state state) - { -@@ -498,7 +491,6 @@ const struct amd_ip_funcs acp_ip_funcs = { - .is_idle = acp_is_idle, - .wait_for_idle = acp_wait_for_idle, - .soft_reset = acp_soft_reset, -- .print_status = acp_print_status, - .set_clockgating_state = acp_set_clockgating_state, - .set_powergating_state = acp_set_powergating_state, - }; -diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c -index 8885e9e..8a5e3f7 100644 ---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c -+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c -@@ -47,8 +47,6 @@ - - static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev); - static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev); --static int amdgpu_debugfs_status_init(struct amdgpu_device *adev); -- - - static const char *amdgpu_asic_name[] = { - "BONAIRE", -@@ -1110,15 +1108,6 @@ const struct amdgpu_ip_block_version * amdgpu_get_ip_block( - return NULL; - } - --void amdgpu_print_status(struct amdgpu_device *adev) --{ -- int i; -- -- for (i = 0; i < adev->num_ip_blocks; i++) -- if (adev->ip_blocks[i].funcs->print_status) -- adev->ip_blocks[i].funcs->print_status(adev); --} -- - /** - * amdgpu_ip_block_version_cmp - * -@@ -1269,8 +1258,6 @@ static int amdgpu_init(struct amdgpu_device *adev) - adev->ip_block_status[i].hw = true; - } - -- amdgpu_debugfs_status_init(adev); -- - return 0; - } - -@@ -2242,32 +2229,3 @@ static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev) - } - static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) { } - #endif -- --/* -- * Status debugfs -- */ --#if defined(CONFIG_DEBUG_FS) --static int amdgpu_debugfs_print_status(struct seq_file *m, void *data) --{ -- struct drm_info_node *node = (struct drm_info_node *)m->private; -- struct drm_device *dev = node->minor->dev; -- struct amdgpu_device *adev = dev->dev_private; -- -- amdgpu_print_status(adev); -- -- return 0; --} -- --static const struct drm_info_list amdgpu_debugfs_status_list[] = { -- {"amdgpu_print_status", &amdgpu_debugfs_print_status, 0, NULL}, --}; --#endif -- --static int amdgpu_debugfs_status_init(struct amdgpu_device *adev) --{ --#if defined(CONFIG_DEBUG_FS) -- return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_status_list, 1); --#else -- return 0; --#endif --} -diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c -index f315995..be56595 100644 ---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c -+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c -@@ -303,15 +303,6 @@ static int amdgpu_pp_soft_reset(void *handle) - return ret; - } - --static void amdgpu_pp_print_status(void *handle) --{ -- struct amdgpu_device *adev = (struct amdgpu_device *)handle; -- -- if (adev->powerplay.ip_funcs->print_status) -- adev->powerplay.ip_funcs->print_status( -- adev->powerplay.pp_handle); --} -- - const struct amd_ip_funcs amdgpu_pp_ip_funcs = { - .early_init = amdgpu_pp_early_init, - .late_init = amdgpu_pp_late_init, -@@ -324,7 +315,6 @@ const struct amd_ip_funcs amdgpu_pp_ip_funcs = { - .is_idle = amdgpu_pp_is_idle, - .wait_for_idle = amdgpu_pp_wait_for_idle, - .soft_reset = amdgpu_pp_soft_reset, -- .print_status = amdgpu_pp_print_status, - .set_clockgating_state = amdgpu_pp_set_clockgating_state, - .set_powergating_state = amdgpu_pp_set_powergating_state, - }; -diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c -index 1f9109d..90f83b2 100644 ---- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c -+++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c -@@ -6309,215 +6309,6 @@ static int ci_dpm_wait_for_idle(void *handle) - return 0; - } - --static void ci_dpm_print_status(void *handle) --{ -- struct amdgpu_device *adev = (struct amdgpu_device *)handle; -- -- dev_info(adev->dev, "CIK DPM registers\n"); -- dev_info(adev->dev, " BIOS_SCRATCH_4=0x%08X\n", -- RREG32(mmBIOS_SCRATCH_4)); -- dev_info(adev->dev, " MC_ARB_DRAM_TIMING=0x%08X\n", -- RREG32(mmMC_ARB_DRAM_TIMING)); -- dev_info(adev->dev, " MC_ARB_DRAM_TIMING2=0x%08X\n", -- RREG32(mmMC_ARB_DRAM_TIMING2)); -- dev_info(adev->dev, " MC_ARB_BURST_TIME=0x%08X\n", -- RREG32(mmMC_ARB_BURST_TIME)); -- dev_info(adev->dev, " MC_ARB_DRAM_TIMING_1=0x%08X\n", -- RREG32(mmMC_ARB_DRAM_TIMING_1)); -- dev_info(adev->dev, " MC_ARB_DRAM_TIMING2_1=0x%08X\n", -- RREG32(mmMC_ARB_DRAM_TIMING2_1)); -- dev_info(adev->dev, " MC_CG_CONFIG=0x%08X\n", -- RREG32(mmMC_CG_CONFIG)); -- dev_info(adev->dev, " MC_ARB_CG=0x%08X\n", -- RREG32(mmMC_ARB_CG)); -- dev_info(adev->dev, " DIDT_SQ_CTRL0=0x%08X\n", -- RREG32_DIDT(ixDIDT_SQ_CTRL0)); -- dev_info(adev->dev, " DIDT_DB_CTRL0=0x%08X\n", -- RREG32_DIDT(ixDIDT_DB_CTRL0)); -- dev_info(adev->dev, " DIDT_TD_CTRL0=0x%08X\n", -- RREG32_DIDT(ixDIDT_TD_CTRL0)); -- dev_info(adev->dev, " DIDT_TCP_CTRL0=0x%08X\n", -- RREG32_DIDT(ixDIDT_TCP_CTRL0)); -- dev_info(adev->dev, " CG_THERMAL_INT=0x%08X\n", -- RREG32_SMC(ixCG_THERMAL_INT)); -- dev_info(adev->dev, " CG_THERMAL_CTRL=0x%08X\n", -- RREG32_SMC(ixCG_THERMAL_CTRL)); -- dev_info(adev->dev, " GENERAL_PWRMGT=0x%08X\n", -- RREG32_SMC(ixGENERAL_PWRMGT)); -- dev_info(adev->dev, " MC_SEQ_CNTL_3=0x%08X\n", -- RREG32(mmMC_SEQ_CNTL_3)); -- dev_info(adev->dev, " LCAC_MC0_CNTL=0x%08X\n", -- RREG32_SMC(ixLCAC_MC0_CNTL)); -- dev_info(adev->dev, " LCAC_MC1_CNTL=0x%08X\n", -- RREG32_SMC(ixLCAC_MC1_CNTL)); -- dev_info(adev->dev, " LCAC_CPL_CNTL=0x%08X\n", -- RREG32_SMC(ixLCAC_CPL_CNTL)); -- dev_info(adev->dev, " SCLK_PWRMGT_CNTL=0x%08X\n", -- RREG32_SMC(ixSCLK_PWRMGT_CNTL)); -- dev_info(adev->dev, " BIF_LNCNT_RESET=0x%08X\n", -- RREG32(mmBIF_LNCNT_RESET)); -- dev_info(adev->dev, " FIRMWARE_FLAGS=0x%08X\n", -- RREG32_SMC(ixFIRMWARE_FLAGS)); -- dev_info(adev->dev, " CG_SPLL_FUNC_CNTL=0x%08X\n", -- RREG32_SMC(ixCG_SPLL_FUNC_CNTL)); -- dev_info(adev->dev, " CG_SPLL_FUNC_CNTL_2=0x%08X\n", -- RREG32_SMC(ixCG_SPLL_FUNC_CNTL_2)); -- dev_info(adev->dev, " CG_SPLL_FUNC_CNTL_3=0x%08X\n", -- RREG32_SMC(ixCG_SPLL_FUNC_CNTL_3)); -- dev_info(adev->dev, " CG_SPLL_FUNC_CNTL_4=0x%08X\n", -- RREG32_SMC(ixCG_SPLL_FUNC_CNTL_4)); -- dev_info(adev->dev, " CG_SPLL_SPREAD_SPECTRUM=0x%08X\n", -- RREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM)); -- dev_info(adev->dev, " CG_SPLL_SPREAD_SPECTRUM_2=0x%08X\n", -- RREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM_2)); -- dev_info(adev->dev, " DLL_CNTL=0x%08X\n", -- RREG32(mmDLL_CNTL)); -- dev_info(adev->dev, " MCLK_PWRMGT_CNTL=0x%08X\n", -- RREG32(mmMCLK_PWRMGT_CNTL)); -- dev_info(adev->dev, " MPLL_AD_FUNC_CNTL=0x%08X\n", -- RREG32(mmMPLL_AD_FUNC_CNTL)); -- dev_info(adev->dev, " MPLL_DQ_FUNC_CNTL=0x%08X\n", -- RREG32(mmMPLL_DQ_FUNC_CNTL)); -- dev_info(adev->dev, " MPLL_FUNC_CNTL=0x%08X\n", -- RREG32(mmMPLL_FUNC_CNTL)); -- dev_info(adev->dev, " MPLL_FUNC_CNTL_1=0x%08X\n", -- RREG32(mmMPLL_FUNC_CNTL_1)); -- dev_info(adev->dev, " MPLL_FUNC_CNTL_2=0x%08X\n", -- RREG32(mmMPLL_FUNC_CNTL_2)); -- dev_info(adev->dev, " MPLL_SS1=0x%08X\n", -- RREG32(mmMPLL_SS1)); -- dev_info(adev->dev, " MPLL_SS2=0x%08X\n", -- RREG32(mmMPLL_SS2)); -- dev_info(adev->dev, " CG_DISPLAY_GAP_CNTL=0x%08X\n", -- RREG32_SMC(ixCG_DISPLAY_GAP_CNTL)); -- dev_info(adev->dev, " CG_DISPLAY_GAP_CNTL2=0x%08X\n", -- RREG32_SMC(ixCG_DISPLAY_GAP_CNTL2)); -- dev_info(adev->dev, " CG_STATIC_SCREEN_PARAMETER=0x%08X\n", -- RREG32_SMC(ixCG_STATIC_SCREEN_PARAMETER)); -- dev_info(adev->dev, " CG_FREQ_TRAN_VOTING_0=0x%08X\n", -- RREG32_SMC(ixCG_FREQ_TRAN_VOTING_0)); -- dev_info(adev->dev, " CG_FREQ_TRAN_VOTING_1=0x%08X\n", -- RREG32_SMC(ixCG_FREQ_TRAN_VOTING_1)); -- dev_info(adev->dev, " CG_FREQ_TRAN_VOTING_2=0x%08X\n", -- RREG32_SMC(ixCG_FREQ_TRAN_VOTING_2)); -- dev_info(adev->dev, " CG_FREQ_TRAN_VOTING_3=0x%08X\n", -- RREG32_SMC(ixCG_FREQ_TRAN_VOTING_3)); -- dev_info(adev->dev, " CG_FREQ_TRAN_VOTING_4=0x%08X\n", -- RREG32_SMC(ixCG_FREQ_TRAN_VOTING_4)); -- dev_info(adev->dev, " CG_FREQ_TRAN_VOTING_5=0x%08X\n", -- RREG32_SMC(ixCG_FREQ_TRAN_VOTING_5)); -- dev_info(adev->dev, " CG_FREQ_TRAN_VOTING_6=0x%08X\n", -- RREG32_SMC(ixCG_FREQ_TRAN_VOTING_6)); -- dev_info(adev->dev, " CG_FREQ_TRAN_VOTING_7=0x%08X\n", -- RREG32_SMC(ixCG_FREQ_TRAN_VOTING_7)); -- dev_info(adev->dev, " RCU_UC_EVENTS=0x%08X\n", -- RREG32_SMC(ixRCU_UC_EVENTS)); -- dev_info(adev->dev, " DPM_TABLE_475=0x%08X\n", -- RREG32_SMC(ixDPM_TABLE_475)); -- dev_info(adev->dev, " MC_SEQ_RAS_TIMING_LP=0x%08X\n", -- RREG32(mmMC_SEQ_RAS_TIMING_LP)); -- dev_info(adev->dev, " MC_SEQ_RAS_TIMING=0x%08X\n", -- RREG32(mmMC_SEQ_RAS_TIMING)); -- dev_info(adev->dev, " MC_SEQ_CAS_TIMING_LP=0x%08X\n", -- RREG32(mmMC_SEQ_CAS_TIMING_LP)); -- dev_info(adev->dev, " MC_SEQ_CAS_TIMING=0x%08X\n", -- RREG32(mmMC_SEQ_CAS_TIMING)); -- dev_info(adev->dev, " MC_SEQ_DLL_STBY_LP=0x%08X\n", -- RREG32(mmMC_SEQ_DLL_STBY_LP)); -- dev_info(adev->dev, " MC_SEQ_DLL_STBY=0x%08X\n", -- RREG32(mmMC_SEQ_DLL_STBY)); -- dev_info(adev->dev, " MC_SEQ_G5PDX_CMD0_LP=0x%08X\n", -- RREG32(mmMC_SEQ_G5PDX_CMD0_LP)); -- dev_info(adev->dev, " MC_SEQ_G5PDX_CMD0=0x%08X\n", -- RREG32(mmMC_SEQ_G5PDX_CMD0)); -- dev_info(adev->dev, " MC_SEQ_G5PDX_CMD1_LP=0x%08X\n", -- RREG32(mmMC_SEQ_G5PDX_CMD1_LP)); -- dev_info(adev->dev, " MC_SEQ_G5PDX_CMD1=0x%08X\n", -- RREG32(mmMC_SEQ_G5PDX_CMD1)); -- dev_info(adev->dev, " MC_SEQ_G5PDX_CTRL_LP=0x%08X\n", -- RREG32(mmMC_SEQ_G5PDX_CTRL_LP)); -- dev_info(adev->dev, " MC_SEQ_G5PDX_CTRL=0x%08X\n", -- RREG32(mmMC_SEQ_G5PDX_CTRL)); -- dev_info(adev->dev, " MC_SEQ_PMG_DVS_CMD_LP=0x%08X\n", -- RREG32(mmMC_SEQ_PMG_DVS_CMD_LP)); -- dev_info(adev->dev, " MC_SEQ_PMG_DVS_CMD=0x%08X\n", -- RREG32(mmMC_SEQ_PMG_DVS_CMD)); -- dev_info(adev->dev, " MC_SEQ_PMG_DVS_CTL_LP=0x%08X\n", -- RREG32(mmMC_SEQ_PMG_DVS_CTL_LP)); -- dev_info(adev->dev, " MC_SEQ_PMG_DVS_CTL=0x%08X\n", -- RREG32(mmMC_SEQ_PMG_DVS_CTL)); -- dev_info(adev->dev, " MC_SEQ_MISC_TIMING_LP=0x%08X\n", -- RREG32(mmMC_SEQ_MISC_TIMING_LP)); -- dev_info(adev->dev, " MC_SEQ_MISC_TIMING=0x%08X\n", -- RREG32(mmMC_SEQ_MISC_TIMING)); -- dev_info(adev->dev, " MC_SEQ_MISC_TIMING2_LP=0x%08X\n", -- RREG32(mmMC_SEQ_MISC_TIMING2_LP)); -- dev_info(adev->dev, " MC_SEQ_MISC_TIMING2=0x%08X\n", -- RREG32(mmMC_SEQ_MISC_TIMING2)); -- dev_info(adev->dev, " MC_SEQ_PMG_CMD_EMRS_LP=0x%08X\n", -- RREG32(mmMC_SEQ_PMG_CMD_EMRS_LP)); -- dev_info(adev->dev, " MC_PMG_CMD_EMRS=0x%08X\n", -- RREG32(mmMC_PMG_CMD_EMRS)); -- dev_info(adev->dev, " MC_SEQ_PMG_CMD_MRS_LP=0x%08X\n", -- RREG32(mmMC_SEQ_PMG_CMD_MRS_LP)); -- dev_info(adev->dev, " MC_PMG_CMD_MRS=0x%08X\n", -- RREG32(mmMC_PMG_CMD_MRS)); -- dev_info(adev->dev, " MC_SEQ_PMG_CMD_MRS1_LP=0x%08X\n", -- RREG32(mmMC_SEQ_PMG_CMD_MRS1_LP)); -- dev_info(adev->dev, " MC_PMG_CMD_MRS1=0x%08X\n", -- RREG32(mmMC_PMG_CMD_MRS1)); -- dev_info(adev->dev, " MC_SEQ_WR_CTL_D0_LP=0x%08X\n", -- RREG32(mmMC_SEQ_WR_CTL_D0_LP)); -- dev_info(adev->dev, " MC_SEQ_WR_CTL_D0=0x%08X\n", -- RREG32(mmMC_SEQ_WR_CTL_D0)); -- dev_info(adev->dev, " MC_SEQ_WR_CTL_D1_LP=0x%08X\n", -- RREG32(mmMC_SEQ_WR_CTL_D1_LP)); -- dev_info(adev->dev, " MC_SEQ_WR_CTL_D1=0x%08X\n", -- RREG32(mmMC_SEQ_WR_CTL_D1)); -- dev_info(adev->dev, " MC_SEQ_RD_CTL_D0_LP=0x%08X\n", -- RREG32(mmMC_SEQ_RD_CTL_D0_LP)); -- dev_info(adev->dev, " MC_SEQ_RD_CTL_D0=0x%08X\n", -- RREG32(mmMC_SEQ_RD_CTL_D0)); -- dev_info(adev->dev, " MC_SEQ_RD_CTL_D1_LP=0x%08X\n", -- RREG32(mmMC_SEQ_RD_CTL_D1_LP)); -- dev_info(adev->dev, " MC_SEQ_RD_CTL_D1=0x%08X\n", -- RREG32(mmMC_SEQ_RD_CTL_D1)); -- dev_info(adev->dev, " MC_SEQ_PMG_TIMING_LP=0x%08X\n", -- RREG32(mmMC_SEQ_PMG_TIMING_LP)); -- dev_info(adev->dev, " MC_SEQ_PMG_TIMING=0x%08X\n", -- RREG32(mmMC_SEQ_PMG_TIMING)); -- dev_info(adev->dev, " MC_SEQ_PMG_CMD_MRS2_LP=0x%08X\n", -- RREG32(mmMC_SEQ_PMG_CMD_MRS2_LP)); -- dev_info(adev->dev, " MC_PMG_CMD_MRS2=0x%08X\n", -- RREG32(mmMC_PMG_CMD_MRS2)); -- dev_info(adev->dev, " MC_SEQ_WR_CTL_2_LP=0x%08X\n", -- RREG32(mmMC_SEQ_WR_CTL_2_LP)); -- dev_info(adev->dev, " MC_SEQ_WR_CTL_2=0x%08X\n", -- RREG32(mmMC_SEQ_WR_CTL_2)); -- dev_info(adev->dev, " PCIE_LC_SPEED_CNTL=0x%08X\n", -- RREG32_PCIE(ixPCIE_LC_SPEED_CNTL)); -- dev_info(adev->dev, " PCIE_LC_LINK_WIDTH_CNTL=0x%08X\n", -- RREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL)); -- dev_info(adev->dev, " SMC_IND_INDEX_0=0x%08X\n", -- RREG32(mmSMC_IND_INDEX_0)); -- dev_info(adev->dev, " SMC_IND_DATA_0=0x%08X\n", -- RREG32(mmSMC_IND_DATA_0)); -- dev_info(adev->dev, " SMC_IND_ACCESS_CNTL=0x%08X\n", -- RREG32(mmSMC_IND_ACCESS_CNTL)); -- dev_info(adev->dev, " SMC_RESP_0=0x%08X\n", -- RREG32(mmSMC_RESP_0)); -- dev_info(adev->dev, " SMC_MESSAGE_0=0x%08X\n", -- RREG32(mmSMC_MESSAGE_0)); -- dev_info(adev->dev, " SMC_SYSCON_RESET_CNTL=0x%08X\n", -- RREG32_SMC(ixSMC_SYSCON_RESET_CNTL)); -- dev_info(adev->dev, " SMC_SYSCON_CLOCK_CNTL_0=0x%08X\n", -- RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0)); -- dev_info(adev->dev, " SMC_SYSCON_MISC_CNTL=0x%08X\n", -- RREG32_SMC(ixSMC_SYSCON_MISC_CNTL)); -- dev_info(adev->dev, " SMC_PC_C=0x%08X\n", -- RREG32_SMC(ixSMC_PC_C)); --} -- - static int ci_dpm_soft_reset(void *handle) - { - return 0; -@@ -6625,7 +6416,6 @@ const struct amd_ip_funcs ci_dpm_ip_funcs = { - .is_idle = ci_dpm_is_idle, - .wait_for_idle = ci_dpm_wait_for_idle, - .soft_reset = ci_dpm_soft_reset, -- .print_status = ci_dpm_print_status, - .set_clockgating_state = ci_dpm_set_clockgating_state, - .set_powergating_state = ci_dpm_set_powergating_state, - }; -diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c -index 14a1411..e86afec 100644 ---- a/drivers/gpu/drm/amd/amdgpu/cik.c -+++ b/drivers/gpu/drm/amd/amdgpu/cik.c -@@ -2375,11 +2375,6 @@ static int cik_common_wait_for_idle(void *handle) - return 0; - } - --static void cik_common_print_status(void *handle) --{ -- --} -- - static int cik_common_soft_reset(void *handle) - { - /* XXX hard reset?? */ -@@ -2410,7 +2405,6 @@ const struct amd_ip_funcs cik_common_ip_funcs = { - .is_idle = cik_common_is_idle, - .wait_for_idle = cik_common_wait_for_idle, - .soft_reset = cik_common_soft_reset, -- .print_status = cik_common_print_status, - .set_clockgating_state = cik_common_set_clockgating_state, - .set_powergating_state = cik_common_set_powergating_state, - }; -diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.c b/drivers/gpu/drm/amd/amdgpu/cik_ih.c -index 30c9b3b..f2f14fe 100644 ---- a/drivers/gpu/drm/amd/amdgpu/cik_ih.c -+++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.c -@@ -372,35 +372,6 @@ static int cik_ih_wait_for_idle(void *handle) - return -ETIMEDOUT; - } - --static void cik_ih_print_status(void *handle) --{ -- struct amdgpu_device *adev = (struct amdgpu_device *)handle; -- -- dev_info(adev->dev, "CIK IH registers\n"); -- dev_info(adev->dev, " SRBM_STATUS=0x%08X\n", -- RREG32(mmSRBM_STATUS)); -- dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n", -- RREG32(mmSRBM_STATUS2)); -- dev_info(adev->dev, " INTERRUPT_CNTL=0x%08X\n", -- RREG32(mmINTERRUPT_CNTL)); -- dev_info(adev->dev, " INTERRUPT_CNTL2=0x%08X\n", -- RREG32(mmINTERRUPT_CNTL2)); -- dev_info(adev->dev, " IH_CNTL=0x%08X\n", -- RREG32(mmIH_CNTL)); -- dev_info(adev->dev, " IH_RB_CNTL=0x%08X\n", -- RREG32(mmIH_RB_CNTL)); -- dev_info(adev->dev, " IH_RB_BASE=0x%08X\n", -- RREG32(mmIH_RB_BASE)); -- dev_info(adev->dev, " IH_RB_WPTR_ADDR_LO=0x%08X\n", -- RREG32(mmIH_RB_WPTR_ADDR_LO)); -- dev_info(adev->dev, " IH_RB_WPTR_ADDR_HI=0x%08X\n", -- RREG32(mmIH_RB_WPTR_ADDR_HI)); -- dev_info(adev->dev, " IH_RB_RPTR=0x%08X\n", -- RREG32(mmIH_RB_RPTR)); -- dev_info(adev->dev, " IH_RB_WPTR=0x%08X\n", -- RREG32(mmIH_RB_WPTR)); --} -- - static int cik_ih_soft_reset(void *handle) - { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; -@@ -412,8 +383,6 @@ static int cik_ih_soft_reset(void *handle) - srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_IH_MASK; - - if (srbm_soft_reset) { -- cik_ih_print_status((void *)adev); -- - tmp = RREG32(mmSRBM_SOFT_RESET); - tmp |= srbm_soft_reset; - dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); -@@ -428,8 +397,6 @@ static int cik_ih_soft_reset(void *handle) - - /* Wait a little for things to settle down */ - udelay(50); -- -- cik_ih_print_status((void *)adev); - } - - return 0; -@@ -459,7 +426,6 @@ const struct amd_ip_funcs cik_ih_ip_funcs = { - .is_idle = cik_ih_is_idle, - .wait_for_idle = cik_ih_wait_for_idle, - .soft_reset = cik_ih_soft_reset, -- .print_status = cik_ih_print_status, - .set_clockgating_state = cik_ih_set_clockgating_state, - .set_powergating_state = cik_ih_set_powergating_state, - }; -diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c -index 7e28b1c..1ae79fc 100644 ---- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c -+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c -@@ -1064,57 +1064,6 @@ static int cik_sdma_wait_for_idle(void *handle) - return -ETIMEDOUT; - } - --static void cik_sdma_print_status(void *handle) --{ -- int i, j; -- struct amdgpu_device *adev = (struct amdgpu_device *)handle; -- -- dev_info(adev->dev, "CIK SDMA registers\n"); -- dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n", -- RREG32(mmSRBM_STATUS2)); -- for (i = 0; i < adev->sdma.num_instances; i++) { -- dev_info(adev->dev, " SDMA%d_STATUS_REG=0x%08X\n", -- i, RREG32(mmSDMA0_STATUS_REG + sdma_offsets[i])); -- dev_info(adev->dev, " SDMA%d_ME_CNTL=0x%08X\n", -- i, RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i])); -- dev_info(adev->dev, " SDMA%d_CNTL=0x%08X\n", -- i, RREG32(mmSDMA0_CNTL + sdma_offsets[i])); -- dev_info(adev->dev, " SDMA%d_SEM_INCOMPLETE_TIMER_CNTL=0x%08X\n", -- i, RREG32(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i])); -- dev_info(adev->dev, " SDMA%d_SEM_WAIT_FAIL_TIMER_CNTL=0x%08X\n", -- i, RREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i])); -- dev_info(adev->dev, " SDMA%d_GFX_IB_CNTL=0x%08X\n", -- i, RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i])); -- dev_info(adev->dev, " SDMA%d_GFX_RB_CNTL=0x%08X\n", -- i, RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i])); -- dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR=0x%08X\n", -- i, RREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i])); -- dev_info(adev->dev, " SDMA%d_GFX_RB_WPTR=0x%08X\n", -- i, RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i])); -- dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR_ADDR_HI=0x%08X\n", -- i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i])); -- dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR_ADDR_LO=0x%08X\n", -- i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i])); -- dev_info(adev->dev, " SDMA%d_GFX_RB_BASE=0x%08X\n", -- i, RREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i])); -- dev_info(adev->dev, " SDMA%d_GFX_RB_BASE_HI=0x%08X\n", -- i, RREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i])); -- dev_info(adev->dev, " SDMA%d_TILING_CONFIG=0x%08X\n", -- i, RREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i])); -- mutex_lock(&adev->srbm_mutex); -- for (j = 0; j < 16; j++) { -- cik_srbm_select(adev, 0, 0, 0, j); -- dev_info(adev->dev, " VM %d:\n", j); -- dev_info(adev->dev, " SDMA0_GFX_VIRTUAL_ADDR=0x%08X\n", -- RREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i])); -- dev_info(adev->dev, " SDMA0_GFX_APE1_CNTL=0x%08X\n", -- RREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i])); -- } -- cik_srbm_select(adev, 0, 0, 0, 0); -- mutex_unlock(&adev->srbm_mutex); -- } --} -- - static int cik_sdma_soft_reset(void *handle) - { - u32 srbm_soft_reset = 0; -@@ -1137,8 +1086,6 @@ static int cik_sdma_soft_reset(void *handle) - } - - if (srbm_soft_reset) { -- cik_sdma_print_status((void *)adev); -- - tmp = RREG32(mmSRBM_SOFT_RESET); - tmp |= srbm_soft_reset; - dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); -@@ -1153,8 +1100,6 @@ static int cik_sdma_soft_reset(void *handle) - - /* Wait a little for things to settle down */ - udelay(50); -- -- cik_sdma_print_status((void *)adev); - } - - return 0; -@@ -1289,7 +1234,6 @@ const struct amd_ip_funcs cik_sdma_ip_funcs = { - .is_idle = cik_sdma_is_idle, - .wait_for_idle = cik_sdma_wait_for_idle, - .soft_reset = cik_sdma_soft_reset, -- .print_status = cik_sdma_print_status, - .set_clockgating_state = cik_sdma_set_clockgating_state, - .set_powergating_state = cik_sdma_set_powergating_state, - }; -diff --git a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c -index e7ef226..bf1847b 100644 ---- a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c -+++ b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c -@@ -2241,7 +2241,6 @@ const struct amd_ip_funcs cz_dpm_ip_funcs = { - .is_idle = NULL, - .wait_for_idle = NULL, - .soft_reset = NULL, -- .print_status = NULL, - .set_clockgating_state = cz_dpm_set_clockgating_state, - .set_powergating_state = cz_dpm_set_powergating_state, - }; -diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.c b/drivers/gpu/drm/amd/amdgpu/cz_ih.c -index c79638f..23bd912 100644 ---- a/drivers/gpu/drm/amd/amdgpu/cz_ih.c -+++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.c -@@ -351,35 +351,6 @@ static int cz_ih_wait_for_idle(void *handle) - return -ETIMEDOUT; - } - --static void cz_ih_print_status(void *handle) --{ -- struct amdgpu_device *adev = (struct amdgpu_device *)handle; -- -- dev_info(adev->dev, "CZ IH registers\n"); -- dev_info(adev->dev, " SRBM_STATUS=0x%08X\n", -- RREG32(mmSRBM_STATUS)); -- dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n", -- RREG32(mmSRBM_STATUS2)); -- dev_info(adev->dev, " INTERRUPT_CNTL=0x%08X\n", -- RREG32(mmINTERRUPT_CNTL)); -- dev_info(adev->dev, " INTERRUPT_CNTL2=0x%08X\n", -- RREG32(mmINTERRUPT_CNTL2)); -- dev_info(adev->dev, " IH_CNTL=0x%08X\n", -- RREG32(mmIH_CNTL)); -- dev_info(adev->dev, " IH_RB_CNTL=0x%08X\n", -- RREG32(mmIH_RB_CNTL)); -- dev_info(adev->dev, " IH_RB_BASE=0x%08X\n", -- RREG32(mmIH_RB_BASE)); -- dev_info(adev->dev, " IH_RB_WPTR_ADDR_LO=0x%08X\n", -- RREG32(mmIH_RB_WPTR_ADDR_LO)); -- dev_info(adev->dev, " IH_RB_WPTR_ADDR_HI=0x%08X\n", -- RREG32(mmIH_RB_WPTR_ADDR_HI)); -- dev_info(adev->dev, " IH_RB_RPTR=0x%08X\n", -- RREG32(mmIH_RB_RPTR)); -- dev_info(adev->dev, " IH_RB_WPTR=0x%08X\n", -- RREG32(mmIH_RB_WPTR)); --} -- - static int cz_ih_soft_reset(void *handle) - { - u32 srbm_soft_reset = 0; -@@ -391,8 +362,6 @@ static int cz_ih_soft_reset(void *handle) - SOFT_RESET_IH, 1); - - if (srbm_soft_reset) { -- cz_ih_print_status((void *)adev); -- - tmp = RREG32(mmSRBM_SOFT_RESET); - tmp |= srbm_soft_reset; - dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); -@@ -407,8 +376,6 @@ static int cz_ih_soft_reset(void *handle) - - /* Wait a little for things to settle down */ - udelay(50); -- -- cz_ih_print_status((void *)adev); - } - - return 0; -@@ -440,7 +407,6 @@ const struct amd_ip_funcs cz_ih_ip_funcs = { - .is_idle = cz_ih_is_idle, - .wait_for_idle = cz_ih_wait_for_idle, - .soft_reset = cz_ih_soft_reset, -- .print_status = cz_ih_print_status, - .set_clockgating_state = cz_ih_set_clockgating_state, - .set_powergating_state = cz_ih_set_powergating_state, - }; -diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c -index 2445c01..609aa36 100644 ---- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c -+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c -@@ -3130,14 +3130,6 @@ static int dce_v10_0_wait_for_idle(void *handle) - return 0; - } - --static void dce_v10_0_print_status(void *handle) --{ -- struct amdgpu_device *adev = (struct amdgpu_device *)handle; -- -- dev_info(adev->dev, "DCE 10.x registers\n"); -- /* XXX todo */ --} -- - static int dce_v10_0_soft_reset(void *handle) - { - u32 srbm_soft_reset = 0, tmp; -@@ -3147,8 +3139,6 @@ static int dce_v10_0_soft_reset(void *handle) - srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK; - - if (srbm_soft_reset) { -- dce_v10_0_print_status((void *)adev); -- - tmp = RREG32(mmSRBM_SOFT_RESET); - tmp |= srbm_soft_reset; - dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); -@@ -3163,7 +3153,6 @@ static int dce_v10_0_soft_reset(void *handle) - - /* Wait a little for things to settle down */ - udelay(50); -- dce_v10_0_print_status((void *)adev); - } - return 0; - } -@@ -3512,7 +3501,6 @@ const struct amd_ip_funcs dce_v10_0_ip_funcs = { - .is_idle = dce_v10_0_is_idle, - .wait_for_idle = dce_v10_0_wait_for_idle, - .soft_reset = dce_v10_0_soft_reset, -- .print_status = dce_v10_0_print_status, - .set_clockgating_state = dce_v10_0_set_clockgating_state, - .set_powergating_state = dce_v10_0_set_powergating_state, - }; -diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c -index e47b252..22c6250 100644 ---- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c -+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c -@@ -3166,14 +3166,6 @@ static int dce_v11_0_wait_for_idle(void *handle) - return 0; - } - --static void dce_v11_0_print_status(void *handle) --{ -- struct amdgpu_device *adev = (struct amdgpu_device *)handle; -- -- dev_info(adev->dev, "DCE 10.x registers\n"); -- /* XXX todo */ --} -- - static int dce_v11_0_soft_reset(void *handle) - { - u32 srbm_soft_reset = 0, tmp; -@@ -3183,8 +3175,6 @@ static int dce_v11_0_soft_reset(void *handle) - srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK; - - if (srbm_soft_reset) { -- dce_v11_0_print_status((void *)adev); -- - tmp = RREG32(mmSRBM_SOFT_RESET); - tmp |= srbm_soft_reset; - dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); -@@ -3199,7 +3189,6 @@ static int dce_v11_0_soft_reset(void *handle) - - /* Wait a little for things to settle down */ - udelay(50); -- dce_v11_0_print_status((void *)adev); - } - return 0; - } -@@ -3548,7 +3537,6 @@ const struct amd_ip_funcs dce_v11_0_ip_funcs = { - .is_idle = dce_v11_0_is_idle, - .wait_for_idle = dce_v11_0_wait_for_idle, - .soft_reset = dce_v11_0_soft_reset, -- .print_status = dce_v11_0_print_status, - .set_clockgating_state = dce_v11_0_set_clockgating_state, - .set_powergating_state = dce_v11_0_set_powergating_state, - }; -diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c -index a42148f..2626c7e 100644 ---- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c -+++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c -@@ -3038,14 +3038,6 @@ static int dce_v8_0_wait_for_idle(void *handle) - return 0; - } - --static void dce_v8_0_print_status(void *handle) --{ -- struct amdgpu_device *adev = (struct amdgpu_device *)handle; -- -- dev_info(adev->dev, "DCE 8.x registers\n"); -- /* XXX todo */ --} -- - static int dce_v8_0_soft_reset(void *handle) - { - u32 srbm_soft_reset = 0, tmp; -@@ -3055,8 +3047,6 @@ static int dce_v8_0_soft_reset(void *handle) - srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK; - - if (srbm_soft_reset) { -- dce_v8_0_print_status((void *)adev); -- - tmp = RREG32(mmSRBM_SOFT_RESET); - tmp |= srbm_soft_reset; - dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); -@@ -3071,7 +3061,6 @@ static int dce_v8_0_soft_reset(void *handle) - - /* Wait a little for things to settle down */ - udelay(50); -- dce_v8_0_print_status((void *)adev); - } - return 0; - } -@@ -3442,7 +3431,6 @@ const struct amd_ip_funcs dce_v8_0_ip_funcs = { - .is_idle = dce_v8_0_is_idle, - .wait_for_idle = dce_v8_0_wait_for_idle, - .soft_reset = dce_v8_0_soft_reset, -- .print_status = dce_v8_0_print_status, - .set_clockgating_state = dce_v8_0_set_clockgating_state, - .set_powergating_state = dce_v8_0_set_powergating_state, - }; -diff --git a/drivers/gpu/drm/amd/amdgpu/fiji_dpm.c b/drivers/gpu/drm/amd/amdgpu/fiji_dpm.c -index 4b0e45a..6d13345 100644 ---- a/drivers/gpu/drm/amd/amdgpu/fiji_dpm.c -+++ b/drivers/gpu/drm/amd/amdgpu/fiji_dpm.c -@@ -154,7 +154,6 @@ const struct amd_ip_funcs fiji_dpm_ip_funcs = { - .is_idle = NULL, - .wait_for_idle = NULL, - .soft_reset = NULL, -- .print_status = NULL, - .set_clockgating_state = fiji_dpm_set_clockgating_state, - .set_powergating_state = fiji_dpm_set_powergating_state, - }; -diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c -index 19b07a8..f1842f9 100644 ---- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c -+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c -@@ -4572,256 +4572,6 @@ static int gfx_v7_0_wait_for_idle(void *handle) - return -ETIMEDOUT; - } - --static void gfx_v7_0_print_status(void *handle) --{ -- int i; -- struct amdgpu_device *adev = (struct amdgpu_device *)handle; -- -- dev_info(adev->dev, "GFX 7.x registers\n"); -- dev_info(adev->dev, " GRBM_STATUS=0x%08X\n", -- RREG32(mmGRBM_STATUS)); -- dev_info(adev->dev, " GRBM_STATUS2=0x%08X\n", -- RREG32(mmGRBM_STATUS2)); -- dev_info(adev->dev, " GRBM_STATUS_SE0=0x%08X\n", -- RREG32(mmGRBM_STATUS_SE0)); -- dev_info(adev->dev, " GRBM_STATUS_SE1=0x%08X\n", -- RREG32(mmGRBM_STATUS_SE1)); -- dev_info(adev->dev, " GRBM_STATUS_SE2=0x%08X\n", -- RREG32(mmGRBM_STATUS_SE2)); -- dev_info(adev->dev, " GRBM_STATUS_SE3=0x%08X\n", -- RREG32(mmGRBM_STATUS_SE3)); -- dev_info(adev->dev, " CP_STAT = 0x%08x\n", RREG32(mmCP_STAT)); -- dev_info(adev->dev, " CP_STALLED_STAT1 = 0x%08x\n", -- RREG32(mmCP_STALLED_STAT1)); -- dev_info(adev->dev, " CP_STALLED_STAT2 = 0x%08x\n", -- RREG32(mmCP_STALLED_STAT2)); -- dev_info(adev->dev, " CP_STALLED_STAT3 = 0x%08x\n", -- RREG32(mmCP_STALLED_STAT3)); -- dev_info(adev->dev, " CP_CPF_BUSY_STAT = 0x%08x\n", -- RREG32(mmCP_CPF_BUSY_STAT)); -- dev_info(adev->dev, " CP_CPF_STALLED_STAT1 = 0x%08x\n", -- RREG32(mmCP_CPF_STALLED_STAT1)); -- dev_info(adev->dev, " CP_CPF_STATUS = 0x%08x\n", RREG32(mmCP_CPF_STATUS)); -- dev_info(adev->dev, " CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(mmCP_CPC_BUSY_STAT)); -- dev_info(adev->dev, " CP_CPC_STALLED_STAT1 = 0x%08x\n", -- RREG32(mmCP_CPC_STALLED_STAT1)); -- dev_info(adev->dev, " CP_CPC_STATUS = 0x%08x\n", RREG32(mmCP_CPC_STATUS)); -- -- for (i = 0; i < 32; i++) { -- dev_info(adev->dev, " GB_TILE_MODE%d=0x%08X\n", -- i, RREG32(mmGB_TILE_MODE0 + (i * 4))); -- } -- for (i = 0; i < 16; i++) { -- dev_info(adev->dev, " GB_MACROTILE_MODE%d=0x%08X\n", -- i, RREG32(mmGB_MACROTILE_MODE0 + (i * 4))); -- } -- for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { -- dev_info(adev->dev, " se: %d\n", i); -- gfx_v7_0_select_se_sh(adev, i, 0xffffffff); -- dev_info(adev->dev, " PA_SC_RASTER_CONFIG=0x%08X\n", -- RREG32(mmPA_SC_RASTER_CONFIG)); -- dev_info(adev->dev, " PA_SC_RASTER_CONFIG_1=0x%08X\n", -- RREG32(mmPA_SC_RASTER_CONFIG_1)); -- } -- gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff); -- -- dev_info(adev->dev, " GB_ADDR_CONFIG=0x%08X\n", -- RREG32(mmGB_ADDR_CONFIG)); -- dev_info(adev->dev, " HDP_ADDR_CONFIG=0x%08X\n", -- RREG32(mmHDP_ADDR_CONFIG)); -- dev_info(adev->dev, " DMIF_ADDR_CALC=0x%08X\n", -- RREG32(mmDMIF_ADDR_CALC)); -- -- dev_info(adev->dev, " CP_MEQ_THRESHOLDS=0x%08X\n", -- RREG32(mmCP_MEQ_THRESHOLDS)); -- dev_info(adev->dev, " SX_DEBUG_1=0x%08X\n", -- RREG32(mmSX_DEBUG_1)); -- dev_info(adev->dev, " TA_CNTL_AUX=0x%08X\n", -- RREG32(mmTA_CNTL_AUX)); -- dev_info(adev->dev, " SPI_CONFIG_CNTL=0x%08X\n", -- RREG32(mmSPI_CONFIG_CNTL)); -- dev_info(adev->dev, " SQ_CONFIG=0x%08X\n", -- RREG32(mmSQ_CONFIG)); -- dev_info(adev->dev, " DB_DEBUG=0x%08X\n", -- RREG32(mmDB_DEBUG)); -- dev_info(adev->dev, " DB_DEBUG2=0x%08X\n", -- RREG32(mmDB_DEBUG2)); -- dev_info(adev->dev, " DB_DEBUG3=0x%08X\n", -- RREG32(mmDB_DEBUG3)); -- dev_info(adev->dev, " CB_HW_CONTROL=0x%08X\n", -- RREG32(mmCB_HW_CONTROL)); -- dev_info(adev->dev, " SPI_CONFIG_CNTL_1=0x%08X\n", -- RREG32(mmSPI_CONFIG_CNTL_1)); -- dev_info(adev->dev, " PA_SC_FIFO_SIZE=0x%08X\n", -- RREG32(mmPA_SC_FIFO_SIZE)); -- dev_info(adev->dev, " VGT_NUM_INSTANCES=0x%08X\n", -- RREG32(mmVGT_NUM_INSTANCES)); -- dev_info(adev->dev, " CP_PERFMON_CNTL=0x%08X\n", -- RREG32(mmCP_PERFMON_CNTL)); -- dev_info(adev->dev, " PA_SC_FORCE_EOV_MAX_CNTS=0x%08X\n", -- RREG32(mmPA_SC_FORCE_EOV_MAX_CNTS)); -- dev_info(adev->dev, " VGT_CACHE_INVALIDATION=0x%08X\n", -- RREG32(mmVGT_CACHE_INVALIDATION)); -- dev_info(adev->dev, " VGT_GS_VERTEX_REUSE=0x%08X\n", -- RREG32(mmVGT_GS_VERTEX_REUSE)); -- dev_info(adev->dev, " PA_SC_LINE_STIPPLE_STATE=0x%08X\n", -- RREG32(mmPA_SC_LINE_STIPPLE_STATE)); -- dev_info(adev->dev, " PA_CL_ENHANCE=0x%08X\n", -- RREG32(mmPA_CL_ENHANCE)); -- dev_info(adev->dev, " PA_SC_ENHANCE=0x%08X\n", -- RREG32(mmPA_SC_ENHANCE)); -- -- dev_info(adev->dev, " CP_ME_CNTL=0x%08X\n", -- RREG32(mmCP_ME_CNTL)); -- dev_info(adev->dev, " CP_MAX_CONTEXT=0x%08X\n", -- RREG32(mmCP_MAX_CONTEXT)); -- dev_info(adev->dev, " CP_ENDIAN_SWAP=0x%08X\n", -- RREG32(mmCP_ENDIAN_SWAP)); -- dev_info(adev->dev, " CP_DEVICE_ID=0x%08X\n", -- RREG32(mmCP_DEVICE_ID)); -- -- dev_info(adev->dev, " CP_SEM_WAIT_TIMER=0x%08X\n", -- RREG32(mmCP_SEM_WAIT_TIMER)); -- if (adev->asic_type != CHIP_HAWAII) -- dev_info(adev->dev, " CP_SEM_INCOMPLETE_TIMER_CNTL=0x%08X\n", -- RREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL)); -- -- dev_info(adev->dev, " CP_RB_WPTR_DELAY=0x%08X\n", -- RREG32(mmCP_RB_WPTR_DELAY)); -- dev_info(adev->dev, " CP_RB_VMID=0x%08X\n", -- RREG32(mmCP_RB_VMID)); -- dev_info(adev->dev, " CP_RB0_CNTL=0x%08X\n", -- RREG32(mmCP_RB0_CNTL)); -- dev_info(adev->dev, " CP_RB0_WPTR=0x%08X\n", -- RREG32(mmCP_RB0_WPTR)); -- dev_info(adev->dev, " CP_RB0_RPTR_ADDR=0x%08X\n", -- RREG32(mmCP_RB0_RPTR_ADDR)); -- dev_info(adev->dev, " CP_RB0_RPTR_ADDR_HI=0x%08X\n", -- RREG32(mmCP_RB0_RPTR_ADDR_HI)); -- dev_info(adev->dev, " CP_RB0_CNTL=0x%08X\n", -- RREG32(mmCP_RB0_CNTL)); -- dev_info(adev->dev, " CP_RB0_BASE=0x%08X\n", -- RREG32(mmCP_RB0_BASE)); -- dev_info(adev->dev, " CP_RB0_BASE_HI=0x%08X\n", -- RREG32(mmCP_RB0_BASE_HI)); -- dev_info(adev->dev, " CP_MEC_CNTL=0x%08X\n", -- RREG32(mmCP_MEC_CNTL)); -- dev_info(adev->dev, " CP_CPF_DEBUG=0x%08X\n", -- RREG32(mmCP_CPF_DEBUG)); -- -- dev_info(adev->dev, " SCRATCH_ADDR=0x%08X\n", -- RREG32(mmSCRATCH_ADDR)); -- dev_info(adev->dev, " SCRATCH_UMSK=0x%08X\n", -- RREG32(mmSCRATCH_UMSK)); -- -- /* init the pipes */ -- mutex_lock(&adev->srbm_mutex); -- for (i = 0; i < (adev->gfx.mec.num_pipe * adev->gfx.mec.num_mec); i++) { -- int me = (i < 4) ? 1 : 2; -- int pipe = (i < 4) ? i : (i - 4); -- int queue; -- -- dev_info(adev->dev, " me: %d, pipe: %d\n", me, pipe); -- cik_srbm_select(adev, me, pipe, 0, 0); -- dev_info(adev->dev, " CP_HPD_EOP_BASE_ADDR=0x%08X\n", -- RREG32(mmCP_HPD_EOP_BASE_ADDR)); -- dev_info(adev->dev, " CP_HPD_EOP_BASE_ADDR_HI=0x%08X\n", -- RREG32(mmCP_HPD_EOP_BASE_ADDR_HI)); -- dev_info(adev->dev, " CP_HPD_EOP_VMID=0x%08X\n", -- RREG32(mmCP_HPD_EOP_VMID)); -- dev_info(adev->dev, " CP_HPD_EOP_CONTROL=0x%08X\n", -- RREG32(mmCP_HPD_EOP_CONTROL)); -- -- for (queue = 0; queue < 8; queue++) { -- cik_srbm_select(adev, me, pipe, queue, 0); -- dev_info(adev->dev, " queue: %d\n", queue); -- dev_info(adev->dev, " CP_PQ_WPTR_POLL_CNTL=0x%08X\n", -- RREG32(mmCP_PQ_WPTR_POLL_CNTL)); -- dev_info(adev->dev, " CP_HQD_PQ_DOORBELL_CONTROL=0x%08X\n", -- RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL)); -- dev_info(adev->dev, " CP_HQD_ACTIVE=0x%08X\n", -- RREG32(mmCP_HQD_ACTIVE)); -- dev_info(adev->dev, " CP_HQD_DEQUEUE_REQUEST=0x%08X\n", -- RREG32(mmCP_HQD_DEQUEUE_REQUEST)); -- dev_info(adev->dev, " CP_HQD_PQ_RPTR=0x%08X\n", -- RREG32(mmCP_HQD_PQ_RPTR)); -- dev_info(adev->dev, " CP_HQD_PQ_WPTR=0x%08X\n", -- RREG32(mmCP_HQD_PQ_WPTR)); -- dev_info(adev->dev, " CP_HQD_PQ_BASE=0x%08X\n", -- RREG32(mmCP_HQD_PQ_BASE)); -- dev_info(adev->dev, " CP_HQD_PQ_BASE_HI=0x%08X\n", -- RREG32(mmCP_HQD_PQ_BASE_HI)); -- dev_info(adev->dev, " CP_HQD_PQ_CONTROL=0x%08X\n", -- RREG32(mmCP_HQD_PQ_CONTROL)); -- dev_info(adev->dev, " CP_HQD_PQ_WPTR_POLL_ADDR=0x%08X\n", -- RREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR)); -- dev_info(adev->dev, " CP_HQD_PQ_WPTR_POLL_ADDR_HI=0x%08X\n", -- RREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI)); -- dev_info(adev->dev, " CP_HQD_PQ_RPTR_REPORT_ADDR=0x%08X\n", -- RREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR)); -- dev_info(adev->dev, " CP_HQD_PQ_RPTR_REPORT_ADDR_HI=0x%08X\n", -- RREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI)); -- dev_info(adev->dev, " CP_HQD_PQ_DOORBELL_CONTROL=0x%08X\n", -- RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL)); -- dev_info(adev->dev, " CP_HQD_PQ_WPTR=0x%08X\n", -- RREG32(mmCP_HQD_PQ_WPTR)); -- dev_info(adev->dev, " CP_HQD_VMID=0x%08X\n", -- RREG32(mmCP_HQD_VMID)); -- dev_info(adev->dev, " CP_MQD_BASE_ADDR=0x%08X\n", -- RREG32(mmCP_MQD_BASE_ADDR)); -- dev_info(adev->dev, " CP_MQD_BASE_ADDR_HI=0x%08X\n", -- RREG32(mmCP_MQD_BASE_ADDR_HI)); -- dev_info(adev->dev, " CP_MQD_CONTROL=0x%08X\n", -- RREG32(mmCP_MQD_CONTROL)); -- } -- } -- cik_srbm_select(adev, 0, 0, 0, 0); -- mutex_unlock(&adev->srbm_mutex); -- -- dev_info(adev->dev, " CP_INT_CNTL_RING0=0x%08X\n", -- RREG32(mmCP_INT_CNTL_RING0)); -- dev_info(adev->dev, " RLC_LB_CNTL=0x%08X\n", -- RREG32(mmRLC_LB_CNTL)); -- dev_info(adev->dev, " RLC_CNTL=0x%08X\n", -- RREG32(mmRLC_CNTL)); -- dev_info(adev->dev, " RLC_CGCG_CGLS_CTRL=0x%08X\n", -- RREG32(mmRLC_CGCG_CGLS_CTRL)); -- dev_info(adev->dev, " RLC_LB_CNTR_INIT=0x%08X\n", -- RREG32(mmRLC_LB_CNTR_INIT)); -- dev_info(adev->dev, " RLC_LB_CNTR_MAX=0x%08X\n", -- RREG32(mmRLC_LB_CNTR_MAX)); -- dev_info(adev->dev, " RLC_LB_INIT_CU_MASK=0x%08X\n", -- RREG32(mmRLC_LB_INIT_CU_MASK)); -- dev_info(adev->dev, " RLC_LB_PARAMS=0x%08X\n", -- RREG32(mmRLC_LB_PARAMS)); -- dev_info(adev->dev, " RLC_LB_CNTL=0x%08X\n", -- RREG32(mmRLC_LB_CNTL)); -- dev_info(adev->dev, " RLC_MC_CNTL=0x%08X\n", -- RREG32(mmRLC_MC_CNTL)); -- dev_info(adev->dev, " RLC_UCODE_CNTL=0x%08X\n", -- RREG32(mmRLC_UCODE_CNTL)); -- -- if (adev->asic_type == CHIP_BONAIRE) -- dev_info(adev->dev, " RLC_DRIVER_CPDMA_STATUS=0x%08X\n", -- RREG32(mmRLC_DRIVER_CPDMA_STATUS)); -- -- mutex_lock(&adev->srbm_mutex); -- for (i = 0; i < 16; i++) { -- cik_srbm_select(adev, 0, 0, 0, i); -- dev_info(adev->dev, " VM %d:\n", i); -- dev_info(adev->dev, " SH_MEM_CONFIG=0x%08X\n", -- RREG32(mmSH_MEM_CONFIG)); -- dev_info(adev->dev, " SH_MEM_APE1_BASE=0x%08X\n", -- RREG32(mmSH_MEM_APE1_BASE)); -- dev_info(adev->dev, " SH_MEM_APE1_LIMIT=0x%08X\n", -- RREG32(mmSH_MEM_APE1_LIMIT)); -- dev_info(adev->dev, " SH_MEM_BASES=0x%08X\n", -- RREG32(mmSH_MEM_BASES)); -- } -- cik_srbm_select(adev, 0, 0, 0, 0); -- mutex_unlock(&adev->srbm_mutex); --} -- - static int gfx_v7_0_soft_reset(void *handle) - { - u32 grbm_soft_reset = 0, srbm_soft_reset = 0; -@@ -4855,7 +4605,6 @@ static int gfx_v7_0_soft_reset(void *handle) - srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK; - - if (grbm_soft_reset || srbm_soft_reset) { -- gfx_v7_0_print_status((void *)adev); - /* disable CG/PG */ - gfx_v7_0_fini_pg(adev); - gfx_v7_0_update_cg(adev, false); -@@ -4898,7 +4647,6 @@ static int gfx_v7_0_soft_reset(void *handle) - } - /* Wait a little for things to settle down */ - udelay(50); -- gfx_v7_0_print_status((void *)adev); - } - return 0; - } -@@ -5161,7 +4909,6 @@ const struct amd_ip_funcs gfx_v7_0_ip_funcs = { - .is_idle = gfx_v7_0_is_idle, - .wait_for_idle = gfx_v7_0_wait_for_idle, - .soft_reset = gfx_v7_0_soft_reset, -- .print_status = gfx_v7_0_print_status, - .set_clockgating_state = gfx_v7_0_set_clockgating_state, - .set_powergating_state = gfx_v7_0_set_powergating_state, - }; -diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c -index d0ec83f..dffa413 100644 ---- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c -+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c -@@ -4826,185 +4826,6 @@ static int gfx_v8_0_wait_for_idle(void *handle) - return -ETIMEDOUT; - } - --static void gfx_v8_0_print_status(void *handle) --{ -- int i; -- struct amdgpu_device *adev = (struct amdgpu_device *)handle; -- -- dev_info(adev->dev, "GFX 8.x registers\n"); -- dev_info(adev->dev, " GRBM_STATUS=0x%08X\n", -- RREG32(mmGRBM_STATUS)); -- dev_info(adev->dev, " GRBM_STATUS2=0x%08X\n", -- RREG32(mmGRBM_STATUS2)); -- dev_info(adev->dev, " GRBM_STATUS_SE0=0x%08X\n", -- RREG32(mmGRBM_STATUS_SE0)); -- dev_info(adev->dev, " GRBM_STATUS_SE1=0x%08X\n", -- RREG32(mmGRBM_STATUS_SE1)); -- dev_info(adev->dev, " GRBM_STATUS_SE2=0x%08X\n", -- RREG32(mmGRBM_STATUS_SE2)); -- dev_info(adev->dev, " GRBM_STATUS_SE3=0x%08X\n", -- RREG32(mmGRBM_STATUS_SE3)); -- dev_info(adev->dev, " CP_STAT = 0x%08x\n", RREG32(mmCP_STAT)); -- dev_info(adev->dev, " CP_STALLED_STAT1 = 0x%08x\n", -- RREG32(mmCP_STALLED_STAT1)); -- dev_info(adev->dev, " CP_STALLED_STAT2 = 0x%08x\n", -- RREG32(mmCP_STALLED_STAT2)); -- dev_info(adev->dev, " CP_STALLED_STAT3 = 0x%08x\n", -- RREG32(mmCP_STALLED_STAT3)); -- dev_info(adev->dev, " CP_CPF_BUSY_STAT = 0x%08x\n", -- RREG32(mmCP_CPF_BUSY_STAT)); -- dev_info(adev->dev, " CP_CPF_STALLED_STAT1 = 0x%08x\n", -- RREG32(mmCP_CPF_STALLED_STAT1)); -- dev_info(adev->dev, " CP_CPF_STATUS = 0x%08x\n", RREG32(mmCP_CPF_STATUS)); -- dev_info(adev->dev, " CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(mmCP_CPC_BUSY_STAT)); -- dev_info(adev->dev, " CP_CPC_STALLED_STAT1 = 0x%08x\n", -- RREG32(mmCP_CPC_STALLED_STAT1)); -- dev_info(adev->dev, " CP_CPC_STATUS = 0x%08x\n", RREG32(mmCP_CPC_STATUS)); -- -- for (i = 0; i < 32; i++) { -- dev_info(adev->dev, " GB_TILE_MODE%d=0x%08X\n", -- i, RREG32(mmGB_TILE_MODE0 + (i * 4))); -- } -- for (i = 0; i < 16; i++) { -- dev_info(adev->dev, " GB_MACROTILE_MODE%d=0x%08X\n", -- i, RREG32(mmGB_MACROTILE_MODE0 + (i * 4))); -- } -- for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { -- dev_info(adev->dev, " se: %d\n", i); -- gfx_v8_0_select_se_sh(adev, i, 0xffffffff); -- dev_info(adev->dev, " PA_SC_RASTER_CONFIG=0x%08X\n", -- RREG32(mmPA_SC_RASTER_CONFIG)); -- dev_info(adev->dev, " PA_SC_RASTER_CONFIG_1=0x%08X\n", -- RREG32(mmPA_SC_RASTER_CONFIG_1)); -- } -- gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff); -- -- dev_info(adev->dev, " GB_ADDR_CONFIG=0x%08X\n", -- RREG32(mmGB_ADDR_CONFIG)); -- dev_info(adev->dev, " HDP_ADDR_CONFIG=0x%08X\n", -- RREG32(mmHDP_ADDR_CONFIG)); -- dev_info(adev->dev, " DMIF_ADDR_CALC=0x%08X\n", -- RREG32(mmDMIF_ADDR_CALC)); -- -- dev_info(adev->dev, " CP_MEQ_THRESHOLDS=0x%08X\n", -- RREG32(mmCP_MEQ_THRESHOLDS)); -- dev_info(adev->dev, " SX_DEBUG_1=0x%08X\n", -- RREG32(mmSX_DEBUG_1)); -- dev_info(adev->dev, " TA_CNTL_AUX=0x%08X\n", -- RREG32(mmTA_CNTL_AUX)); -- dev_info(adev->dev, " SPI_CONFIG_CNTL=0x%08X\n", -- RREG32(mmSPI_CONFIG_CNTL)); -- dev_info(adev->dev, " SQ_CONFIG=0x%08X\n", -- RREG32(mmSQ_CONFIG)); -- dev_info(adev->dev, " DB_DEBUG=0x%08X\n", -- RREG32(mmDB_DEBUG)); -- dev_info(adev->dev, " DB_DEBUG2=0x%08X\n", -- RREG32(mmDB_DEBUG2)); -- dev_info(adev->dev, " DB_DEBUG3=0x%08X\n", -- RREG32(mmDB_DEBUG3)); -- dev_info(adev->dev, " CB_HW_CONTROL=0x%08X\n", -- RREG32(mmCB_HW_CONTROL)); -- dev_info(adev->dev, " SPI_CONFIG_CNTL_1=0x%08X\n", -- RREG32(mmSPI_CONFIG_CNTL_1)); -- dev_info(adev->dev, " PA_SC_FIFO_SIZE=0x%08X\n", -- RREG32(mmPA_SC_FIFO_SIZE)); -- dev_info(adev->dev, " VGT_NUM_INSTANCES=0x%08X\n", -- RREG32(mmVGT_NUM_INSTANCES)); -- dev_info(adev->dev, " CP_PERFMON_CNTL=0x%08X\n", -- RREG32(mmCP_PERFMON_CNTL)); -- dev_info(adev->dev, " PA_SC_FORCE_EOV_MAX_CNTS=0x%08X\n", -- RREG32(mmPA_SC_FORCE_EOV_MAX_CNTS)); -- dev_info(adev->dev, " VGT_CACHE_INVALIDATION=0x%08X\n", -- RREG32(mmVGT_CACHE_INVALIDATION)); -- dev_info(adev->dev, " VGT_GS_VERTEX_REUSE=0x%08X\n", -- RREG32(mmVGT_GS_VERTEX_REUSE)); -- dev_info(adev->dev, " PA_SC_LINE_STIPPLE_STATE=0x%08X\n", -- RREG32(mmPA_SC_LINE_STIPPLE_STATE)); -- dev_info(adev->dev, " PA_CL_ENHANCE=0x%08X\n", -- RREG32(mmPA_CL_ENHANCE)); -- dev_info(adev->dev, " PA_SC_ENHANCE=0x%08X\n", -- RREG32(mmPA_SC_ENHANCE)); -- -- dev_info(adev->dev, " CP_ME_CNTL=0x%08X\n", -- RREG32(mmCP_ME_CNTL)); -- dev_info(adev->dev, " CP_MAX_CONTEXT=0x%08X\n", -- RREG32(mmCP_MAX_CONTEXT)); -- dev_info(adev->dev, " CP_ENDIAN_SWAP=0x%08X\n", -- RREG32(mmCP_ENDIAN_SWAP)); -- dev_info(adev->dev, " CP_DEVICE_ID=0x%08X\n", -- RREG32(mmCP_DEVICE_ID)); -- -- dev_info(adev->dev, " CP_SEM_WAIT_TIMER=0x%08X\n", -- RREG32(mmCP_SEM_WAIT_TIMER)); -- -- dev_info(adev->dev, " CP_RB_WPTR_DELAY=0x%08X\n", -- RREG32(mmCP_RB_WPTR_DELAY)); -- dev_info(adev->dev, " CP_RB_VMID=0x%08X\n", -- RREG32(mmCP_RB_VMID)); -- dev_info(adev->dev, " CP_RB0_CNTL=0x%08X\n", -- RREG32(mmCP_RB0_CNTL)); -- dev_info(adev->dev, " CP_RB0_WPTR=0x%08X\n", -- RREG32(mmCP_RB0_WPTR)); -- dev_info(adev->dev, " CP_RB0_RPTR_ADDR=0x%08X\n", -- RREG32(mmCP_RB0_RPTR_ADDR)); -- dev_info(adev->dev, " CP_RB0_RPTR_ADDR_HI=0x%08X\n", -- RREG32(mmCP_RB0_RPTR_ADDR_HI)); -- dev_info(adev->dev, " CP_RB0_CNTL=0x%08X\n", -- RREG32(mmCP_RB0_CNTL)); -- dev_info(adev->dev, " CP_RB0_BASE=0x%08X\n", -- RREG32(mmCP_RB0_BASE)); -- dev_info(adev->dev, " CP_RB0_BASE_HI=0x%08X\n", -- RREG32(mmCP_RB0_BASE_HI)); -- dev_info(adev->dev, " CP_MEC_CNTL=0x%08X\n", -- RREG32(mmCP_MEC_CNTL)); -- dev_info(adev->dev, " CP_CPF_DEBUG=0x%08X\n", -- RREG32(mmCP_CPF_DEBUG)); -- -- dev_info(adev->dev, " SCRATCH_ADDR=0x%08X\n", -- RREG32(mmSCRATCH_ADDR)); -- dev_info(adev->dev, " SCRATCH_UMSK=0x%08X\n", -- RREG32(mmSCRATCH_UMSK)); -- -- dev_info(adev->dev, " CP_INT_CNTL_RING0=0x%08X\n", -- RREG32(mmCP_INT_CNTL_RING0)); -- dev_info(adev->dev, " RLC_LB_CNTL=0x%08X\n", -- RREG32(mmRLC_LB_CNTL)); -- dev_info(adev->dev, " RLC_CNTL=0x%08X\n", -- RREG32(mmRLC_CNTL)); -- dev_info(adev->dev, " RLC_CGCG_CGLS_CTRL=0x%08X\n", -- RREG32(mmRLC_CGCG_CGLS_CTRL)); -- dev_info(adev->dev, " RLC_LB_CNTR_INIT=0x%08X\n", -- RREG32(mmRLC_LB_CNTR_INIT)); -- dev_info(adev->dev, " RLC_LB_CNTR_MAX=0x%08X\n", -- RREG32(mmRLC_LB_CNTR_MAX)); -- dev_info(adev->dev, " RLC_LB_INIT_CU_MASK=0x%08X\n", -- RREG32(mmRLC_LB_INIT_CU_MASK)); -- dev_info(adev->dev, " RLC_LB_PARAMS=0x%08X\n", -- RREG32(mmRLC_LB_PARAMS)); -- dev_info(adev->dev, " RLC_LB_CNTL=0x%08X\n", -- RREG32(mmRLC_LB_CNTL)); -- dev_info(adev->dev, " RLC_MC_CNTL=0x%08X\n", -- RREG32(mmRLC_MC_CNTL)); -- dev_info(adev->dev, " RLC_UCODE_CNTL=0x%08X\n", -- RREG32(mmRLC_UCODE_CNTL)); -- -- mutex_lock(&adev->srbm_mutex); -- for (i = 0; i < 16; i++) { -- vi_srbm_select(adev, 0, 0, 0, i); -- dev_info(adev->dev, " VM %d:\n", i); -- dev_info(adev->dev, " SH_MEM_CONFIG=0x%08X\n", -- RREG32(mmSH_MEM_CONFIG)); -- dev_info(adev->dev, " SH_MEM_APE1_BASE=0x%08X\n", -- RREG32(mmSH_MEM_APE1_BASE)); -- dev_info(adev->dev, " SH_MEM_APE1_LIMIT=0x%08X\n", -- RREG32(mmSH_MEM_APE1_LIMIT)); -- dev_info(adev->dev, " SH_MEM_BASES=0x%08X\n", -- RREG32(mmSH_MEM_BASES)); -- } -- vi_srbm_select(adev, 0, 0, 0, 0); -- mutex_unlock(&adev->srbm_mutex); --} -- - static int gfx_v8_0_soft_reset(void *handle) - { - u32 grbm_soft_reset = 0, srbm_soft_reset = 0; -@@ -5045,7 +4866,6 @@ static int gfx_v8_0_soft_reset(void *handle) - SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1); - - if (grbm_soft_reset || srbm_soft_reset) { -- gfx_v8_0_print_status((void *)adev); - /* stop the rlc */ - gfx_v8_0_rlc_stop(adev); - -@@ -5105,7 +4925,6 @@ static int gfx_v8_0_soft_reset(void *handle) - - /* Wait a little for things to settle down */ - udelay(50); -- gfx_v8_0_print_status((void *)adev); - } - return 0; - } -@@ -6256,7 +6075,6 @@ const struct amd_ip_funcs gfx_v8_0_ip_funcs = { - .is_idle = gfx_v8_0_is_idle, - .wait_for_idle = gfx_v8_0_wait_for_idle, - .soft_reset = gfx_v8_0_soft_reset, -- .print_status = gfx_v8_0_print_status, - .set_clockgating_state = gfx_v8_0_set_clockgating_state, - .set_powergating_state = gfx_v8_0_set_powergating_state, - }; -diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c -index 09829f1..2037218 100644 ---- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c -+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c -@@ -1114,114 +1114,6 @@ static int gmc_v7_0_wait_for_idle(void *handle) - - } - --static void gmc_v7_0_print_status(void *handle) --{ -- int i, j; -- struct amdgpu_device *adev = (struct amdgpu_device *)handle; -- -- dev_info(adev->dev, "GMC 8.x registers\n"); -- dev_info(adev->dev, " SRBM_STATUS=0x%08X\n", -- RREG32(mmSRBM_STATUS)); -- dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n", -- RREG32(mmSRBM_STATUS2)); -- -- dev_info(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", -- RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR)); -- dev_info(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", -- RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS)); -- dev_info(adev->dev, " MC_VM_MX_L1_TLB_CNTL=0x%08X\n", -- RREG32(mmMC_VM_MX_L1_TLB_CNTL)); -- dev_info(adev->dev, " VM_L2_CNTL=0x%08X\n", -- RREG32(mmVM_L2_CNTL)); -- dev_info(adev->dev, " VM_L2_CNTL2=0x%08X\n", -- RREG32(mmVM_L2_CNTL2)); -- dev_info(adev->dev, " VM_L2_CNTL3=0x%08X\n", -- RREG32(mmVM_L2_CNTL3)); -- dev_info(adev->dev, " VM_CONTEXT0_PAGE_TABLE_START_ADDR=0x%08X\n", -- RREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR)); -- dev_info(adev->dev, " VM_CONTEXT0_PAGE_TABLE_END_ADDR=0x%08X\n", -- RREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR)); -- dev_info(adev->dev, " VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR=0x%08X\n", -- RREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR)); -- dev_info(adev->dev, " VM_CONTEXT0_CNTL2=0x%08X\n", -- RREG32(mmVM_CONTEXT0_CNTL2)); -- dev_info(adev->dev, " VM_CONTEXT0_CNTL=0x%08X\n", -- RREG32(mmVM_CONTEXT0_CNTL)); -- dev_info(adev->dev, " 0x15D4=0x%08X\n", -- RREG32(0x575)); -- dev_info(adev->dev, " 0x15D8=0x%08X\n", -- RREG32(0x576)); -- dev_info(adev->dev, " 0x15DC=0x%08X\n", -- RREG32(0x577)); -- dev_info(adev->dev, " VM_CONTEXT1_PAGE_TABLE_START_ADDR=0x%08X\n", -- RREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR)); -- dev_info(adev->dev, " VM_CONTEXT1_PAGE_TABLE_END_ADDR=0x%08X\n", -- RREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR)); -- dev_info(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR=0x%08X\n", -- RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR)); -- dev_info(adev->dev, " VM_CONTEXT1_CNTL2=0x%08X\n", -- RREG32(mmVM_CONTEXT1_CNTL2)); -- dev_info(adev->dev, " VM_CONTEXT1_CNTL=0x%08X\n", -- RREG32(mmVM_CONTEXT1_CNTL)); -- for (i = 0; i < 16; i++) { -- if (i < 8) -- dev_info(adev->dev, " VM_CONTEXT%d_PAGE_TABLE_BASE_ADDR=0x%08X\n", -- i, RREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i)); -- else -- dev_info(adev->dev, " VM_CONTEXT%d_PAGE_TABLE_BASE_ADDR=0x%08X\n", -- i, RREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8)); -- } -- dev_info(adev->dev, " MC_VM_SYSTEM_APERTURE_LOW_ADDR=0x%08X\n", -- RREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR)); -- dev_info(adev->dev, " MC_VM_SYSTEM_APERTURE_HIGH_ADDR=0x%08X\n", -- RREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR)); -- dev_info(adev->dev, " MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR=0x%08X\n", -- RREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR)); -- dev_info(adev->dev, " MC_VM_FB_LOCATION=0x%08X\n", -- RREG32(mmMC_VM_FB_LOCATION)); -- dev_info(adev->dev, " MC_VM_AGP_BASE=0x%08X\n", -- RREG32(mmMC_VM_AGP_BASE)); -- dev_info(adev->dev, " MC_VM_AGP_TOP=0x%08X\n", -- RREG32(mmMC_VM_AGP_TOP)); -- dev_info(adev->dev, " MC_VM_AGP_BOT=0x%08X\n", -- RREG32(mmMC_VM_AGP_BOT)); -- -- if (adev->asic_type == CHIP_KAVERI) { -- dev_info(adev->dev, " CHUB_CONTROL=0x%08X\n", -- RREG32(mmCHUB_CONTROL)); -- } -- -- dev_info(adev->dev, " HDP_REG_COHERENCY_FLUSH_CNTL=0x%08X\n", -- RREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL)); -- dev_info(adev->dev, " HDP_NONSURFACE_BASE=0x%08X\n", -- RREG32(mmHDP_NONSURFACE_BASE)); -- dev_info(adev->dev, " HDP_NONSURFACE_INFO=0x%08X\n", -- RREG32(mmHDP_NONSURFACE_INFO)); -- dev_info(adev->dev, " HDP_NONSURFACE_SIZE=0x%08X\n", -- RREG32(mmHDP_NONSURFACE_SIZE)); -- dev_info(adev->dev, " HDP_MISC_CNTL=0x%08X\n", -- RREG32(mmHDP_MISC_CNTL)); -- dev_info(adev->dev, " HDP_HOST_PATH_CNTL=0x%08X\n", -- RREG32(mmHDP_HOST_PATH_CNTL)); -- -- for (i = 0, j = 0; i < 32; i++, j += 0x6) { -- dev_info(adev->dev, " %d:\n", i); -- dev_info(adev->dev, " 0x%04X=0x%08X\n", -- 0xb05 + j, RREG32(0xb05 + j)); -- dev_info(adev->dev, " 0x%04X=0x%08X\n", -- 0xb06 + j, RREG32(0xb06 + j)); -- dev_info(adev->dev, " 0x%04X=0x%08X\n", -- 0xb07 + j, RREG32(0xb07 + j)); -- dev_info(adev->dev, " 0x%04X=0x%08X\n", -- 0xb08 + j, RREG32(0xb08 + j)); -- dev_info(adev->dev, " 0x%04X=0x%08X\n", -- 0xb09 + j, RREG32(0xb09 + j)); -- } -- -- dev_info(adev->dev, " BIF_FB_EN=0x%08X\n", -- RREG32(mmBIF_FB_EN)); --} -- - static int gmc_v7_0_soft_reset(void *handle) - { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; -@@ -1241,8 +1133,6 @@ static int gmc_v7_0_soft_reset(void *handle) - } - - if (srbm_soft_reset) { -- gmc_v7_0_print_status((void *)adev); -- - gmc_v7_0_mc_stop(adev, &save); - if (gmc_v7_0_wait_for_idle(adev)) { - dev_warn(adev->dev, "Wait for GMC idle timed out !\n"); -@@ -1266,8 +1156,6 @@ static int gmc_v7_0_soft_reset(void *handle) - - gmc_v7_0_mc_resume(adev, &save); - udelay(50); -- -- gmc_v7_0_print_status((void *)adev); - } - - return 0; -@@ -1381,7 +1269,6 @@ const struct amd_ip_funcs gmc_v7_0_ip_funcs = { - .is_idle = gmc_v7_0_is_idle, - .wait_for_idle = gmc_v7_0_wait_for_idle, - .soft_reset = gmc_v7_0_soft_reset, -- .print_status = gmc_v7_0_print_status, - .set_clockgating_state = gmc_v7_0_set_clockgating_state, - .set_powergating_state = gmc_v7_0_set_powergating_state, - }; -diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c -index f5efc67..aeb753e 100644 ---- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c -+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c -@@ -1117,111 +1117,6 @@ static int gmc_v8_0_wait_for_idle(void *handle) - - } - --static void gmc_v8_0_print_status(void *handle) --{ -- int i, j; -- struct amdgpu_device *adev = (struct amdgpu_device *)handle; -- -- dev_info(adev->dev, "GMC 8.x registers\n"); -- dev_info(adev->dev, " SRBM_STATUS=0x%08X\n", -- RREG32(mmSRBM_STATUS)); -- dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n", -- RREG32(mmSRBM_STATUS2)); -- -- dev_info(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", -- RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR)); -- dev_info(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", -- RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS)); -- dev_info(adev->dev, " MC_VM_MX_L1_TLB_CNTL=0x%08X\n", -- RREG32(mmMC_VM_MX_L1_TLB_CNTL)); -- dev_info(adev->dev, " VM_L2_CNTL=0x%08X\n", -- RREG32(mmVM_L2_CNTL)); -- dev_info(adev->dev, " VM_L2_CNTL2=0x%08X\n", -- RREG32(mmVM_L2_CNTL2)); -- dev_info(adev->dev, " VM_L2_CNTL3=0x%08X\n", -- RREG32(mmVM_L2_CNTL3)); -- dev_info(adev->dev, " VM_L2_CNTL4=0x%08X\n", -- RREG32(mmVM_L2_CNTL4)); -- dev_info(adev->dev, " VM_CONTEXT0_PAGE_TABLE_START_ADDR=0x%08X\n", -- RREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR)); -- dev_info(adev->dev, " VM_CONTEXT0_PAGE_TABLE_END_ADDR=0x%08X\n", -- RREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR)); -- dev_info(adev->dev, " VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR=0x%08X\n", -- RREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR)); -- dev_info(adev->dev, " VM_CONTEXT0_CNTL2=0x%08X\n", -- RREG32(mmVM_CONTEXT0_CNTL2)); -- dev_info(adev->dev, " VM_CONTEXT0_CNTL=0x%08X\n", -- RREG32(mmVM_CONTEXT0_CNTL)); -- dev_info(adev->dev, " VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR=0x%08X\n", -- RREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR)); -- dev_info(adev->dev, " VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR=0x%08X\n", -- RREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR)); -- dev_info(adev->dev, " mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET=0x%08X\n", -- RREG32(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET)); -- dev_info(adev->dev, " VM_CONTEXT1_PAGE_TABLE_START_ADDR=0x%08X\n", -- RREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR)); -- dev_info(adev->dev, " VM_CONTEXT1_PAGE_TABLE_END_ADDR=0x%08X\n", -- RREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR)); -- dev_info(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR=0x%08X\n", -- RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR)); -- dev_info(adev->dev, " VM_CONTEXT1_CNTL2=0x%08X\n", -- RREG32(mmVM_CONTEXT1_CNTL2)); -- dev_info(adev->dev, " VM_CONTEXT1_CNTL=0x%08X\n", -- RREG32(mmVM_CONTEXT1_CNTL)); -- for (i = 0; i < 16; i++) { -- if (i < 8) -- dev_info(adev->dev, " VM_CONTEXT%d_PAGE_TABLE_BASE_ADDR=0x%08X\n", -- i, RREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i)); -- else -- dev_info(adev->dev, " VM_CONTEXT%d_PAGE_TABLE_BASE_ADDR=0x%08X\n", -- i, RREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8)); -- } -- dev_info(adev->dev, " MC_VM_SYSTEM_APERTURE_LOW_ADDR=0x%08X\n", -- RREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR)); -- dev_info(adev->dev, " MC_VM_SYSTEM_APERTURE_HIGH_ADDR=0x%08X\n", -- RREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR)); -- dev_info(adev->dev, " MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR=0x%08X\n", -- RREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR)); -- dev_info(adev->dev, " MC_VM_FB_LOCATION=0x%08X\n", -- RREG32(mmMC_VM_FB_LOCATION)); -- dev_info(adev->dev, " MC_VM_AGP_BASE=0x%08X\n", -- RREG32(mmMC_VM_AGP_BASE)); -- dev_info(adev->dev, " MC_VM_AGP_TOP=0x%08X\n", -- RREG32(mmMC_VM_AGP_TOP)); -- dev_info(adev->dev, " MC_VM_AGP_BOT=0x%08X\n", -- RREG32(mmMC_VM_AGP_BOT)); -- -- dev_info(adev->dev, " HDP_REG_COHERENCY_FLUSH_CNTL=0x%08X\n", -- RREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL)); -- dev_info(adev->dev, " HDP_NONSURFACE_BASE=0x%08X\n", -- RREG32(mmHDP_NONSURFACE_BASE)); -- dev_info(adev->dev, " HDP_NONSURFACE_INFO=0x%08X\n", -- RREG32(mmHDP_NONSURFACE_INFO)); -- dev_info(adev->dev, " HDP_NONSURFACE_SIZE=0x%08X\n", -- RREG32(mmHDP_NONSURFACE_SIZE)); -- dev_info(adev->dev, " HDP_MISC_CNTL=0x%08X\n", -- RREG32(mmHDP_MISC_CNTL)); -- dev_info(adev->dev, " HDP_HOST_PATH_CNTL=0x%08X\n", -- RREG32(mmHDP_HOST_PATH_CNTL)); -- -- for (i = 0, j = 0; i < 32; i++, j += 0x6) { -- dev_info(adev->dev, " %d:\n", i); -- dev_info(adev->dev, " 0x%04X=0x%08X\n", -- 0xb05 + j, RREG32(0xb05 + j)); -- dev_info(adev->dev, " 0x%04X=0x%08X\n", -- 0xb06 + j, RREG32(0xb06 + j)); -- dev_info(adev->dev, " 0x%04X=0x%08X\n", -- 0xb07 + j, RREG32(0xb07 + j)); -- dev_info(adev->dev, " 0x%04X=0x%08X\n", -- 0xb08 + j, RREG32(0xb08 + j)); -- dev_info(adev->dev, " 0x%04X=0x%08X\n", -- 0xb09 + j, RREG32(0xb09 + j)); -- } -- -- dev_info(adev->dev, " BIF_FB_EN=0x%08X\n", -- RREG32(mmBIF_FB_EN)); --} -- - static int gmc_v8_0_soft_reset(void *handle) - { - struct amdgpu_mode_mc_save save; -@@ -1241,8 +1136,6 @@ static int gmc_v8_0_soft_reset(void *handle) - } - - if (srbm_soft_reset) { -- gmc_v8_0_print_status((void *)adev); -- - gmc_v8_0_mc_stop(adev, &save); - if (gmc_v8_0_wait_for_idle(adev)) { - dev_warn(adev->dev, "Wait for GMC idle timed out !\n"); -@@ -1266,8 +1159,6 @@ static int gmc_v8_0_soft_reset(void *handle) - - gmc_v8_0_mc_resume(adev, &save); - udelay(50); -- -- gmc_v8_0_print_status((void *)adev); - } - - return 0; -@@ -1540,7 +1431,6 @@ const struct amd_ip_funcs gmc_v8_0_ip_funcs = { - .is_idle = gmc_v8_0_is_idle, - .wait_for_idle = gmc_v8_0_wait_for_idle, - .soft_reset = gmc_v8_0_soft_reset, -- .print_status = gmc_v8_0_print_status, - .set_clockgating_state = gmc_v8_0_set_clockgating_state, - .set_powergating_state = gmc_v8_0_set_powergating_state, - }; -diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_dpm.c b/drivers/gpu/drm/amd/amdgpu/iceland_dpm.c -index 208d55f..57a9613 100644 ---- a/drivers/gpu/drm/amd/amdgpu/iceland_dpm.c -+++ b/drivers/gpu/drm/amd/amdgpu/iceland_dpm.c -@@ -168,7 +168,6 @@ const struct amd_ip_funcs iceland_dpm_ip_funcs = { - .is_idle = NULL, - .wait_for_idle = NULL, - .soft_reset = NULL, -- .print_status = NULL, - .set_clockgating_state = iceland_dpm_set_clockgating_state, - .set_powergating_state = iceland_dpm_set_powergating_state, - }; -diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c -index 679e739..5c4001e 100644 ---- a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c -+++ b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c -@@ -351,35 +351,6 @@ static int iceland_ih_wait_for_idle(void *handle) - return -ETIMEDOUT; - } - --static void iceland_ih_print_status(void *handle) --{ -- struct amdgpu_device *adev = (struct amdgpu_device *)handle; -- -- dev_info(adev->dev, "ICELAND IH registers\n"); -- dev_info(adev->dev, " SRBM_STATUS=0x%08X\n", -- RREG32(mmSRBM_STATUS)); -- dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n", -- RREG32(mmSRBM_STATUS2)); -- dev_info(adev->dev, " INTERRUPT_CNTL=0x%08X\n", -- RREG32(mmINTERRUPT_CNTL)); -- dev_info(adev->dev, " INTERRUPT_CNTL2=0x%08X\n", -- RREG32(mmINTERRUPT_CNTL2)); -- dev_info(adev->dev, " IH_CNTL=0x%08X\n", -- RREG32(mmIH_CNTL)); -- dev_info(adev->dev, " IH_RB_CNTL=0x%08X\n", -- RREG32(mmIH_RB_CNTL)); -- dev_info(adev->dev, " IH_RB_BASE=0x%08X\n", -- RREG32(mmIH_RB_BASE)); -- dev_info(adev->dev, " IH_RB_WPTR_ADDR_LO=0x%08X\n", -- RREG32(mmIH_RB_WPTR_ADDR_LO)); -- dev_info(adev->dev, " IH_RB_WPTR_ADDR_HI=0x%08X\n", -- RREG32(mmIH_RB_WPTR_ADDR_HI)); -- dev_info(adev->dev, " IH_RB_RPTR=0x%08X\n", -- RREG32(mmIH_RB_RPTR)); -- dev_info(adev->dev, " IH_RB_WPTR=0x%08X\n", -- RREG32(mmIH_RB_WPTR)); --} -- - static int iceland_ih_soft_reset(void *handle) - { - u32 srbm_soft_reset = 0; -@@ -391,8 +362,6 @@ static int iceland_ih_soft_reset(void *handle) - SOFT_RESET_IH, 1); - - if (srbm_soft_reset) { -- iceland_ih_print_status((void *)adev); -- - tmp = RREG32(mmSRBM_SOFT_RESET); - tmp |= srbm_soft_reset; - dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); -@@ -407,8 +376,6 @@ static int iceland_ih_soft_reset(void *handle) - - /* Wait a little for things to settle down */ - udelay(50); -- -- iceland_ih_print_status((void *)adev); - } - - return 0; -@@ -438,7 +405,6 @@ const struct amd_ip_funcs iceland_ih_ip_funcs = { - .is_idle = iceland_ih_is_idle, - .wait_for_idle = iceland_ih_wait_for_idle, - .soft_reset = iceland_ih_soft_reset, -- .print_status = iceland_ih_print_status, - .set_clockgating_state = iceland_ih_set_clockgating_state, - .set_powergating_state = iceland_ih_set_powergating_state, - }; -diff --git a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c -index 654d767..4bd1e55 100644 ---- a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c -+++ b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c -@@ -3147,62 +3147,6 @@ static int kv_dpm_wait_for_idle(void *handle) - return 0; - } - --static void kv_dpm_print_status(void *handle) --{ -- struct amdgpu_device *adev = (struct amdgpu_device *)handle; -- -- dev_info(adev->dev, "KV/KB DPM registers\n"); -- dev_info(adev->dev, " DIDT_SQ_CTRL0=0x%08X\n", -- RREG32_DIDT(ixDIDT_SQ_CTRL0)); -- dev_info(adev->dev, " DIDT_DB_CTRL0=0x%08X\n", -- RREG32_DIDT(ixDIDT_DB_CTRL0)); -- dev_info(adev->dev, " DIDT_TD_CTRL0=0x%08X\n", -- RREG32_DIDT(ixDIDT_TD_CTRL0)); -- dev_info(adev->dev, " DIDT_TCP_CTRL0=0x%08X\n", -- RREG32_DIDT(ixDIDT_TCP_CTRL0)); -- dev_info(adev->dev, " LCAC_SX0_OVR_SEL=0x%08X\n", -- RREG32_SMC(ixLCAC_SX0_OVR_SEL)); -- dev_info(adev->dev, " LCAC_SX0_OVR_VAL=0x%08X\n", -- RREG32_SMC(ixLCAC_SX0_OVR_VAL)); -- dev_info(adev->dev, " LCAC_MC0_OVR_SEL=0x%08X\n", -- RREG32_SMC(ixLCAC_MC0_OVR_SEL)); -- dev_info(adev->dev, " LCAC_MC0_OVR_VAL=0x%08X\n", -- RREG32_SMC(ixLCAC_MC0_OVR_VAL)); -- dev_info(adev->dev, " LCAC_MC1_OVR_SEL=0x%08X\n", -- RREG32_SMC(ixLCAC_MC1_OVR_SEL)); -- dev_info(adev->dev, " LCAC_MC1_OVR_VAL=0x%08X\n", -- RREG32_SMC(ixLCAC_MC1_OVR_VAL)); -- dev_info(adev->dev, " LCAC_MC2_OVR_SEL=0x%08X\n", -- RREG32_SMC(ixLCAC_MC2_OVR_SEL)); -- dev_info(adev->dev, " LCAC_MC2_OVR_VAL=0x%08X\n", -- RREG32_SMC(ixLCAC_MC2_OVR_VAL)); -- dev_info(adev->dev, " LCAC_MC3_OVR_SEL=0x%08X\n", -- RREG32_SMC(ixLCAC_MC3_OVR_SEL)); -- dev_info(adev->dev, " LCAC_MC3_OVR_VAL=0x%08X\n", -- RREG32_SMC(ixLCAC_MC3_OVR_VAL)); -- dev_info(adev->dev, " LCAC_CPL_OVR_SEL=0x%08X\n", -- RREG32_SMC(ixLCAC_CPL_OVR_SEL)); -- dev_info(adev->dev, " LCAC_CPL_OVR_VAL=0x%08X\n", -- RREG32_SMC(ixLCAC_CPL_OVR_VAL)); -- dev_info(adev->dev, " CG_FREQ_TRAN_VOTING_0=0x%08X\n", -- RREG32_SMC(ixCG_FREQ_TRAN_VOTING_0)); -- dev_info(adev->dev, " GENERAL_PWRMGT=0x%08X\n", -- RREG32_SMC(ixGENERAL_PWRMGT)); -- dev_info(adev->dev, " SCLK_PWRMGT_CNTL=0x%08X\n", -- RREG32_SMC(ixSCLK_PWRMGT_CNTL)); -- dev_info(adev->dev, " SMC_MESSAGE_0=0x%08X\n", -- RREG32(mmSMC_MESSAGE_0)); -- dev_info(adev->dev, " SMC_RESP_0=0x%08X\n", -- RREG32(mmSMC_RESP_0)); -- dev_info(adev->dev, " SMC_MSG_ARG_0=0x%08X\n", -- RREG32(mmSMC_MSG_ARG_0)); -- dev_info(adev->dev, " SMC_IND_INDEX_0=0x%08X\n", -- RREG32(mmSMC_IND_INDEX_0)); -- dev_info(adev->dev, " SMC_IND_DATA_0=0x%08X\n", -- RREG32(mmSMC_IND_DATA_0)); -- dev_info(adev->dev, " SMC_IND_ACCESS_CNTL=0x%08X\n", -- RREG32(mmSMC_IND_ACCESS_CNTL)); --} - - static int kv_dpm_soft_reset(void *handle) - { -@@ -3311,7 +3255,6 @@ const struct amd_ip_funcs kv_dpm_ip_funcs = { - .is_idle = kv_dpm_is_idle, - .wait_for_idle = kv_dpm_wait_for_idle, - .soft_reset = kv_dpm_soft_reset, -- .print_status = kv_dpm_print_status, - .set_clockgating_state = kv_dpm_set_clockgating_state, - .set_powergating_state = kv_dpm_set_powergating_state, - }; -diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c -index 9d8d3ef..037a425 100644 ---- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c -+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c -@@ -1080,55 +1080,6 @@ static int sdma_v2_4_wait_for_idle(void *handle) - return -ETIMEDOUT; - } - --static void sdma_v2_4_print_status(void *handle) --{ -- int i, j; -- struct amdgpu_device *adev = (struct amdgpu_device *)handle; -- -- dev_info(adev->dev, "VI SDMA registers\n"); -- dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n", -- RREG32(mmSRBM_STATUS2)); -- for (i = 0; i < adev->sdma.num_instances; i++) { -- dev_info(adev->dev, " SDMA%d_STATUS_REG=0x%08X\n", -- i, RREG32(mmSDMA0_STATUS_REG + sdma_offsets[i])); -- dev_info(adev->dev, " SDMA%d_F32_CNTL=0x%08X\n", -- i, RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i])); -- dev_info(adev->dev, " SDMA%d_CNTL=0x%08X\n", -- i, RREG32(mmSDMA0_CNTL + sdma_offsets[i])); -- dev_info(adev->dev, " SDMA%d_SEM_WAIT_FAIL_TIMER_CNTL=0x%08X\n", -- i, RREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i])); -- dev_info(adev->dev, " SDMA%d_GFX_IB_CNTL=0x%08X\n", -- i, RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i])); -- dev_info(adev->dev, " SDMA%d_GFX_RB_CNTL=0x%08X\n", -- i, RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i])); -- dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR=0x%08X\n", -- i, RREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i])); -- dev_info(adev->dev, " SDMA%d_GFX_RB_WPTR=0x%08X\n", -- i, RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i])); -- dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR_ADDR_HI=0x%08X\n", -- i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i])); -- dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR_ADDR_LO=0x%08X\n", -- i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i])); -- dev_info(adev->dev, " SDMA%d_GFX_RB_BASE=0x%08X\n", -- i, RREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i])); -- dev_info(adev->dev, " SDMA%d_GFX_RB_BASE_HI=0x%08X\n", -- i, RREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i])); -- dev_info(adev->dev, " SDMA%d_TILING_CONFIG=0x%08X\n", -- i, RREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i])); -- mutex_lock(&adev->srbm_mutex); -- for (j = 0; j < 16; j++) { -- vi_srbm_select(adev, 0, 0, 0, j); -- dev_info(adev->dev, " VM %d:\n", j); -- dev_info(adev->dev, " SDMA%d_GFX_VIRTUAL_ADDR=0x%08X\n", -- i, RREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i])); -- dev_info(adev->dev, " SDMA%d_GFX_APE1_CNTL=0x%08X\n", -- i, RREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i])); -- } -- vi_srbm_select(adev, 0, 0, 0, 0); -- mutex_unlock(&adev->srbm_mutex); -- } --} -- - static int sdma_v2_4_soft_reset(void *handle) - { - u32 srbm_soft_reset = 0; -@@ -1151,8 +1102,6 @@ static int sdma_v2_4_soft_reset(void *handle) - } - - if (srbm_soft_reset) { -- sdma_v2_4_print_status((void *)adev); -- - tmp = RREG32(mmSRBM_SOFT_RESET); - tmp |= srbm_soft_reset; - dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); -@@ -1167,8 +1116,6 @@ static int sdma_v2_4_soft_reset(void *handle) - - /* Wait a little for things to settle down */ - udelay(50); -- -- sdma_v2_4_print_status((void *)adev); - } - - return 0; -@@ -1294,7 +1241,6 @@ const struct amd_ip_funcs sdma_v2_4_ip_funcs = { - .is_idle = sdma_v2_4_is_idle, - .wait_for_idle = sdma_v2_4_wait_for_idle, - .soft_reset = sdma_v2_4_soft_reset, -- .print_status = sdma_v2_4_print_status, - .set_clockgating_state = sdma_v2_4_set_clockgating_state, - .set_powergating_state = sdma_v2_4_set_powergating_state, - }; -diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c -index 72cae36..c94c266 100644 ---- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c -+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c -@@ -1314,57 +1314,6 @@ static int sdma_v3_0_wait_for_idle(void *handle) - return -ETIMEDOUT; - } - --static void sdma_v3_0_print_status(void *handle) --{ -- int i, j; -- struct amdgpu_device *adev = (struct amdgpu_device *)handle; -- -- dev_info(adev->dev, "VI SDMA registers\n"); -- dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n", -- RREG32(mmSRBM_STATUS2)); -- for (i = 0; i < adev->sdma.num_instances; i++) { -- dev_info(adev->dev, " SDMA%d_STATUS_REG=0x%08X\n", -- i, RREG32(mmSDMA0_STATUS_REG + sdma_offsets[i])); -- dev_info(adev->dev, " SDMA%d_F32_CNTL=0x%08X\n", -- i, RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i])); -- dev_info(adev->dev, " SDMA%d_CNTL=0x%08X\n", -- i, RREG32(mmSDMA0_CNTL + sdma_offsets[i])); -- dev_info(adev->dev, " SDMA%d_SEM_WAIT_FAIL_TIMER_CNTL=0x%08X\n", -- i, RREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i])); -- dev_info(adev->dev, " SDMA%d_GFX_IB_CNTL=0x%08X\n", -- i, RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i])); -- dev_info(adev->dev, " SDMA%d_GFX_RB_CNTL=0x%08X\n", -- i, RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i])); -- dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR=0x%08X\n", -- i, RREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i])); -- dev_info(adev->dev, " SDMA%d_GFX_RB_WPTR=0x%08X\n", -- i, RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i])); -- dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR_ADDR_HI=0x%08X\n", -- i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i])); -- dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR_ADDR_LO=0x%08X\n", -- i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i])); -- dev_info(adev->dev, " SDMA%d_GFX_RB_BASE=0x%08X\n", -- i, RREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i])); -- dev_info(adev->dev, " SDMA%d_GFX_RB_BASE_HI=0x%08X\n", -- i, RREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i])); -- dev_info(adev->dev, " SDMA%d_GFX_DOORBELL=0x%08X\n", -- i, RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i])); -- dev_info(adev->dev, " SDMA%d_TILING_CONFIG=0x%08X\n", -- i, RREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i])); -- mutex_lock(&adev->srbm_mutex); -- for (j = 0; j < 16; j++) { -- vi_srbm_select(adev, 0, 0, 0, j); -- dev_info(adev->dev, " VM %d:\n", j); -- dev_info(adev->dev, " SDMA%d_GFX_VIRTUAL_ADDR=0x%08X\n", -- i, RREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i])); -- dev_info(adev->dev, " SDMA%d_GFX_APE1_CNTL=0x%08X\n", -- i, RREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i])); -- } -- vi_srbm_select(adev, 0, 0, 0, 0); -- mutex_unlock(&adev->srbm_mutex); -- } --} -- - static int sdma_v3_0_soft_reset(void *handle) - { - u32 srbm_soft_reset = 0; -@@ -1387,8 +1336,6 @@ static int sdma_v3_0_soft_reset(void *handle) - } - - if (srbm_soft_reset) { -- sdma_v3_0_print_status((void *)adev); -- - tmp = RREG32(mmSRBM_SOFT_RESET); - tmp |= srbm_soft_reset; - dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); -@@ -1403,8 +1350,6 @@ static int sdma_v3_0_soft_reset(void *handle) - - /* Wait a little for things to settle down */ - udelay(50); -- -- sdma_v3_0_print_status((void *)adev); - } - - return 0; -@@ -1608,7 +1553,6 @@ const struct amd_ip_funcs sdma_v3_0_ip_funcs = { - .is_idle = sdma_v3_0_is_idle, - .wait_for_idle = sdma_v3_0_wait_for_idle, - .soft_reset = sdma_v3_0_soft_reset, -- .print_status = sdma_v3_0_print_status, - .set_clockgating_state = sdma_v3_0_set_clockgating_state, - .set_powergating_state = sdma_v3_0_set_powergating_state, - }; -diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_dpm.c b/drivers/gpu/drm/amd/amdgpu/tonga_dpm.c -index 0497784..552f0f4 100644 ---- a/drivers/gpu/drm/amd/amdgpu/tonga_dpm.c -+++ b/drivers/gpu/drm/amd/amdgpu/tonga_dpm.c -@@ -154,7 +154,6 @@ const struct amd_ip_funcs tonga_dpm_ip_funcs = { - .is_idle = NULL, - .wait_for_idle = NULL, - .soft_reset = NULL, -- .print_status = NULL, - .set_clockgating_state = tonga_dpm_set_clockgating_state, - .set_powergating_state = tonga_dpm_set_powergating_state, - }; -diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c -index 0f14199..55cdab8 100644 ---- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c -+++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c -@@ -374,35 +374,6 @@ static int tonga_ih_wait_for_idle(void *handle) - return -ETIMEDOUT; - } - --static void tonga_ih_print_status(void *handle) --{ -- struct amdgpu_device *adev = (struct amdgpu_device *)handle; -- -- dev_info(adev->dev, "TONGA IH registers\n"); -- dev_info(adev->dev, " SRBM_STATUS=0x%08X\n", -- RREG32(mmSRBM_STATUS)); -- dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n", -- RREG32(mmSRBM_STATUS2)); -- dev_info(adev->dev, " INTERRUPT_CNTL=0x%08X\n", -- RREG32(mmINTERRUPT_CNTL)); -- dev_info(adev->dev, " INTERRUPT_CNTL2=0x%08X\n", -- RREG32(mmINTERRUPT_CNTL2)); -- dev_info(adev->dev, " IH_CNTL=0x%08X\n", -- RREG32(mmIH_CNTL)); -- dev_info(adev->dev, " IH_RB_CNTL=0x%08X\n", -- RREG32(mmIH_RB_CNTL)); -- dev_info(adev->dev, " IH_RB_BASE=0x%08X\n", -- RREG32(mmIH_RB_BASE)); -- dev_info(adev->dev, " IH_RB_WPTR_ADDR_LO=0x%08X\n", -- RREG32(mmIH_RB_WPTR_ADDR_LO)); -- dev_info(adev->dev, " IH_RB_WPTR_ADDR_HI=0x%08X\n", -- RREG32(mmIH_RB_WPTR_ADDR_HI)); -- dev_info(adev->dev, " IH_RB_RPTR=0x%08X\n", -- RREG32(mmIH_RB_RPTR)); -- dev_info(adev->dev, " IH_RB_WPTR=0x%08X\n", -- RREG32(mmIH_RB_WPTR)); --} -- - static int tonga_ih_soft_reset(void *handle) - { - u32 srbm_soft_reset = 0; -@@ -414,8 +385,6 @@ static int tonga_ih_soft_reset(void *handle) - SOFT_RESET_IH, 1); - - if (srbm_soft_reset) { -- tonga_ih_print_status(adev); -- - tmp = RREG32(mmSRBM_SOFT_RESET); - tmp |= srbm_soft_reset; - dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); -@@ -430,8 +399,6 @@ static int tonga_ih_soft_reset(void *handle) - - /* Wait a little for things to settle down */ - udelay(50); -- -- tonga_ih_print_status(adev); - } - - return 0; -@@ -461,7 +428,6 @@ const struct amd_ip_funcs tonga_ih_ip_funcs = { - .is_idle = tonga_ih_is_idle, - .wait_for_idle = tonga_ih_wait_for_idle, - .soft_reset = tonga_ih_soft_reset, -- .print_status = tonga_ih_print_status, - .set_clockgating_state = tonga_ih_set_clockgating_state, - .set_powergating_state = tonga_ih_set_powergating_state, - }; -diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c -index c257cfa..abd37a7 100644 ---- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c -+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c -@@ -680,117 +680,6 @@ static int uvd_v4_2_soft_reset(void *handle) - return uvd_v4_2_start(adev); - } - --static void uvd_v4_2_print_status(void *handle) --{ -- struct amdgpu_device *adev = (struct amdgpu_device *)handle; -- dev_info(adev->dev, "UVD 4.2 registers\n"); -- dev_info(adev->dev, " UVD_SEMA_ADDR_LOW=0x%08X\n", -- RREG32(mmUVD_SEMA_ADDR_LOW)); -- dev_info(adev->dev, " UVD_SEMA_ADDR_HIGH=0x%08X\n", -- RREG32(mmUVD_SEMA_ADDR_HIGH)); -- dev_info(adev->dev, " UVD_SEMA_CMD=0x%08X\n", -- RREG32(mmUVD_SEMA_CMD)); -- dev_info(adev->dev, " UVD_GPCOM_VCPU_CMD=0x%08X\n", -- RREG32(mmUVD_GPCOM_VCPU_CMD)); -- dev_info(adev->dev, " UVD_GPCOM_VCPU_DATA0=0x%08X\n", -- RREG32(mmUVD_GPCOM_VCPU_DATA0)); -- dev_info(adev->dev, " UVD_GPCOM_VCPU_DATA1=0x%08X\n", -- RREG32(mmUVD_GPCOM_VCPU_DATA1)); -- dev_info(adev->dev, " UVD_ENGINE_CNTL=0x%08X\n", -- RREG32(mmUVD_ENGINE_CNTL)); -- dev_info(adev->dev, " UVD_UDEC_ADDR_CONFIG=0x%08X\n", -- RREG32(mmUVD_UDEC_ADDR_CONFIG)); -- dev_info(adev->dev, " UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n", -- RREG32(mmUVD_UDEC_DB_ADDR_CONFIG)); -- dev_info(adev->dev, " UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n", -- RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG)); -- dev_info(adev->dev, " UVD_SEMA_CNTL=0x%08X\n", -- RREG32(mmUVD_SEMA_CNTL)); -- dev_info(adev->dev, " UVD_LMI_EXT40_ADDR=0x%08X\n", -- RREG32(mmUVD_LMI_EXT40_ADDR)); -- dev_info(adev->dev, " UVD_CTX_INDEX=0x%08X\n", -- RREG32(mmUVD_CTX_INDEX)); -- dev_info(adev->dev, " UVD_CTX_DATA=0x%08X\n", -- RREG32(mmUVD_CTX_DATA)); -- dev_info(adev->dev, " UVD_CGC_GATE=0x%08X\n", -- RREG32(mmUVD_CGC_GATE)); -- dev_info(adev->dev, " UVD_CGC_CTRL=0x%08X\n", -- RREG32(mmUVD_CGC_CTRL)); -- dev_info(adev->dev, " UVD_LMI_CTRL2=0x%08X\n", -- RREG32(mmUVD_LMI_CTRL2)); -- dev_info(adev->dev, " UVD_MASTINT_EN=0x%08X\n", -- RREG32(mmUVD_MASTINT_EN)); -- dev_info(adev->dev, " UVD_LMI_ADDR_EXT=0x%08X\n", -- RREG32(mmUVD_LMI_ADDR_EXT)); -- dev_info(adev->dev, " UVD_LMI_CTRL=0x%08X\n", -- RREG32(mmUVD_LMI_CTRL)); -- dev_info(adev->dev, " UVD_LMI_SWAP_CNTL=0x%08X\n", -- RREG32(mmUVD_LMI_SWAP_CNTL)); -- dev_info(adev->dev, " UVD_MP_SWAP_CNTL=0x%08X\n", -- RREG32(mmUVD_MP_SWAP_CNTL)); -- dev_info(adev->dev, " UVD_MPC_SET_MUXA0=0x%08X\n", -- RREG32(mmUVD_MPC_SET_MUXA0)); -- dev_info(adev->dev, " UVD_MPC_SET_MUXA1=0x%08X\n", -- RREG32(mmUVD_MPC_SET_MUXA1)); -- dev_info(adev->dev, " UVD_MPC_SET_MUXB0=0x%08X\n", -- RREG32(mmUVD_MPC_SET_MUXB0)); -- dev_info(adev->dev, " UVD_MPC_SET_MUXB1=0x%08X\n", -- RREG32(mmUVD_MPC_SET_MUXB1)); -- dev_info(adev->dev, " UVD_MPC_SET_MUX=0x%08X\n", -- RREG32(mmUVD_MPC_SET_MUX)); -- dev_info(adev->dev, " UVD_MPC_SET_ALU=0x%08X\n", -- RREG32(mmUVD_MPC_SET_ALU)); -- dev_info(adev->dev, " UVD_VCPU_CACHE_OFFSET0=0x%08X\n", -- RREG32(mmUVD_VCPU_CACHE_OFFSET0)); -- dev_info(adev->dev, " UVD_VCPU_CACHE_SIZE0=0x%08X\n", -- RREG32(mmUVD_VCPU_CACHE_SIZE0)); -- dev_info(adev->dev, " UVD_VCPU_CACHE_OFFSET1=0x%08X\n", -- RREG32(mmUVD_VCPU_CACHE_OFFSET1)); -- dev_info(adev->dev, " UVD_VCPU_CACHE_SIZE1=0x%08X\n", -- RREG32(mmUVD_VCPU_CACHE_SIZE1)); -- dev_info(adev->dev, " UVD_VCPU_CACHE_OFFSET2=0x%08X\n", -- RREG32(mmUVD_VCPU_CACHE_OFFSET2)); -- dev_info(adev->dev, " UVD_VCPU_CACHE_SIZE2=0x%08X\n", -- RREG32(mmUVD_VCPU_CACHE_SIZE2)); -- dev_info(adev->dev, " UVD_VCPU_CNTL=0x%08X\n", -- RREG32(mmUVD_VCPU_CNTL)); -- dev_info(adev->dev, " UVD_SOFT_RESET=0x%08X\n", -- RREG32(mmUVD_SOFT_RESET)); -- dev_info(adev->dev, " UVD_RBC_IB_BASE=0x%08X\n", -- RREG32(mmUVD_RBC_IB_BASE)); -- dev_info(adev->dev, " UVD_RBC_IB_SIZE=0x%08X\n", -- RREG32(mmUVD_RBC_IB_SIZE)); -- dev_info(adev->dev, " UVD_RBC_RB_BASE=0x%08X\n", -- RREG32(mmUVD_RBC_RB_BASE)); -- dev_info(adev->dev, " UVD_RBC_RB_RPTR=0x%08X\n", -- RREG32(mmUVD_RBC_RB_RPTR)); -- dev_info(adev->dev, " UVD_RBC_RB_WPTR=0x%08X\n", -- RREG32(mmUVD_RBC_RB_WPTR)); -- dev_info(adev->dev, " UVD_RBC_RB_WPTR_CNTL=0x%08X\n", -- RREG32(mmUVD_RBC_RB_WPTR_CNTL)); -- dev_info(adev->dev, " UVD_RBC_RB_CNTL=0x%08X\n", -- RREG32(mmUVD_RBC_RB_CNTL)); -- dev_info(adev->dev, " UVD_STATUS=0x%08X\n", -- RREG32(mmUVD_STATUS)); -- dev_info(adev->dev, " UVD_SEMA_TIMEOUT_STATUS=0x%08X\n", -- RREG32(mmUVD_SEMA_TIMEOUT_STATUS)); -- dev_info(adev->dev, " UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL=0x%08X\n", -- RREG32(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL)); -- dev_info(adev->dev, " UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL=0x%08X\n", -- RREG32(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL)); -- dev_info(adev->dev, " UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL=0x%08X\n", -- RREG32(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL)); -- dev_info(adev->dev, " UVD_CONTEXT_ID=0x%08X\n", -- RREG32(mmUVD_CONTEXT_ID)); -- dev_info(adev->dev, " UVD_UDEC_ADDR_CONFIG=0x%08X\n", -- RREG32(mmUVD_UDEC_ADDR_CONFIG)); -- dev_info(adev->dev, " UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n", -- RREG32(mmUVD_UDEC_DB_ADDR_CONFIG)); -- dev_info(adev->dev, " UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n", -- RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG)); -- --} -- - static int uvd_v4_2_set_interrupt_state(struct amdgpu_device *adev, - struct amdgpu_irq_src *source, - unsigned type, -@@ -861,7 +750,6 @@ const struct amd_ip_funcs uvd_v4_2_ip_funcs = { - .is_idle = uvd_v4_2_is_idle, - .wait_for_idle = uvd_v4_2_wait_for_idle, - .soft_reset = uvd_v4_2_soft_reset, -- .print_status = uvd_v4_2_print_status, - .set_clockgating_state = uvd_v4_2_set_clockgating_state, - .set_powergating_state = uvd_v4_2_set_powergating_state, - }; -diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c -index 5f0d4f7..1c1a0e2 100644 ---- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c -+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c -@@ -624,120 +624,6 @@ static int uvd_v5_0_soft_reset(void *handle) - return uvd_v5_0_start(adev); - } - --static void uvd_v5_0_print_status(void *handle) --{ -- struct amdgpu_device *adev = (struct amdgpu_device *)handle; -- dev_info(adev->dev, "UVD 5.0 registers\n"); -- dev_info(adev->dev, " UVD_SEMA_ADDR_LOW=0x%08X\n", -- RREG32(mmUVD_SEMA_ADDR_LOW)); -- dev_info(adev->dev, " UVD_SEMA_ADDR_HIGH=0x%08X\n", -- RREG32(mmUVD_SEMA_ADDR_HIGH)); -- dev_info(adev->dev, " UVD_SEMA_CMD=0x%08X\n", -- RREG32(mmUVD_SEMA_CMD)); -- dev_info(adev->dev, " UVD_GPCOM_VCPU_CMD=0x%08X\n", -- RREG32(mmUVD_GPCOM_VCPU_CMD)); -- dev_info(adev->dev, " UVD_GPCOM_VCPU_DATA0=0x%08X\n", -- RREG32(mmUVD_GPCOM_VCPU_DATA0)); -- dev_info(adev->dev, " UVD_GPCOM_VCPU_DATA1=0x%08X\n", -- RREG32(mmUVD_GPCOM_VCPU_DATA1)); -- dev_info(adev->dev, " UVD_ENGINE_CNTL=0x%08X\n", -- RREG32(mmUVD_ENGINE_CNTL)); -- dev_info(adev->dev, " UVD_UDEC_ADDR_CONFIG=0x%08X\n", -- RREG32(mmUVD_UDEC_ADDR_CONFIG)); -- dev_info(adev->dev, " UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n", -- RREG32(mmUVD_UDEC_DB_ADDR_CONFIG)); -- dev_info(adev->dev, " UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n", -- RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG)); -- dev_info(adev->dev, " UVD_SEMA_CNTL=0x%08X\n", -- RREG32(mmUVD_SEMA_CNTL)); -- dev_info(adev->dev, " UVD_LMI_EXT40_ADDR=0x%08X\n", -- RREG32(mmUVD_LMI_EXT40_ADDR)); -- dev_info(adev->dev, " UVD_CTX_INDEX=0x%08X\n", -- RREG32(mmUVD_CTX_INDEX)); -- dev_info(adev->dev, " UVD_CTX_DATA=0x%08X\n", -- RREG32(mmUVD_CTX_DATA)); -- dev_info(adev->dev, " UVD_CGC_GATE=0x%08X\n", -- RREG32(mmUVD_CGC_GATE)); -- dev_info(adev->dev, " UVD_CGC_CTRL=0x%08X\n", -- RREG32(mmUVD_CGC_CTRL)); -- dev_info(adev->dev, " UVD_LMI_CTRL2=0x%08X\n", -- RREG32(mmUVD_LMI_CTRL2)); -- dev_info(adev->dev, " UVD_MASTINT_EN=0x%08X\n", -- RREG32(mmUVD_MASTINT_EN)); -- dev_info(adev->dev, " UVD_LMI_ADDR_EXT=0x%08X\n", -- RREG32(mmUVD_LMI_ADDR_EXT)); -- dev_info(adev->dev, " UVD_LMI_CTRL=0x%08X\n", -- RREG32(mmUVD_LMI_CTRL)); -- dev_info(adev->dev, " UVD_LMI_SWAP_CNTL=0x%08X\n", -- RREG32(mmUVD_LMI_SWAP_CNTL)); -- dev_info(adev->dev, " UVD_MP_SWAP_CNTL=0x%08X\n", -- RREG32(mmUVD_MP_SWAP_CNTL)); -- dev_info(adev->dev, " UVD_MPC_SET_MUXA0=0x%08X\n", -- RREG32(mmUVD_MPC_SET_MUXA0)); -- dev_info(adev->dev, " UVD_MPC_SET_MUXA1=0x%08X\n", -- RREG32(mmUVD_MPC_SET_MUXA1)); -- dev_info(adev->dev, " UVD_MPC_SET_MUXB0=0x%08X\n", -- RREG32(mmUVD_MPC_SET_MUXB0)); -- dev_info(adev->dev, " UVD_MPC_SET_MUXB1=0x%08X\n", -- RREG32(mmUVD_MPC_SET_MUXB1)); -- dev_info(adev->dev, " UVD_MPC_SET_MUX=0x%08X\n", -- RREG32(mmUVD_MPC_SET_MUX)); -- dev_info(adev->dev, " UVD_MPC_SET_ALU=0x%08X\n", -- RREG32(mmUVD_MPC_SET_ALU)); -- dev_info(adev->dev, " UVD_VCPU_CACHE_OFFSET0=0x%08X\n", -- RREG32(mmUVD_VCPU_CACHE_OFFSET0)); -- dev_info(adev->dev, " UVD_VCPU_CACHE_SIZE0=0x%08X\n", -- RREG32(mmUVD_VCPU_CACHE_SIZE0)); -- dev_info(adev->dev, " UVD_VCPU_CACHE_OFFSET1=0x%08X\n", -- RREG32(mmUVD_VCPU_CACHE_OFFSET1)); -- dev_info(adev->dev, " UVD_VCPU_CACHE_SIZE1=0x%08X\n", -- RREG32(mmUVD_VCPU_CACHE_SIZE1)); -- dev_info(adev->dev, " UVD_VCPU_CACHE_OFFSET2=0x%08X\n", -- RREG32(mmUVD_VCPU_CACHE_OFFSET2)); -- dev_info(adev->dev, " UVD_VCPU_CACHE_SIZE2=0x%08X\n", -- RREG32(mmUVD_VCPU_CACHE_SIZE2)); -- dev_info(adev->dev, " UVD_VCPU_CNTL=0x%08X\n", -- RREG32(mmUVD_VCPU_CNTL)); -- dev_info(adev->dev, " UVD_SOFT_RESET=0x%08X\n", -- RREG32(mmUVD_SOFT_RESET)); -- dev_info(adev->dev, " UVD_LMI_RBC_IB_64BIT_BAR_LOW=0x%08X\n", -- RREG32(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW)); -- dev_info(adev->dev, " UVD_LMI_RBC_IB_64BIT_BAR_HIGH=0x%08X\n", -- RREG32(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH)); -- dev_info(adev->dev, " UVD_RBC_IB_SIZE=0x%08X\n", -- RREG32(mmUVD_RBC_IB_SIZE)); -- dev_info(adev->dev, " UVD_LMI_RBC_RB_64BIT_BAR_LOW=0x%08X\n", -- RREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW)); -- dev_info(adev->dev, " UVD_LMI_RBC_RB_64BIT_BAR_HIGH=0x%08X\n", -- RREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH)); -- dev_info(adev->dev, " UVD_RBC_RB_RPTR=0x%08X\n", -- RREG32(mmUVD_RBC_RB_RPTR)); -- dev_info(adev->dev, " UVD_RBC_RB_WPTR=0x%08X\n", -- RREG32(mmUVD_RBC_RB_WPTR)); -- dev_info(adev->dev, " UVD_RBC_RB_WPTR_CNTL=0x%08X\n", -- RREG32(mmUVD_RBC_RB_WPTR_CNTL)); -- dev_info(adev->dev, " UVD_RBC_RB_CNTL=0x%08X\n", -- RREG32(mmUVD_RBC_RB_CNTL)); -- dev_info(adev->dev, " UVD_STATUS=0x%08X\n", -- RREG32(mmUVD_STATUS)); -- dev_info(adev->dev, " UVD_SEMA_TIMEOUT_STATUS=0x%08X\n", -- RREG32(mmUVD_SEMA_TIMEOUT_STATUS)); -- dev_info(adev->dev, " UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL=0x%08X\n", -- RREG32(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL)); -- dev_info(adev->dev, " UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL=0x%08X\n", -- RREG32(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL)); -- dev_info(adev->dev, " UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL=0x%08X\n", -- RREG32(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL)); -- dev_info(adev->dev, " UVD_CONTEXT_ID=0x%08X\n", -- RREG32(mmUVD_CONTEXT_ID)); -- dev_info(adev->dev, " UVD_UDEC_ADDR_CONFIG=0x%08X\n", -- RREG32(mmUVD_UDEC_ADDR_CONFIG)); -- dev_info(adev->dev, " UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n", -- RREG32(mmUVD_UDEC_DB_ADDR_CONFIG)); -- dev_info(adev->dev, " UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n", -- RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG)); --} -- - static int uvd_v5_0_set_interrupt_state(struct amdgpu_device *adev, - struct amdgpu_irq_src *source, - unsigned type, -@@ -916,7 +802,6 @@ const struct amd_ip_funcs uvd_v5_0_ip_funcs = { - .is_idle = uvd_v5_0_is_idle, - .wait_for_idle = uvd_v5_0_wait_for_idle, - .soft_reset = uvd_v5_0_soft_reset, -- .print_status = uvd_v5_0_print_status, - .set_clockgating_state = uvd_v5_0_set_clockgating_state, - .set_powergating_state = uvd_v5_0_set_powergating_state, - }; -diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c -index 7e7c3da..5665a4f 100644 ---- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c -+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c -@@ -706,112 +706,6 @@ static int uvd_v6_0_soft_reset(void *handle) - return uvd_v6_0_start(adev); - } - --static void uvd_v6_0_print_status(void *handle) --{ -- struct amdgpu_device *adev = (struct amdgpu_device *)handle; -- dev_info(adev->dev, "UVD 6.0 registers\n"); -- dev_info(adev->dev, " UVD_SEMA_ADDR_LOW=0x%08X\n", -- RREG32(mmUVD_SEMA_ADDR_LOW)); -- dev_info(adev->dev, " UVD_SEMA_ADDR_HIGH=0x%08X\n", -- RREG32(mmUVD_SEMA_ADDR_HIGH)); -- dev_info(adev->dev, " UVD_SEMA_CMD=0x%08X\n", -- RREG32(mmUVD_SEMA_CMD)); -- dev_info(adev->dev, " UVD_GPCOM_VCPU_CMD=0x%08X\n", -- RREG32(mmUVD_GPCOM_VCPU_CMD)); -- dev_info(adev->dev, " UVD_GPCOM_VCPU_DATA0=0x%08X\n", -- RREG32(mmUVD_GPCOM_VCPU_DATA0)); -- dev_info(adev->dev, " UVD_GPCOM_VCPU_DATA1=0x%08X\n", -- RREG32(mmUVD_GPCOM_VCPU_DATA1)); -- dev_info(adev->dev, " UVD_ENGINE_CNTL=0x%08X\n", -- RREG32(mmUVD_ENGINE_CNTL)); -- dev_info(adev->dev, " UVD_UDEC_ADDR_CONFIG=0x%08X\n", -- RREG32(mmUVD_UDEC_ADDR_CONFIG)); -- dev_info(adev->dev, " UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n", -- RREG32(mmUVD_UDEC_DB_ADDR_CONFIG)); -- dev_info(adev->dev, " UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n", -- RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG)); -- dev_info(adev->dev, " UVD_SEMA_CNTL=0x%08X\n", -- RREG32(mmUVD_SEMA_CNTL)); -- dev_info(adev->dev, " UVD_LMI_EXT40_ADDR=0x%08X\n", -- RREG32(mmUVD_LMI_EXT40_ADDR)); -- dev_info(adev->dev, " UVD_CTX_INDEX=0x%08X\n", -- RREG32(mmUVD_CTX_INDEX)); -- dev_info(adev->dev, " UVD_CTX_DATA=0x%08X\n", -- RREG32(mmUVD_CTX_DATA)); -- dev_info(adev->dev, " UVD_CGC_GATE=0x%08X\n", -- RREG32(mmUVD_CGC_GATE)); -- dev_info(adev->dev, " UVD_CGC_CTRL=0x%08X\n", -- RREG32(mmUVD_CGC_CTRL)); -- dev_info(adev->dev, " UVD_LMI_CTRL2=0x%08X\n", -- RREG32(mmUVD_LMI_CTRL2)); -- dev_info(adev->dev, " UVD_MASTINT_EN=0x%08X\n", -- RREG32(mmUVD_MASTINT_EN)); -- dev_info(adev->dev, " UVD_LMI_ADDR_EXT=0x%08X\n", -- RREG32(mmUVD_LMI_ADDR_EXT)); -- dev_info(adev->dev, " UVD_LMI_CTRL=0x%08X\n", -- RREG32(mmUVD_LMI_CTRL)); -- dev_info(adev->dev, " UVD_LMI_SWAP_CNTL=0x%08X\n", -- RREG32(mmUVD_LMI_SWAP_CNTL)); -- dev_info(adev->dev, " UVD_MP_SWAP_CNTL=0x%08X\n", -- RREG32(mmUVD_MP_SWAP_CNTL)); -- dev_info(adev->dev, " UVD_MPC_SET_MUXA0=0x%08X\n", -- RREG32(mmUVD_MPC_SET_MUXA0)); -- dev_info(adev->dev, " UVD_MPC_SET_MUXA1=0x%08X\n", -- RREG32(mmUVD_MPC_SET_MUXA1)); -- dev_info(adev->dev, " UVD_MPC_SET_MUXB0=0x%08X\n", -- RREG32(mmUVD_MPC_SET_MUXB0)); -- dev_info(adev->dev, " UVD_MPC_SET_MUXB1=0x%08X\n", -- RREG32(mmUVD_MPC_SET_MUXB1)); -- dev_info(adev->dev, " UVD_MPC_SET_MUX=0x%08X\n", -- RREG32(mmUVD_MPC_SET_MUX)); -- dev_info(adev->dev, " UVD_MPC_SET_ALU=0x%08X\n", -- RREG32(mmUVD_MPC_SET_ALU)); -- dev_info(adev->dev, " UVD_VCPU_CACHE_OFFSET0=0x%08X\n", -- RREG32(mmUVD_VCPU_CACHE_OFFSET0)); -- dev_info(adev->dev, " UVD_VCPU_CACHE_SIZE0=0x%08X\n", -- RREG32(mmUVD_VCPU_CACHE_SIZE0)); -- dev_info(adev->dev, " UVD_VCPU_CACHE_OFFSET1=0x%08X\n", -- RREG32(mmUVD_VCPU_CACHE_OFFSET1)); -- dev_info(adev->dev, " UVD_VCPU_CACHE_SIZE1=0x%08X\n", -- RREG32(mmUVD_VCPU_CACHE_SIZE1)); -- dev_info(adev->dev, " UVD_VCPU_CACHE_OFFSET2=0x%08X\n", -- RREG32(mmUVD_VCPU_CACHE_OFFSET2)); -- dev_info(adev->dev, " UVD_VCPU_CACHE_SIZE2=0x%08X\n", -- RREG32(mmUVD_VCPU_CACHE_SIZE2)); -- dev_info(adev->dev, " UVD_VCPU_CNTL=0x%08X\n", -- RREG32(mmUVD_VCPU_CNTL)); -- dev_info(adev->dev, " UVD_SOFT_RESET=0x%08X\n", -- RREG32(mmUVD_SOFT_RESET)); -- dev_info(adev->dev, " UVD_RBC_IB_SIZE=0x%08X\n", -- RREG32(mmUVD_RBC_IB_SIZE)); -- dev_info(adev->dev, " UVD_RBC_RB_RPTR=0x%08X\n", -- RREG32(mmUVD_RBC_RB_RPTR)); -- dev_info(adev->dev, " UVD_RBC_RB_WPTR=0x%08X\n", -- RREG32(mmUVD_RBC_RB_WPTR)); -- dev_info(adev->dev, " UVD_RBC_RB_WPTR_CNTL=0x%08X\n", -- RREG32(mmUVD_RBC_RB_WPTR_CNTL)); -- dev_info(adev->dev, " UVD_RBC_RB_CNTL=0x%08X\n", -- RREG32(mmUVD_RBC_RB_CNTL)); -- dev_info(adev->dev, " UVD_STATUS=0x%08X\n", -- RREG32(mmUVD_STATUS)); -- dev_info(adev->dev, " UVD_SEMA_TIMEOUT_STATUS=0x%08X\n", -- RREG32(mmUVD_SEMA_TIMEOUT_STATUS)); -- dev_info(adev->dev, " UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL=0x%08X\n", -- RREG32(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL)); -- dev_info(adev->dev, " UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL=0x%08X\n", -- RREG32(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL)); -- dev_info(adev->dev, " UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL=0x%08X\n", -- RREG32(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL)); -- dev_info(adev->dev, " UVD_CONTEXT_ID=0x%08X\n", -- RREG32(mmUVD_CONTEXT_ID)); -- dev_info(adev->dev, " UVD_UDEC_ADDR_CONFIG=0x%08X\n", -- RREG32(mmUVD_UDEC_ADDR_CONFIG)); -- dev_info(adev->dev, " UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n", -- RREG32(mmUVD_UDEC_DB_ADDR_CONFIG)); -- dev_info(adev->dev, " UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n", -- RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG)); --} -- - static int uvd_v6_0_set_interrupt_state(struct amdgpu_device *adev, - struct amdgpu_irq_src *source, - unsigned type, -@@ -993,7 +887,6 @@ const struct amd_ip_funcs uvd_v6_0_ip_funcs = { - .is_idle = uvd_v6_0_is_idle, - .wait_for_idle = uvd_v6_0_wait_for_idle, - .soft_reset = uvd_v6_0_soft_reset, -- .print_status = uvd_v6_0_print_status, - .set_clockgating_state = uvd_v6_0_set_clockgating_state, - .set_powergating_state = uvd_v6_0_set_powergating_state, - }; -diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c -index ab9ee2a..95f6e57 100644 ---- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c -+++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c -@@ -495,75 +495,6 @@ static int vce_v2_0_soft_reset(void *handle) - return vce_v2_0_start(adev); - } - --static void vce_v2_0_print_status(void *handle) --{ -- struct amdgpu_device *adev = (struct amdgpu_device *)handle; -- -- dev_info(adev->dev, "VCE 2.0 registers\n"); -- dev_info(adev->dev, " VCE_STATUS=0x%08X\n", -- RREG32(mmVCE_STATUS)); -- dev_info(adev->dev, " VCE_VCPU_CNTL=0x%08X\n", -- RREG32(mmVCE_VCPU_CNTL)); -- dev_info(adev->dev, " VCE_VCPU_CACHE_OFFSET0=0x%08X\n", -- RREG32(mmVCE_VCPU_CACHE_OFFSET0)); -- dev_info(adev->dev, " VCE_VCPU_CACHE_SIZE0=0x%08X\n", -- RREG32(mmVCE_VCPU_CACHE_SIZE0)); -- dev_info(adev->dev, " VCE_VCPU_CACHE_OFFSET1=0x%08X\n", -- RREG32(mmVCE_VCPU_CACHE_OFFSET1)); -- dev_info(adev->dev, " VCE_VCPU_CACHE_SIZE1=0x%08X\n", -- RREG32(mmVCE_VCPU_CACHE_SIZE1)); -- dev_info(adev->dev, " VCE_VCPU_CACHE_OFFSET2=0x%08X\n", -- RREG32(mmVCE_VCPU_CACHE_OFFSET2)); -- dev_info(adev->dev, " VCE_VCPU_CACHE_SIZE2=0x%08X\n", -- RREG32(mmVCE_VCPU_CACHE_SIZE2)); -- dev_info(adev->dev, " VCE_SOFT_RESET=0x%08X\n", -- RREG32(mmVCE_SOFT_RESET)); -- dev_info(adev->dev, " VCE_RB_BASE_LO2=0x%08X\n", -- RREG32(mmVCE_RB_BASE_LO2)); -- dev_info(adev->dev, " VCE_RB_BASE_HI2=0x%08X\n", -- RREG32(mmVCE_RB_BASE_HI2)); -- dev_info(adev->dev, " VCE_RB_SIZE2=0x%08X\n", -- RREG32(mmVCE_RB_SIZE2)); -- dev_info(adev->dev, " VCE_RB_RPTR2=0x%08X\n", -- RREG32(mmVCE_RB_RPTR2)); -- dev_info(adev->dev, " VCE_RB_WPTR2=0x%08X\n", -- RREG32(mmVCE_RB_WPTR2)); -- dev_info(adev->dev, " VCE_RB_BASE_LO=0x%08X\n", -- RREG32(mmVCE_RB_BASE_LO)); -- dev_info(adev->dev, " VCE_RB_BASE_HI=0x%08X\n", -- RREG32(mmVCE_RB_BASE_HI)); -- dev_info(adev->dev, " VCE_RB_SIZE=0x%08X\n", -- RREG32(mmVCE_RB_SIZE)); -- dev_info(adev->dev, " VCE_RB_RPTR=0x%08X\n", -- RREG32(mmVCE_RB_RPTR)); -- dev_info(adev->dev, " VCE_RB_WPTR=0x%08X\n", -- RREG32(mmVCE_RB_WPTR)); -- dev_info(adev->dev, " VCE_CLOCK_GATING_A=0x%08X\n", -- RREG32(mmVCE_CLOCK_GATING_A)); -- dev_info(adev->dev, " VCE_CLOCK_GATING_B=0x%08X\n", -- RREG32(mmVCE_CLOCK_GATING_B)); -- dev_info(adev->dev, " VCE_CGTT_CLK_OVERRIDE=0x%08X\n", -- RREG32(mmVCE_CGTT_CLK_OVERRIDE)); -- dev_info(adev->dev, " VCE_UENC_CLOCK_GATING=0x%08X\n", -- RREG32(mmVCE_UENC_CLOCK_GATING)); -- dev_info(adev->dev, " VCE_UENC_REG_CLOCK_GATING=0x%08X\n", -- RREG32(mmVCE_UENC_REG_CLOCK_GATING)); -- dev_info(adev->dev, " VCE_SYS_INT_EN=0x%08X\n", -- RREG32(mmVCE_SYS_INT_EN)); -- dev_info(adev->dev, " VCE_LMI_CTRL2=0x%08X\n", -- RREG32(mmVCE_LMI_CTRL2)); -- dev_info(adev->dev, " VCE_LMI_CTRL=0x%08X\n", -- RREG32(mmVCE_LMI_CTRL)); -- dev_info(adev->dev, " VCE_LMI_VM_CTRL=0x%08X\n", -- RREG32(mmVCE_LMI_VM_CTRL)); -- dev_info(adev->dev, " VCE_LMI_SWAP_CNTL=0x%08X\n", -- RREG32(mmVCE_LMI_SWAP_CNTL)); -- dev_info(adev->dev, " VCE_LMI_SWAP_CNTL1=0x%08X\n", -- RREG32(mmVCE_LMI_SWAP_CNTL1)); -- dev_info(adev->dev, " VCE_LMI_CACHE_CTRL=0x%08X\n", -- RREG32(mmVCE_LMI_CACHE_CTRL)); --} -- - static int vce_v2_0_set_interrupt_state(struct amdgpu_device *adev, - struct amdgpu_irq_src *source, - unsigned type, -@@ -647,7 +578,6 @@ const struct amd_ip_funcs vce_v2_0_ip_funcs = { - .is_idle = vce_v2_0_is_idle, - .wait_for_idle = vce_v2_0_wait_for_idle, - .soft_reset = vce_v2_0_soft_reset, -- .print_status = vce_v2_0_print_status, - .set_clockgating_state = vce_v2_0_set_clockgating_state, - .set_powergating_state = vce_v2_0_set_powergating_state, - }; -diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c -index 5834285..e1d6ae7 100644 ---- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c -+++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c -@@ -566,73 +566,6 @@ static int vce_v3_0_soft_reset(void *handle) - return vce_v3_0_start(adev); - } - --static void vce_v3_0_print_status(void *handle) --{ -- struct amdgpu_device *adev = (struct amdgpu_device *)handle; -- -- dev_info(adev->dev, "VCE 3.0 registers\n"); -- dev_info(adev->dev, " VCE_STATUS=0x%08X\n", -- RREG32(mmVCE_STATUS)); -- dev_info(adev->dev, " VCE_VCPU_CNTL=0x%08X\n", -- RREG32(mmVCE_VCPU_CNTL)); -- dev_info(adev->dev, " VCE_VCPU_CACHE_OFFSET0=0x%08X\n", -- RREG32(mmVCE_VCPU_CACHE_OFFSET0)); -- dev_info(adev->dev, " VCE_VCPU_CACHE_SIZE0=0x%08X\n", -- RREG32(mmVCE_VCPU_CACHE_SIZE0)); -- dev_info(adev->dev, " VCE_VCPU_CACHE_OFFSET1=0x%08X\n", -- RREG32(mmVCE_VCPU_CACHE_OFFSET1)); -- dev_info(adev->dev, " VCE_VCPU_CACHE_SIZE1=0x%08X\n", -- RREG32(mmVCE_VCPU_CACHE_SIZE1)); -- dev_info(adev->dev, " VCE_VCPU_CACHE_OFFSET2=0x%08X\n", -- RREG32(mmVCE_VCPU_CACHE_OFFSET2)); -- dev_info(adev->dev, " VCE_VCPU_CACHE_SIZE2=0x%08X\n", -- RREG32(mmVCE_VCPU_CACHE_SIZE2)); -- dev_info(adev->dev, " VCE_SOFT_RESET=0x%08X\n", -- RREG32(mmVCE_SOFT_RESET)); -- dev_info(adev->dev, " VCE_RB_BASE_LO2=0x%08X\n", -- RREG32(mmVCE_RB_BASE_LO2)); -- dev_info(adev->dev, " VCE_RB_BASE_HI2=0x%08X\n", -- RREG32(mmVCE_RB_BASE_HI2)); -- dev_info(adev->dev, " VCE_RB_SIZE2=0x%08X\n", -- RREG32(mmVCE_RB_SIZE2)); -- dev_info(adev->dev, " VCE_RB_RPTR2=0x%08X\n", -- RREG32(mmVCE_RB_RPTR2)); -- dev_info(adev->dev, " VCE_RB_WPTR2=0x%08X\n", -- RREG32(mmVCE_RB_WPTR2)); -- dev_info(adev->dev, " VCE_RB_BASE_LO=0x%08X\n", -- RREG32(mmVCE_RB_BASE_LO)); -- dev_info(adev->dev, " VCE_RB_BASE_HI=0x%08X\n", -- RREG32(mmVCE_RB_BASE_HI)); -- dev_info(adev->dev, " VCE_RB_SIZE=0x%08X\n", -- RREG32(mmVCE_RB_SIZE)); -- dev_info(adev->dev, " VCE_RB_RPTR=0x%08X\n", -- RREG32(mmVCE_RB_RPTR)); -- dev_info(adev->dev, " VCE_RB_WPTR=0x%08X\n", -- RREG32(mmVCE_RB_WPTR)); -- dev_info(adev->dev, " VCE_CLOCK_GATING_A=0x%08X\n", -- RREG32(mmVCE_CLOCK_GATING_A)); -- dev_info(adev->dev, " VCE_CLOCK_GATING_B=0x%08X\n", -- RREG32(mmVCE_CLOCK_GATING_B)); -- dev_info(adev->dev, " VCE_UENC_CLOCK_GATING=0x%08X\n", -- RREG32(mmVCE_UENC_CLOCK_GATING)); -- dev_info(adev->dev, " VCE_UENC_REG_CLOCK_GATING=0x%08X\n", -- RREG32(mmVCE_UENC_REG_CLOCK_GATING)); -- dev_info(adev->dev, " VCE_SYS_INT_EN=0x%08X\n", -- RREG32(mmVCE_SYS_INT_EN)); -- dev_info(adev->dev, " VCE_LMI_CTRL2=0x%08X\n", -- RREG32(mmVCE_LMI_CTRL2)); -- dev_info(adev->dev, " VCE_LMI_CTRL=0x%08X\n", -- RREG32(mmVCE_LMI_CTRL)); -- dev_info(adev->dev, " VCE_LMI_VM_CTRL=0x%08X\n", -- RREG32(mmVCE_LMI_VM_CTRL)); -- dev_info(adev->dev, " VCE_LMI_SWAP_CNTL=0x%08X\n", -- RREG32(mmVCE_LMI_SWAP_CNTL)); -- dev_info(adev->dev, " VCE_LMI_SWAP_CNTL1=0x%08X\n", -- RREG32(mmVCE_LMI_SWAP_CNTL1)); -- dev_info(adev->dev, " VCE_LMI_CACHE_CTRL=0x%08X\n", -- RREG32(mmVCE_LMI_CACHE_CTRL)); --} -- - static int vce_v3_0_set_interrupt_state(struct amdgpu_device *adev, - struct amdgpu_irq_src *source, - unsigned type, -@@ -752,7 +685,6 @@ const struct amd_ip_funcs vce_v3_0_ip_funcs = { - .is_idle = vce_v3_0_is_idle, - .wait_for_idle = vce_v3_0_wait_for_idle, - .soft_reset = vce_v3_0_soft_reset, -- .print_status = vce_v3_0_print_status, - .set_clockgating_state = vce_v3_0_set_clockgating_state, - .set_powergating_state = vce_v3_0_set_powergating_state, - }; -diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c -index b5602ac..61f5555 100644 ---- a/drivers/gpu/drm/amd/amdgpu/vi.c -+++ b/drivers/gpu/drm/amd/amdgpu/vi.c -@@ -1624,11 +1624,6 @@ static int vi_common_wait_for_idle(void *handle) - return 0; - } - --static void vi_common_print_status(void *handle) --{ -- return; --} -- - static int vi_common_soft_reset(void *handle) - { - return 0; -@@ -1753,7 +1748,6 @@ const struct amd_ip_funcs vi_common_ip_funcs = { - .is_idle = vi_common_is_idle, - .wait_for_idle = vi_common_wait_for_idle, - .soft_reset = vi_common_soft_reset, -- .print_status = vi_common_print_status, - .set_clockgating_state = vi_common_set_clockgating_state, - .set_powergating_state = vi_common_set_powergating_state, - }; -diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c -index 4defc70..468c4ba 100644 ---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c -+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c -@@ -124,13 +124,6 @@ static int dm_wait_for_idle(void *handle) - return 0; - } - --static void dm_print_status(void *handle) --{ -- struct amdgpu_device *adev = (struct amdgpu_device *)handle; -- dev_info(adev->dev, "DCE registers\n"); -- /* XXX todo */ --} -- - static int dm_soft_reset(void *handle) - { - /* XXX todo */ -@@ -639,7 +632,6 @@ const struct amd_ip_funcs amdgpu_dm_funcs = { - .is_idle = dm_is_idle, - .wait_for_idle = dm_wait_for_idle, - .soft_reset = dm_soft_reset, -- .print_status = dm_print_status, - .set_clockgating_state = dm_set_clockgating_state, - .set_powergating_state = dm_set_powergating_state, - }; -diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h -index e56d8a3..ea9ee46 100644 ---- a/drivers/gpu/drm/amd/include/amd_shared.h -+++ b/drivers/gpu/drm/amd/include/amd_shared.h -@@ -165,8 +165,6 @@ struct amd_ip_funcs { - int (*wait_for_idle)(void *handle); - /* soft reset the IP block */ - int (*soft_reset)(void *handle); -- /* dump the IP block status registers */ -- void (*print_status)(void *handle); - /* enable/disable cg for the IP block */ - int (*set_clockgating_state)(void *handle, - enum amd_clockgating_state state); -diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c -index 0527ae3..aba587c 100644 ---- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c -+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c -@@ -180,10 +180,6 @@ static int pp_sw_reset(void *handle) - return 0; - } - --static void pp_print_status(void *handle) --{ -- --} - - static int pp_set_clockgating_state(void *handle, - enum amd_clockgating_state state) -@@ -355,7 +351,6 @@ const struct amd_ip_funcs pp_ip_funcs = { - .is_idle = pp_is_idle, - .wait_for_idle = pp_wait_for_idle, - .soft_reset = pp_sw_reset, -- .print_status = pp_print_status, - .set_clockgating_state = pp_set_clockgating_state, - .set_powergating_state = pp_set_powergating_state, - }; --- -2.7.4 - |