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-rw-r--r--common/recipes-kernel/linux/files/1006-drm-amd-dal-remove-dead-code.patch1233
1 files changed, 0 insertions, 1233 deletions
diff --git a/common/recipes-kernel/linux/files/1006-drm-amd-dal-remove-dead-code.patch b/common/recipes-kernel/linux/files/1006-drm-amd-dal-remove-dead-code.patch
deleted file mode 100644
index 0c07856f..00000000
--- a/common/recipes-kernel/linux/files/1006-drm-amd-dal-remove-dead-code.patch
+++ /dev/null
@@ -1,1233 +0,0 @@
-From bbda780aa778a436e8310692181f620f52a60ca2 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?J=C3=A9r=C3=B4me=20Glisse?= <jglisse@redhat.com>
-Date: Thu, 24 Mar 2016 14:17:14 +0100
-Subject: [PATCH 1006/1110] drm/amd/dal: remove dead code.
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-More seriously ...
-
-Signed-off-by: Jérôme Glisse <jglisse@redhat.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/dc_types.h | 24 --
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_types.h | 28 ---
- drivers/gpu/drm/amd/dal/dc/dm_services_types.h | 8 -
- drivers/gpu/drm/amd/dal/dc/inc/compressor.h | 48 ----
- drivers/gpu/drm/amd/dal/dc/inc/core_types.h | 10 -
- drivers/gpu/drm/amd/dal/dc/inc/hw/ipp.h | 5 -
- drivers/gpu/drm/amd/dal/dc/inc/hw/link_encoder.h | 3 -
- drivers/gpu/drm/amd/dal/dc/inc/hw/opp.h | 7 -
- drivers/gpu/drm/amd/dal/include/dal_types.h | 126 ----------
- drivers/gpu/drm/amd/dal/include/dcs_types.h | 269 ---------------------
- .../drm/amd/dal/include/display_clock_interface.h | 23 --
- drivers/gpu/drm/amd/dal/include/dmcu_types.h | 45 ----
- drivers/gpu/drm/amd/dal/include/dpcd_defs.h | 9 -
- .../drm/amd/dal/include/grph_object_ctrl_defs.h | 63 -----
- drivers/gpu/drm/amd/dal/include/grph_object_defs.h | 65 -----
- .../drm/amd/dal/include/hw_sequencer_interface.h | 15 --
- .../gpu/drm/amd/dal/include/hw_sequencer_types.h | 37 ---
- drivers/gpu/drm/amd/dal/include/video_csc_types.h | 40 ---
- .../gpu/drm/amd/dal/include/video_gamma_types.h | 16 --
- 19 files changed, 841 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_types.h b/drivers/gpu/drm/amd/dal/dc/dc_types.h
-index a375b00..8bc0413 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_types.h
-@@ -187,15 +187,6 @@ enum view_3d_format {
- VIEW_3D_FORMAT_FIRST = VIEW_3D_FORMAT_FRAME_SEQUENTIAL
- };
-
--struct view_stereo_3d_support {
-- enum view_3d_format format;
-- struct {
-- uint32_t CLONE_MODE :1;
-- uint32_t SCALING :1;
-- uint32_t SINGLE_FRAME_SW_PACKED :1;
-- } features;
--};
--
- enum plane_stereo_format {
- PLANE_STEREO_FORMAT_NONE = 0,
- PLANE_STEREO_FORMAT_SIDE_BY_SIDE = 1,
-@@ -280,11 +271,6 @@ struct view {
- uint32_t height;
- };
-
--struct dc_resolution {
-- uint32_t width;
-- uint32_t height;
--};
--
- struct dc_mode_flags {
- /* note: part of refresh rate flag*/
- uint32_t INTERLACE :1;
-@@ -441,16 +427,6 @@ enum scaling_transformation {
- SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE
- };
-
--struct view_position {
-- uint32_t x;
-- uint32_t y;
--};
--
--struct render_mode {
-- struct view view;
-- enum pixel_format pixel_format;
--};
--
- /* audio*/
-
- union audio_sample_rates {
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_types.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_types.h
-index e61a494..f68d51c 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_types.h
-@@ -26,33 +26,5 @@
- #define __DCE110_TYPES_H_
-
- #define GAMMA_SEGMENTS_NUM 16
--struct end_point {
-- uint32_t x_value;
-- uint32_t y_value;
-- uint32_t slope;
--};
--
--struct pwl_segment {
-- uint32_t r_value;
-- uint32_t g_value;
-- uint32_t b_value;
-- uint32_t r_delta;
-- uint32_t g_delta;
-- uint32_t b_delta;
--};
--
--struct dce110_opp_regamma_params {
-- struct {
-- uint8_t num_segments[GAMMA_SEGMENTS_NUM];
-- uint16_t offsets[GAMMA_SEGMENTS_NUM];
-- struct end_point first;
-- struct end_point last;
-- } region_config;
--
-- struct {
-- struct pwl_segment *segments;
-- int num_pwl_segments;
-- } pwl_config;
--};
-
- #endif /* DRIVERS_GPU_DRM_AMD_DAL_DEV_DC_DCE110_DCE110_TYPES_H_ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/dm_services_types.h b/drivers/gpu/drm/amd/dal/dc/dm_services_types.h
-index 982e968..62ff098 100644
---- a/drivers/gpu/drm/amd/dal/dc/dm_services_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dm_services_types.h
-@@ -260,12 +260,4 @@ struct dm_pp_display_configuration {
- uint32_t line_time_in_us;
- };
-
--struct dm_pp_static_clock_info {
-- uint32_t max_sclk_khz;
-- uint32_t max_mclk_khz;
--
-- /* max possible display block clocks state */
-- enum dm_pp_clocks_state max_clocks_state;
--};
--
- #endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/compressor.h b/drivers/gpu/drm/amd/dal/dc/inc/compressor.h
-index 4992ffd..a2e44b5 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/compressor.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/compressor.h
-@@ -49,59 +49,11 @@ struct compr_addr_and_pitch_params {
- uint32_t source_view_height;
- };
-
--struct fbc_lpt_config {
-- uint32_t mem_channels_num;
-- uint32_t banks_num;
-- uint32_t chan_interleave_size;
-- uint32_t row_size;
--};
--
--struct fbc_input_info {
-- bool dynamic_fbc_buffer_alloc;
-- uint32_t source_view_width;
-- uint32_t source_view_height;
-- uint32_t active_targets_num;
-- struct fbc_lpt_config lpt_config;
--};
--
--struct fbc_requested_compressed_size {
-- uint32_t preferred_size;
-- uint32_t preferred_size_alignment;
-- uint32_t min_size;
-- uint32_t min_size_alignment;
-- union {
-- struct {
-- /*Above preferred_size must be allocated in FB pool */
-- uint32_t PREFERRED_MUST_BE_FRAME_BUFFER_POOL:1;
-- /*Above min_size must be allocated in FB pool */
-- uint32_t MIN_MUST_BE_FRAME_BUFFER_POOL:1;
-- } flags;
-- uint32_t bits;
-- };
--};
--
--struct fbc_compressed_surface_info {
-- union fbc_physical_address compressed_surface_address;
-- uint32_t allocated_size;
-- union {
-- struct {
-- uint32_t FB_POOL:1; /*Allocated in FB Pool */
-- uint32_t DYNAMIC_ALLOC:1; /*Dynamic allocation */
-- } allocation_flags;
-- uint32_t bits;
-- };
--};
--
- enum fbc_hw_max_resolution_supported {
- FBC_MAX_X = 3840,
- FBC_MAX_Y = 2400
- };
-
--struct fbc_max_resolution_supported {
-- uint32_t source_view_width;
-- uint32_t source_view_height;
--};
--
- struct compressor {
- struct dc_context *ctx;
- uint32_t attached_inst;
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-index 14b62ab..9093e97 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-@@ -128,16 +128,6 @@ struct link_init_data {
- struct adapter_service *adapter_srv;
- };
-
--struct link_caps {
-- /* support for Spread Spectrum(SS) */
-- bool ss_supported;
-- /* DP link settings (laneCount, linkRate, Spread) */
-- uint32_t lane_count;
-- uint32_t rate;
-- uint32_t spread;
-- enum dpcd_revision dpcd_revision;
--};
--
- struct dpcd_caps {
- union dpcd_rev dpcd_rev;
- union max_lane_count max_ln_count;
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw/ipp.h b/drivers/gpu/drm/amd/dal/dc/inc/hw/ipp.h
-index f419331..9063308 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/hw/ipp.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/hw/ipp.h
-@@ -67,11 +67,6 @@ enum ovl_color_space {
- OVL_COLOR_SPACE_YUV709
- };
-
--struct dcp_video_matrix {
-- enum ovl_color_space color_space;
-- int32_t value[MAXTRIX_COEFFICIENTS_NUMBER];
--};
--
- enum expansion_mode {
- EXPANSION_MODE_ZERO,
- EXPANSION_MODE_DYNAMIC
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/dal/dc/inc/hw/link_encoder.h
-index 115ef54..94dd422 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/hw/link_encoder.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/hw/link_encoder.h
-@@ -66,9 +66,6 @@ struct encoder_feature_support {
- unsigned int max_hdmi_pixel_clock;
- };
-
--struct link_enc_status {
-- int dummy; /*TODO*/
--};
- struct link_encoder {
- struct link_encoder_funcs *funcs;
- struct adapter_service *adapter_service;
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw/opp.h b/drivers/gpu/drm/amd/dal/dc/inc/hw/opp.h
-index 1c6bab3..3410357 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/hw/opp.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/hw/opp.h
-@@ -188,13 +188,6 @@ struct gamma_coefficients {
- struct fixed31_32 user_brightness;
- };
-
--struct csc_adjustments {
-- struct fixed31_32 contrast;
-- struct fixed31_32 saturation;
-- struct fixed31_32 brightness;
-- struct fixed31_32 hue;
--};
--
- struct pwl_float_data {
- struct fixed31_32 r;
- struct fixed31_32 g;
-diff --git a/drivers/gpu/drm/amd/dal/include/dal_types.h b/drivers/gpu/drm/amd/dal/include/dal_types.h
-index 21ee669..0e4c9a2 100644
---- a/drivers/gpu/drm/amd/dal/include/dal_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/dal_types.h
-@@ -49,130 +49,4 @@ enum dce_version {
- DCE_VERSION_MAX,
- };
-
--/* Wireless display structs */
--
--union dal_remote_display_cea_mode_bitmap {
-- struct {
-- uint32_t CEA_640X480_60P:1;/*0*/
-- uint32_t CEA_720X480_60P:1;/*1*/
-- uint32_t CEA_720X480_60I:1;/*2*/
-- uint32_t CEA_720X576_50P:1;/*3*/
-- uint32_t CEA_720X576_50I:1;/*4*/
-- uint32_t CEA_1280X720_30P:1;/*5*/
-- uint32_t CEA_1280X720_60P:1;/*6*/
-- uint32_t CEA_1920X1080_30P:1;/*7*/
-- uint32_t CEA_1920X1080_60P:1;/*8*/
-- uint32_t CEA_1920X1080_60I:1;/*9*/
-- uint32_t CEA_1280X720_25P:1;/*10*/
-- uint32_t CEA_1280X728_50P:1;/*11*/
-- uint32_t CEA_1920X1080_25P:1;/*12*/
-- uint32_t CEA_1920X1080_50P:1;/*13*/
-- uint32_t CEA_1920X1080_50I:1;/*14*/
-- uint32_t CEA_1280X1024_24P:1;/*15*/
-- uint32_t CEA_1920X1080_24P:1;/*16*/
-- uint32_t RESERVED:15;/*[17-31]*/
-- } flags;
-- uint32_t raw;
--};
--
--union dal_remote_display_vesa_mode_bitmap {
-- struct {
-- uint32_t VESA_800X600_30P:1;/*0*/
-- uint32_t VESA_800X600_60P:1;/*1*/
-- uint32_t VESA_1024X768_30P:1;/*2*/
-- uint32_t VESA_1024X768_60P:1;/*3*/
-- uint32_t VESA_1152X864_30P:1;/*4*/
-- uint32_t VESA_1152X864_60P:1;/*5*/
-- uint32_t VESA_1280X768_30P:1;/*6*/
-- uint32_t VESA_1280X768_60P:1;/*7*/
-- uint32_t VESA_1280X800_30P:1;/*8*/
-- uint32_t VESA_1280X800_60P:1;/*9*/
-- uint32_t VESA_1360X768_30P:1;/*10*/
-- uint32_t VESA_1360X768_60P:1;/*11*/
-- uint32_t VESA_1366X768_30P:1;/*12*/
-- uint32_t VESA_1366X768_60P:1;/*13*/
-- uint32_t VESA_1280X1024_30P:1;/*14*/
-- uint32_t VESA_1280X1024_60P:1;/*15*/
-- uint32_t VESA_1400X1050_30P:1;/*16*/
-- uint32_t VESA_1400X1050_60P:1;/*17*/
-- uint32_t VESA_1440X900_30P:1;/*18*/
-- uint32_t VESA_1440X900_60P:1;/*19*/
-- uint32_t VESA_1600X900_30P:1;/*20*/
-- uint32_t VESA_1600X900_60P:1;/*21*/
-- uint32_t VESA_1600X1200_30P:1;/*22*/
-- uint32_t VESA_1600X1200_60P:1;/*23*/
-- uint32_t VESA_1680X1024_30P:1;/*24*/
-- uint32_t VESA_1680X1024_60P:1;/*25*/
-- uint32_t VESA_1680X1050_30P:1;/*26*/
-- uint32_t VESA_1680X1050_60P:1;/*27*/
-- uint32_t VESA_1920X1200_30P:1;/*28*/
-- uint32_t VESA_1920X1200_60P:1;/*29*/
-- uint32_t RESERVED:2;/*[30-31]*/
-- } flags;
-- uint32_t raw;
--};
--
--union dal_remote_display_hh_mode_bitmap {
-- struct {
-- uint32_t HH_800X480_30P:1;/*0*/
-- uint32_t HH_800X480_60P:1;/*1*/
-- uint32_t HH_854X480_30P:1;/*2*/
-- uint32_t HH_854X480_60P:1;/*3*/
-- uint32_t HH_864X480_30P:1;/*4*/
-- uint32_t HH_864X480_60P:1;/*5*/
-- uint32_t HH_640X360_30P:1;/*6*/
-- uint32_t HH_640X360_60P:1;/*7*/
-- uint32_t HH_960X540_30P:1;/*8*/
-- uint32_t HH_960X540_60P:1;/*9*/
-- uint32_t HH_848X480_30P:1;/*10*/
-- uint32_t HH_848X480_60P:1;/*11*/
-- uint32_t RESERVED:20;/*[12-31]*/
-- } flags;
-- uint32_t raw;
--};
--
--union dal_remote_display_stereo_3d_mode_bitmap {
-- struct {
-- uint32_t STEREO_1920X1080_24P_TOP_AND_BOTTOM:1;/*0*/
-- uint32_t STEREO_1280X720_60P_TOP_AND_BOTTOM:1;/*1*/
-- uint32_t STEREO_1280X720_50P_TOP_AND_BOTTOM:1;/*2*/
-- uint32_t STEREO_1920X1080_24X2P_FRAME_ALTERNATE:1;/*3*/
-- uint32_t STEREO_1280X720_60X2P_FRAME_ALTERNATE:1;/*4*/
-- uint32_t STEREO_1280X720_30X2P_FRAME_ALTERNATE:1;/*5*/
-- uint32_t STEREO_1280X720_50X2P_FRAME_ALTERNATE:1;/*6*/
-- uint32_t STEREO_1280X720_25X2P_FRAME_ALTERNATE:1;/*7*/
-- uint32_t STEREO_1920X1080_24P_FRAME_PACKING:1;/* 8*/
-- uint32_t STEREO_1280X720_60P_FRAME_PACKING:1;/* 9*/
-- uint32_t STEREO_1280X720_30P_FRAME_PACKING:1;/*10*/
-- uint32_t STEREO_1280X720_50P_FRAME_PACKING:1;/*11*/
-- uint32_t STEREO_1280X720_25P_FRAME_PACKING:1;/*12*/
-- uint32_t RESERVED:19; /*[13-31]*/
-- } flags;
-- uint32_t raw;
--};
--
--union dal_remote_display_audio_bitmap {
-- struct {
-- uint32_t LPCM_44100HZ_16BITS_2_CHANNELS:1;/*0*/
-- uint32_t LPCM_48000HZ_16BITS_2_CHANNELS:1;/*1*/
-- uint32_t AAC_48000HZ_16BITS_2_CHANNELS:1;/*2*/
-- uint32_t AAC_48000HZ_16BITS_4_CHANNELS:1;/*3*/
-- uint32_t AAC_48000HZ_16BITS_6_CHANNELS:1;/*4*/
-- uint32_t AAC_48000HZ_16BITS_8_CHANNELS:1;/*5*/
-- uint32_t AC3_48000HZ_16BITS_2_CHANNELS:1;/*6*/
-- uint32_t AC3_48000HZ_16BITS_4_CHANNELS:1;/*7*/
-- uint32_t AC3_48000HZ_16BITS_6_CHANNELS:1;/*8*/
-- uint32_t RESERVED:23;/*[9-31]*/
-- } flags;
-- uint32_t raw;
--};
--
--struct dal_remote_display_receiver_capability {
-- union dal_remote_display_cea_mode_bitmap cea_mode;
-- union dal_remote_display_vesa_mode_bitmap vesa_mode;
-- union dal_remote_display_hh_mode_bitmap hh_mode;
-- union dal_remote_display_stereo_3d_mode_bitmap stereo_3d_mode;
-- union dal_remote_display_audio_bitmap audio;
--};
--
- #endif /* __DAL_TYPES_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/include/dcs_types.h b/drivers/gpu/drm/amd/dal/include/dcs_types.h
-index 8c65057..bccfd99 100644
---- a/drivers/gpu/drm/amd/dal/include/dcs_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/dcs_types.h
-@@ -48,35 +48,6 @@ struct drr_config {
- } support_method;
- };
-
--struct timing_limits {
-- uint32_t min_pixel_clock_in_khz;
-- uint32_t max_pixel_clock_in_khz;
--};
--
--struct vendor_product_id_info {
-- uint32_t manufacturer_id;
-- uint32_t product_id;
-- uint32_t serial_id;
-- uint32_t manufacture_week;
-- uint32_t manufacture_year;
--};
--
--struct display_range_limits {
-- uint32_t min_v_rate_hz;
-- uint32_t max_v_rate_hz;
-- uint32_t min_h_rate_khz;
-- uint32_t max_h_rateIn_khz;
-- uint32_t max_pix_clk_khz;
-- bool use_override;
--};
--
--struct monitor_user_select_limits {
-- bool use_ati_override;
-- uint32_t max_h_res;
-- uint32_t max_v_res;
-- uint32_t max_refresh_rate;
--};
--
- enum edid_screen_aspect_ratio {
- EDID_SCREEN_AR_UNKNOWN = 0,
- EDID_SCREEN_AR_PROJECTOR,
-@@ -90,17 +61,6 @@ enum edid_screen_aspect_ratio {
- EDID_SCREEN_AR_4X5
- };
-
--struct edid_screen_info {
-- enum edid_screen_aspect_ratio aspect_ratio;
-- uint32_t width;
-- uint32_t height;
--};
--
--struct display_characteristics {
-- uint8_t gamma;
-- uint8_t color_characteristics[NUM_OF_BYTE_EDID_COLOR_CHARACTERISTICS];
--};
--
- union cv_smart_dongle_modes {
- uint8_t all;
- struct cv_smart_dongle_switches {
-@@ -113,18 +73,6 @@ union cv_smart_dongle_modes {
- } switches;
- };
-
--struct cea_audio_mode {
-- uint8_t format_code; /* ucData[0] [6:3]*/
-- uint8_t channel_count; /* ucData[0] [2:0]*/
-- uint8_t sample_rate; /* ucData[1]*/
-- union {
-- uint8_t sample_size; /* for LPCM*/
-- /* for Audio Formats 2-8 (Max bit rate divided by 8 kHz)*/
-- uint8_t max_bit_rate;
-- uint8_t audio_codec_vendor_specific; /* for Audio Formats 9-15*/
-- };
--};
--
- union cea_speaker_allocation_data_block {
- struct {
- uint32_t FL_FR:1;
-@@ -138,23 +86,6 @@ union cea_speaker_allocation_data_block {
- uint32_t raw;
- };
-
--struct cea_colorimetry_data_block {
-- struct {
-- uint32_t XV_YCC601:1;
-- uint32_t XV_YCC709:1;
-- uint32_t S_YCC601:1;
-- uint32_t ADOBE_YCC601:1;
-- uint32_t ADOBE_RGB:1;
--
-- } flag;
-- struct {
-- uint32_t MD0:1;
-- uint32_t MD1:1;
-- uint32_t MD2:1;
-- uint32_t MD3:1;
-- } metadata_flag;
--};
--
- union cea_video_capability_data_block {
- struct {
- uint8_t S_CE0:1;
-@@ -184,121 +115,6 @@ enum cea_hdmi_vic {
- CEA_HDMI_VIC_4KX2K_24_SMPTE
- };
-
--struct cea_hdmi_vsdb_extended_caps {
-- uint32_t reserved;
-- uint32_t image_size;
-- enum stereo_3d_multi_presence stereo_3d_multi_present;
-- bool stereo_3d_present;
-- uint32_t hdmi_3d_len;
-- uint32_t hdmi_vic_len;
--};
--
--struct cea_vendor_specific_data_block {
--
-- uint32_t ieee_id;
--
-- struct commonent_phy {
-- uint32_t PHY_ADDR_A:4;
-- uint32_t PHY_ADDR_B:4;
-- uint32_t PHY_ADDR_C:4;
-- uint32_t PHY_ADDR_D:4;
-- } commonent_phy_addr;
--
-- struct byte6 {
-- uint32_t SUPPORTS_AI:1;
-- uint32_t DC_48BIT:1;
-- uint32_t DC_36BIT:1;
-- uint32_t DC_30BIT:1;
-- uint32_t DC_Y444:1;
-- uint32_t DVI_DUAL:1;
-- uint32_t RESERVED:2;
-- } byte6;/* link capabilities*/
-- bool byte6_valid;
--
-- uint32_t max_tmds_clk_mhz;
--
-- struct byte8 {
-- uint32_t LATENCY_FIELDS_PRESENT:1;
-- uint32_t ILATENCY_FIELDS_PRESENT:1;
-- uint32_t HDMI_VIDEO_PRESENT:1;
-- uint32_t RESERVED:1;
-- uint32_t CNC3_GAME:1;
-- uint32_t CNC2_CINEMA:1;
-- uint32_t CNC1_PHOTO:1;
-- uint32_t CNC0_GRAPHICS:1;
-- } byte8;
-- /*bit 6-7: latency flags to indicate valid latency fields*/
-- /*bit 5: support of additional video format capabilities*/
-- /* bit 0-3: flags indicating which content type is supported*/
-- uint32_t video_latency;
-- uint32_t audio_latency;
-- uint32_t i_video_latency;
-- uint32_t i_audio_latency;
--
-- struct cea_hdmi_vsdb_extended_caps hdmi_vsdb_extended_caps;
--
-- enum stereo_3d_multi_presence stereo_3d_multi_present;
--
-- struct {
-- bool FRAME_PACKING:1;
-- bool SIDE_BY_SIDE_HALF:1;
-- bool TOP_AND_BOTTOM:1;
-- } stereo_3d_all_support;
-- uint16_t stereo_3d_mask;
--
-- enum cea_hdmi_vic hdmi_vic[MAX_NUMBER_OF_HDMI_VSDB_VICS];
-- struct stereo_3d_extended_support {
-- struct {
-- bool FRAME_PACKING:1;
-- bool SIDE_BY_SIDE_HALF:1;
-- bool TOP_AND_BOTTOM:1;
-- } format;
-- uint32_t vic_index;
-- uint32_t value;
-- uint32_t size;
-- } stereo_3d_extended_support[MAX_NUMBER_OF_HDMI_VSDB_3D_EXTENDED_SUPPORT];
--};
--
--struct cea861_support {
--
-- uint32_t revision;
-- union {
-- struct {
-- uint32_t NATIVE_COUNT:4;
-- uint32_t BASE_AUDIO:1;
-- uint32_t YCRCB444:1;
-- uint32_t YCRCB422:1;
-- uint32_t UNDER_SCAN:1;
-- } features;
-- uint8_t raw_features;
-- };
--};
--
--struct dcs_customized_mode {
-- struct {
-- uint32_t READ_ONLY:1;
-- uint32_t ADD_BY_DRIVER:1;
-- uint32_t INTERLACED:1;
-- uint32_t BASE_MODE:1;
-- } flags;
-- struct dc_mode_info base_mode_info;
-- struct dc_mode_info customized_mode_info;
--};
--
--struct dcs_override_mode_timing {
-- /* possible timing standards, bit vector of TimingStandard*/
-- uint32_t possible_timing_standards;
-- /* indicate driver default timing is used , no override*/
-- bool use_driver_default_timing;
-- struct dc_mode_timing mode_timing;
--};
--
--struct dcs_override_mode_timing_list {
-- uint32_t max_num_overrides;
-- uint32_t num_overrides;
-- struct dcs_override_mode_timing mode_timings[1];
--};
--
- /* "interface type" is different from Signal Type because
- * an "interface type" can be driven by more than one Signal Type.
- * For example, INTERFACE_TYPE_DVI can be driven by
-@@ -397,10 +213,6 @@ enum pixel_encoding_mask {
- PIXEL_ENCODING_MASK_RGB = 0x04,
- };
-
--struct display_pixel_encoding_support {
-- uint32_t mask;
--};
--
- enum color_depth_index {
- COLOR_DEPTH_INDEX_UNKNOWN,
- COLOR_DEPTH_INDEX_666 = 0x01,
-@@ -412,17 +224,6 @@ enum color_depth_index {
- COLOR_DEPTH_INDEX_LAST = 0x40,
- };
-
--struct display_color_depth_support {
-- uint32_t mask;
-- bool deep_color_native_res_only;
--};
--
--struct display_color_and_pixel_support {
-- struct display_color_depth_support color_depth_support;
-- struct display_pixel_encoding_support pixel_encoding_support;
-- bool deep_color_y444_support;
--};
--
- enum dcs_packed_pixel_format {
- DCS_PACKED_PIXEL_FORMAT_NOT_PACKED = 0,
- DCS_PACKED_PIXEL_FORMAT_SPLIT_G70_B54_R70_B10 = 1,
-@@ -623,14 +424,6 @@ enum monitor_patch_type {
- MONITOR_PATCH_TYPE_SINGLE_MODE_PACKED_PIXEL
- };
-
--/* Single entry in the monitor table */
--struct monitor_patch_info {
-- enum monitor_manufacturer_id manufacturer_id;
-- enum monitor_product_id product_id;
-- enum monitor_patch_type type;
-- uint32_t param;
--};
--
- union dcs_monitor_patch_flags {
- struct {
- bool ERROR_CHECKSUM:1;
-@@ -676,67 +469,5 @@ union dcs_monitor_patch_flags {
- uint64_t raw;
- };
-
--struct dcs_edid_supported_max_bw {
-- uint32_t pix_clock_khz;
-- uint32_t bits_per_pixel;
--};
--
--struct dcs_stereo_3d_features {
-- struct {
--/* 3D Format supported by monitor (implies supported by driver)*/
-- uint32_t SUPPORTED:1;
--/* 3D Format supported on all timings
--(no need to check every timing for 3D support)*/
-- uint32_t ALL_TIMINGS:1;
--/* 3D Format supported in clone mode*/
-- uint32_t CLONE_MODE:1;
--/* Scaling allowed when driving 3D Format*/
-- uint32_t SCALING:1;
--/* Left and right images packed by SW within single frame*/
-- uint32_t SINGLE_FRAME_SW_PACKED:1;
-- } flags;
--};
--
--struct dcs_container_id {
-- /*128bit GUID in binary form*/
-- uint8_t guid[16];
-- /* 8 byte port ID -> ELD.PortID*/
-- uint32_t port_id[2];
-- /* 2 byte manufacturer name -> ELD.ManufacturerName*/
-- uint16_t manufacturer_name;
-- /* 2 byte product code -> ELD.ProductCode*/
-- uint16_t product_code;
--};
--
--struct dcs_display_tile {
--/*unique Id of Tiled Display. 0 - means display is not part in Tiled Display*/
-- uint64_t id;
-- uint32_t rows;/* size of Tiled Display in tiles*/
-- uint32_t cols;/* size of Tiled Display in tiles*/
-- uint32_t width;/* size of current Tile in pixels*/
-- uint32_t height;/* size of current Tile in pixels*/
-- uint32_t row;/* location of current Tile*/
-- uint32_t col;/* location of current Tile*/
-- struct {
-- /*in pixels*/
-- uint32_t left;
-- uint32_t right;
-- uint32_t top;
-- uint32_t bottom;
-- } bezel;/* bezel information of current tile*/
--
-- struct {
-- uint32_t SEPARATE_ENCLOSURE:1;
-- uint32_t BEZEL_INFO_PRESENT:1;
-- uint32_t CAN_SCALE:1;
-- } flags;
--
-- struct {
-- uint32_t manufacturer_id;
-- uint32_t product_id;
-- uint32_t serial_id;
-- } topology_id;
--};
--
- #endif /* __DAL_DCS_TYPES_H__ */
-
-diff --git a/drivers/gpu/drm/amd/dal/include/display_clock_interface.h b/drivers/gpu/drm/amd/dal/include/display_clock_interface.h
-index 317ce3b..55648ea 100644
---- a/drivers/gpu/drm/amd/dal/include/display_clock_interface.h
-+++ b/drivers/gpu/drm/amd/dal/include/display_clock_interface.h
-@@ -51,22 +51,6 @@ struct dc_scaling_params {
- uint32_t v_taps;
- };
-
--/*Display Request Mode (1 and 2 valid when scaler is OFF)*/
--enum display_request_mode {
-- REQUEST_ONLY_AT_EVERY_READ_POINTER_INCREMENT = 0,
-- REQUEST_WAITING_FOR_THE_FIRST_READ_POINTER_ONLY,
-- REQUEST_WITHOUT_WAITING_FOR_READ_POINTER
--};
--
--/* FBC minimum CompressionRatio*/
--enum fbc_compression_ratio {
-- FBC_COMPRESSION_NOT_USED = 0,
-- FBC_MINIMUM_COMPRESSION_RATIO_1 = 1,
-- FBC_MINIMUM_COMPRESSION_RATIO_2 = 2,
-- FBC_MINIMUM_COMPRESSION_RATIO_4 = 4,
-- FBC_MINIMUM_COMPRESSION_RATIO_8 = 8
--};
--
- /* VScalerEfficiency */
- enum v_scaler_efficiency {
- V_SCALER_EFFICIENCY_LB36BPP = 0,
-@@ -92,13 +76,6 @@ struct min_clock_params {
- bool line_buffer_prefetch_enabled;
- };
-
--/* Enumerations for Source selection of the Display clock */
--enum display_clock_source_select {
-- USE_PIXEL_CLOCK_PLL = 0,
-- USE_EXTERNAL_CLOCK,
-- USE_ENGINE_CLOCK
--};
--
- /* Result of Minimum System and Display clock calculations.
- * Minimum System clock and Display clock, source and path to be used
- * for Display clock*/
-diff --git a/drivers/gpu/drm/amd/dal/include/dmcu_types.h b/drivers/gpu/drm/amd/dal/include/dmcu_types.h
-index 1f3107d..00f9fa4 100644
---- a/drivers/gpu/drm/amd/dal/include/dmcu_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/dmcu_types.h
-@@ -144,44 +144,6 @@ union dmcu_psr_level {
- uint32_t u32all;
- };
-
--struct dmcu_config_data {
-- /* Command sent to DMCU. */
-- enum dmcu_action action;
-- /* PSR Level controls which HW blocks to power down during PSR active,
-- * and also other sequence modifications. */
-- union dmcu_psr_level psr_level;
-- /* To indicate that first changed frame from active state should not
-- * result in exit to inactive state, but instead perform an automatic
-- * single frame RFB update. */
-- bool rfb_update_auto_en;
-- /* Number of consecutive static frames to detect before entering PSR
-- * active state. */
-- uint32_t hyst_frames;
-- /* Partial frames before entering PSR active. Note this parameter is in
-- * units of 100 lines. i.e. Wait a value of 5 means wait 500 additional
-- * lines. */
-- uint32_t hyst_lines;
-- /* Number of repeated AUX retries before indicating failure to driver.
-- * In a working case, first attempt to write/read AUX should pass. */
-- uint32_t aux_repeat;
-- /* Additional delay after remote frame capture before continuing to
-- * power down. This is mainly for debug purposes to identify timing
-- * issues. */
-- uint32_t frame_delay;
-- /* Controls how long the delay of a wait loop is. It should be tuned
-- * to 1 us, and needs to be reconfigured every time DISPCLK changes. */
-- uint32_t wait_loop_num;
--};
--
--struct dmcu_output_data {
-- /* DMCU reply */
-- enum dmcu_output output;
-- /* The current PSR state. */
-- uint32_t psr_state;
-- /* The number of frames during PSR active state. */
-- uint32_t psr_count;
--};
--
- enum varibright_command {
- VARIBRIGHT_CMD_SET_VB_LEVEL = 0,
- VARIBRIGHT_CMD_USER_ENABLE,
-@@ -189,11 +151,4 @@ enum varibright_command {
- VARIBRIGHT_CMD_UNKNOWN
- };
-
--struct varibright_control {
-- enum varibright_command command;
-- uint8_t level;
-- bool enable;
-- bool activate;
--};
--
- #endif /* __DAL_DMCU_TYPES_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/include/dpcd_defs.h b/drivers/gpu/drm/amd/dal/include/dpcd_defs.h
-index 59677ed..e251cff 100644
---- a/drivers/gpu/drm/amd/dal/include/dpcd_defs.h
-+++ b/drivers/gpu/drm/amd/dal/include/dpcd_defs.h
-@@ -608,10 +608,6 @@ union audio_test_pattern_period {
- uint8_t raw;
- };
-
--struct audio_test_pattern_type {
-- uint8_t value;
--};
--
- union dpcd_training_pattern {
- struct {
- uint8_t TRAINING_PATTERN_SET:4;
-@@ -854,11 +850,6 @@ struct dp_device_vendor_id {
- uint8_t ieee_device_id[6];/*usually 6-byte ASCII name*/
- };
-
--struct dp_sink_hw_fw_revision {
-- uint8_t ieee_hw_rev;
-- uint8_t ieee_fw_rev[2];
--};
--
- /*DPCD register of DP receiver capability field bits-*/
- union edp_configuration_cap {
- struct {
-diff --git a/drivers/gpu/drm/amd/dal/include/grph_object_ctrl_defs.h b/drivers/gpu/drm/amd/dal/include/grph_object_ctrl_defs.h
-index 7df01ff..11b1b99 100644
---- a/drivers/gpu/drm/amd/dal/include/grph_object_ctrl_defs.h
-+++ b/drivers/gpu/drm/amd/dal/include/grph_object_ctrl_defs.h
-@@ -39,53 +39,6 @@
- * #####################################################
- */
-
--enum tv_standard {
-- TV_STANDARD_UNKNOWN = 0, /* direct HW (mmBIOS_SCRATCH_2) translation! */
-- TV_STANDARD_NTSC,
-- TV_STANDARD_NTSCJ,
-- TV_STANDARD_PAL,
-- TV_STANDARD_PALM,
-- TV_STANDARD_PALCN,
-- TV_STANDARD_PALN,
-- TV_STANDARD_PAL60,
-- TV_STANDARD_SECAM
--};
--
--enum cv_standard {
-- CV_STANDARD_UNKNOWN = 0x0000,
-- CV_STANDARD_HD_MASK = 0x0800, /* Flag mask HDTV output */
-- CV_STANDARD_SD_NTSC_MASK = 0x1000, /* Flag mask NTSC output */
-- CV_STANDARD_SD_NTSC_M, /* NTSC (North America) output 1001 */
-- CV_STANDARD_SD_NTSC_J, /* NTSC (Japan) output 1002 */
-- CV_STANDARD_SD_480I, /* SDTV 480i output 1003 */
-- CV_STANDARD_SD_480P, /* SDTV 480p output 1004 */
-- CV_STANDARD_HD_720_60P = 0x1800,/* HDTV 720/60p output 1800 */
-- CV_STANDARD_HD_1080_60I, /* HDTV 1080/60i output 1801 */
-- CV_STANDARD_SD_PAL_MASK = 0x2000,/* Flag mask PAL output */
-- CV_STANDARD_SD_PAL_B, /* PAL B output 2001 */
-- CV_STANDARD_SD_PAL_D, /* PAL D output 2002 */
-- CV_STANDARD_SD_PAL_G, /* PAL G output 2003 */
-- CV_STANDARD_SD_PAL_H, /* PAL H output 2004 */
-- CV_STANDARD_SD_PAL_I, /* PAL I output 2005 */
-- CV_STANDARD_SD_PAL_M, /* PAL M output 2006 */
-- CV_STANDARD_SD_PAL_N, /* PAL N output 2007 */
-- CV_STANDARD_SD_PAL_N_COMB, /* PAL Combination N output 2008 */
-- CV_STANDARD_SD_PAL_60, /* PAL 60 output (test mode) 2009 */
-- CV_STANDARD_SD_576I, /* SDTV 576i output 2010 */
-- CV_STANDARD_SD_576P, /* SDTV 576p output 2011 */
-- CV_STANDARD_HD_720_50P = 0x2800,/* HDTV 720/50p output 2800 */
-- CV_STANDARD_HD_1080_50I, /* HDTV 1080/50i output 2801 */
-- CV_STANDARD_SD_SECAM_MASK = 0x4000, /* Flag mask SECAM output */
-- CV_STANDARD_SD_SECAM_B, /* SECAM B output 4001 */
-- CV_STANDARD_SD_SECAM_D, /* SECAM D output 4002 */
-- CV_STANDARD_SD_SECAM_G, /* SECAM G output 4003 */
-- CV_STANDARD_SD_SECAM_H, /* SECAM H output 4004 */
-- CV_STANDARD_SD_SECAM_K, /* SECAM K output 4005 */
-- CV_STANDARD_SD_SECAM_K1, /* SECAM K1 output 4006 */
-- CV_STANDARD_SD_SECAM_L, /* SECAM L output 4007 */
-- CV_STANDARD_SD_SECAM_L1 /* SECAM L1 output 4009 */
--};
--
- enum display_output_bit_depth {
- PANEL_UNDEFINE = 0,
- PANEL_6BIT_COLOR = 1,
-@@ -253,11 +206,6 @@ union tv_standard_support {
- } bits;
- };
-
--struct analog_tv_info {
-- union tv_standard_support tv_suppported;
-- union tv_standard_support tv_boot_up_default;
--};
--
- struct step_and_delay_info {
- uint32_t step;
- uint32_t delay;
-@@ -533,13 +481,6 @@ union optimization_flags {
-
- /* Bitvector and bitfields of performance measurements
- #IMPORTANT# Keep bitfields match bitvector! */
--enum perf_measure {
-- PERF_MEASURE_ADAPTER_POWER_STATE = 0x1,
-- PERF_MEASURE_DISPLAY_POWER_STATE = 0x2,
-- PERF_MEASURE_SET_MODE_SEQ = 0x4,
-- PERF_MEASURE_DETECT_AT_RESUME = 0x8,
-- PERF_MEASURE_MEMORY_READ_CONTROL = 0x10,
--};
-
- union perf_measure_flags {
- struct {
-@@ -586,9 +527,5 @@ struct panel_backlight_boundaries {
- uint32_t max_signal_level;
- };
-
--struct panel_backlight_default_levels {
-- uint32_t ac_level_percentage;
-- uint32_t dc_level_percentage;
--};
-
- #endif
-diff --git a/drivers/gpu/drm/amd/dal/include/grph_object_defs.h b/drivers/gpu/drm/amd/dal/include/grph_object_defs.h
-index a7c42f0..371b22b 100644
---- a/drivers/gpu/drm/amd/dal/include/grph_object_defs.h
-+++ b/drivers/gpu/drm/amd/dal/include/grph_object_defs.h
-@@ -221,28 +221,6 @@ struct static_screen_events {
- * ***************************************************************
- */
-
--/* GPIO/Register access sequences */
--enum io_register_sequence {
-- /* GLSync sequences to access SwapReady & SwapRequest
-- GPIOs - GLSync Connector parameter */
-- IO_REG_SEQUENCE_SWAPREADY_SET = 0,
-- IO_REG_SEQUENCE_SWAPREADY_RESET,
-- IO_REG_SEQUENCE_SWAPREADY_READ,
-- IO_REG_SEQUENCE_SWAPREQUEST_SET,
-- IO_REG_SEQUENCE_SWAPREQUEST_RESET,
-- IO_REG_SEQUENCE_SWAPREQUEST_READ,
--
-- /* Frame synchronization start/stop - display index parameter */
-- IO_REG_SEQUENCE_FRAMELOCK_STOP,
-- IO_REG_SEQUENCE_FRAMELOCK_START,
--
-- /* Flip lock/unlock - GLSync Connector parameter */
-- IO_REG_SEQUENCE_GLOBALSWAP_LOCK,
-- IO_REG_SEQUENCE_GLOBALSWAP_UNLOCK,
--
-- IO_REG_SEQUENCEENUM_MAX
--};
--
- #define IO_REGISTER_SEQUENCE_MAX_LENGTH 5
-
- /*
-@@ -274,54 +252,11 @@ enum io_register_sequence {
- * security consideration.
- */
-
--/*
-- * The generic sequence to program/access registers or GPIOs.
-- * There could be 2 types of sequences - read and write.
-- * Read sequence may have 0 or more writes and in the end one read
-- * Write sequence may have 1 or more writes.
-- */
--struct io_reg_sequence {
-- /* Ordered array of register to program */
-- struct {
-- /* Offset of memory mapped register or GPIO */
-- uint32_t register_offset;
-- /* Mask to use at AND operation (Mandatory, comes
-- before OR operation) */
-- uint32_t and_mask;
-- union {
-- /* Mask to use at OR operation (For write
-- sequence only, comes after AND operation) */
-- uint32_t or_mask;
-- /* Number of bits to shift to get the actual value
-- (For read sequence only, comes after AND operation) */
-- uint32_t bit_shift;
-- };
-- } io_registers[IO_REGISTER_SEQUENCE_MAX_LENGTH];
--
-- uint32_t steps_num; /* Total number of r/w steps in the sequence */
--};
--
- /* Sequence ID - uniqly defines sequence on single adapter */
--struct io_reg_sequence_id {
-- enum io_register_sequence sequence; /* Sequence enumeration Index/ID */
-- union {
-- /* Refers to object to which the sequence applies.*/
-- uint32_t index;
-- uint32_t display_index;
-- uint32_t controller_index;
-- uint32_t glsync_connector_index;
-- };
--};
-
- struct fbc_info {
- bool fbc_enable;
- bool lpt_enable;
- };
-
--/* Event to request TM change IRQ registration state */
--struct hotplug_irq_data {
-- bool disable;
-- struct graphics_object_id connector;
--};
--
- #endif
-diff --git a/drivers/gpu/drm/amd/dal/include/hw_sequencer_interface.h b/drivers/gpu/drm/amd/dal/include/hw_sequencer_interface.h
-index 4238eb0..81b4b93 100644
---- a/drivers/gpu/drm/amd/dal/include/hw_sequencer_interface.h
-+++ b/drivers/gpu/drm/amd/dal/include/hw_sequencer_interface.h
-@@ -51,21 +51,6 @@ struct hws_init_data {
-
- /* TODO: below is three almost equal structures.
- * We should decide what to do with them */
--struct blank_stream_param {
-- struct display_path *display_path;
-- uint32_t link_idx;
-- struct hw_crtc_timing timing;
-- struct link_settings link_settings;
--};
--
--struct enable_stream_param {
-- struct display_path *display_path;
-- uint32_t link_idx;
-- struct hw_crtc_timing timing;
-- struct link_settings link_settings;
--
-- const struct hw_path_mode *path_mode;
--};
-
- struct enable_link_param {
- struct display_path *display_path;
-diff --git a/drivers/gpu/drm/amd/dal/include/hw_sequencer_types.h b/drivers/gpu/drm/amd/dal/include/hw_sequencer_types.h
-index 60dcf81..511caf4 100644
---- a/drivers/gpu/drm/amd/dal/include/hw_sequencer_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/hw_sequencer_types.h
-@@ -41,18 +41,6 @@ enum {
- HW_OTHER_PIPE_INDEX = 1
- };
-
--struct hw_view_port_adjustment {
-- int32_t start_adjustment;
-- int32_t width;
--
-- enum controller_id controller_id;
--};
--
--struct hw_view_port_adjustments {
-- uint32_t view_ports_num;
-- struct hw_view_port_adjustment adjustments[HW_MAX_NUM_VIEWPORTS];
--};
--
- /* Timing standard */
- enum hw_timing_standard {
- HW_TIMING_STANDARD_UNDEFINED,
-@@ -156,12 +144,6 @@ struct hw_crtc_timing {
- } flags;
- };
-
--struct hw_scaling_info {
-- struct view src;
-- struct view dst;
-- enum signal_type signal;
--};
--
- enum hw_color_space {
- HW_COLOR_SPACE_UNKNOWN = 0,
- HW_COLOR_SPACE_SRGB_FULL_RANGE,
-@@ -223,19 +205,6 @@ enum hw_dithering_options {
- HW_DITHERING_OPTION_DISABLE
- };
-
--struct hw_stereo_mixer_params {
-- bool sub_sampling;
-- bool single_pipe;
--};
--
--struct hw_action_flags {
-- uint32_t RESYNC_PATH:1;
-- uint32_t TIMING_CHANGED:1;
-- uint32_t PIXEL_ENCODING_CHANGED:1;
-- uint32_t GAMUT_CHANGED:1;
-- uint32_t TURN_OFF_VCC:1;
--};
--
- enum hw_sync_request {
- HW_SYNC_REQUEST_NONE = 0,
- HW_SYNC_REQUEST_SET_INTERPATH,
-@@ -247,12 +216,6 @@ enum hw_sync_request {
- HW_SYNC_REQUEST_SET_STEREO3D
- };
-
--struct hw_sync_info {
-- enum hw_sync_request sync_request;
-- uint32_t target_pixel_clock; /* in KHz */
-- enum sync_source sync_source;
--};
--
- /* TODO hw_info_frame and hw_info_packet structures are same as in encoder
- * merge it*/
- struct hw_info_packet {
-diff --git a/drivers/gpu/drm/amd/dal/include/video_csc_types.h b/drivers/gpu/drm/amd/dal/include/video_csc_types.h
-index 85619fc..96b4ac9 100644
---- a/drivers/gpu/drm/amd/dal/include/video_csc_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/video_csc_types.h
-@@ -28,46 +28,6 @@
-
- #include "video_gamma_types.h"
-
--enum ovl_alpha_blending_mode {
-- OVL_ALPHA_PER_PIXEL_GRPH_ALPHA_MODE = 0,
-- OVL_ALPHA_PER_PIXEL_OVL_ALPHA_MODE
--};
--
--enum ovl_surface_format {
-- OVL_SURFACE_FORMAT_UNKNOWN = 0,
-- OVL_SURFACE_FORMAT_YUY2,
-- OVL_SURFACE_FORMAT_UYVY,
-- OVL_SURFACE_FORMAT_RGB565,
-- OVL_SURFACE_FORMAT_RGB555,
-- OVL_SURFACE_FORMAT_RGB32,
-- OVL_SURFACE_FORMAT_YUV444,
-- OVL_SURFACE_FORMAT_RGB32_2101010
--};
--
--struct ovl_color_adjust_option {
-- uint32_t ALLOW_OVL_RGB_ADJUST:1;
-- uint32_t ALLOW_OVL_TEMPERATURE:1;
-- uint32_t FULL_RANGE:1; /* 0 for limited range it'is default for YUV */
-- uint32_t OVL_MATRIX:1;
-- uint32_t RESERVED:28;
--};
--
--struct overlay_adjust_item {
-- int32_t adjust; /* InInteger */
-- int32_t adjust_divider;
--};
--
--enum overlay_csc_adjust_type {
-- OVERLAY_CSC_ADJUST_TYPE_BYPASS = 0,
-- OVERLAY_CSC_ADJUST_TYPE_HW, /* without adjustments */
-- OVERLAY_CSC_ADJUST_TYPE_SW /* use adjustments */
--};
--
--enum overlay_gamut_adjust_type {
-- OVERLAY_GAMUT_ADJUST_TYPE_BYPASS = 0,
-- OVERLAY_GAMUT_ADJUST_TYPE_SW /* use adjustments */
--};
--
- #define TEMPERATURE_MATRIX_SIZE 9
- #define MAXTRIX_SIZE TEMPERATURE_MAXTRIX_SIZE
- #define MAXTRIX_SIZE_WITH_OFFSET 12
-diff --git a/drivers/gpu/drm/amd/dal/include/video_gamma_types.h b/drivers/gpu/drm/amd/dal/include/video_gamma_types.h
-index e910711..1e249ac 100644
---- a/drivers/gpu/drm/amd/dal/include/video_gamma_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/video_gamma_types.h
-@@ -29,13 +29,6 @@
- #include "set_mode_types.h"
- #include "gamma_types.h"
-
--enum overlay_gamma_adjust {
-- OVERLAY_GAMMA_ADJUST_BYPASS,
-- OVERLAY_GAMMA_ADJUST_HW, /* without adjustments */
-- OVERLAY_GAMMA_ADJUST_SW /* use adjustments */
--
--};
--
- union video_gamma_flag {
- struct {
- uint32_t CONFIG_IS_CHANGED:1;
-@@ -44,13 +37,4 @@ union video_gamma_flag {
- uint32_t u_all;
- };
-
--struct overlay_gamma_parameters {
-- union video_gamma_flag flag;
-- int32_t ovl_gamma_cont;
-- enum overlay_gamma_adjust adjust_type;
-- enum pixel_format desktop_surface;
--
-- /* here we grow with parameters if necessary */
--};
--
- #endif
---
-2.7.4
-
generated by cgit 1.2.3-korg (git 2.39.0) at 2024-04-16 19:23:40 +0000