diff options
Diffstat (limited to 'common/recipes-kernel/linux/files/0915-drm-amdgpu-atom-add-support-for-new-UNIPHYTransmitte.patch')
-rw-r--r-- | common/recipes-kernel/linux/files/0915-drm-amdgpu-atom-add-support-for-new-UNIPHYTransmitte.patch | 94 |
1 files changed, 94 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/files/0915-drm-amdgpu-atom-add-support-for-new-UNIPHYTransmitte.patch b/common/recipes-kernel/linux/files/0915-drm-amdgpu-atom-add-support-for-new-UNIPHYTransmitte.patch new file mode 100644 index 00000000..dc2fde6e --- /dev/null +++ b/common/recipes-kernel/linux/files/0915-drm-amdgpu-atom-add-support-for-new-UNIPHYTransmitte.patch @@ -0,0 +1,94 @@ +From 615383736e7c94eeaa266c7aeeabef70f48411ed Mon Sep 17 00:00:00 2001 +From: Alex Deucher <alexander.deucher@amd.com> +Date: Thu, 15 Oct 2015 15:08:30 -0400 +Subject: [PATCH 0915/1110] drm/amdgpu/atom: add support for new + UNIPHYTransmitterContol cmd table +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +New uniphy transmitter setup table for elm/baf. + +Reviewed-by: Christian König <christian.koenig@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/atombios_encoders.c | 51 +++++++++++++++++++++++++- + 1 file changed, 50 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c +index 3481962..48b6bd6 100644 +--- a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c ++++ b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c +@@ -756,11 +756,12 @@ union dig_transmitter_control { + DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3; + DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4; + DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5; ++ DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_6 v6; + }; + + void + amdgpu_atombios_encoder_setup_dig_transmitter(struct drm_encoder *encoder, int action, +- uint8_t lane_num, uint8_t lane_set) ++ uint8_t lane_num, uint8_t lane_set) + { + struct drm_device *dev = encoder->dev; + struct amdgpu_device *adev = dev->dev_private; +@@ -1112,6 +1113,54 @@ amdgpu_atombios_encoder_setup_dig_transmitter(struct drm_encoder *encoder, int a + args.v5.ucDigEncoderSel = 1 << dig_encoder; + args.v5.ucDPLaneSet = lane_set; + break; ++ case 6: ++ args.v6.ucAction = action; ++ if (is_dp) ++ args.v6.ulSymClock = cpu_to_le32(dp_clock / 10); ++ else ++ args.v6.ulSymClock = cpu_to_le32(amdgpu_encoder->pixel_clock / 10); ++ ++ switch (amdgpu_encoder->encoder_id) { ++ case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: ++ if (dig->linkb) ++ args.v6.ucPhyId = ATOM_PHY_ID_UNIPHYB; ++ else ++ args.v6.ucPhyId = ATOM_PHY_ID_UNIPHYA; ++ break; ++ case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: ++ if (dig->linkb) ++ args.v6.ucPhyId = ATOM_PHY_ID_UNIPHYD; ++ else ++ args.v6.ucPhyId = ATOM_PHY_ID_UNIPHYC; ++ break; ++ case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: ++ if (dig->linkb) ++ args.v6.ucPhyId = ATOM_PHY_ID_UNIPHYF; ++ else ++ args.v6.ucPhyId = ATOM_PHY_ID_UNIPHYE; ++ break; ++ case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: ++ args.v6.ucPhyId = ATOM_PHY_ID_UNIPHYG; ++ break; ++ } ++ if (is_dp) ++ args.v6.ucLaneNum = dp_lane_count; ++ else if (amdgpu_dig_monitor_is_duallink(encoder, amdgpu_encoder->pixel_clock)) ++ args.v6.ucLaneNum = 8; ++ else ++ args.v6.ucLaneNum = 4; ++ args.v6.ucConnObjId = connector_object_id; ++ if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) ++ args.v6.ucDPLaneSet = lane_set; ++ else ++ args.v6.ucDigMode = amdgpu_atombios_encoder_get_encoder_mode(encoder); ++ ++ if (hpd_id == AMDGPU_HPD_NONE) ++ args.v6.ucHPDSel = 0; ++ else ++ args.v6.ucHPDSel = hpd_id + 1; ++ args.v6.ucDigEncoderSel = 1 << dig_encoder; ++ break; + default: + DRM_ERROR("Unknown table version %d, %d\n", frev, crev); + break; +-- +2.7.4 + |