diff options
Diffstat (limited to 'common/recipes-kernel/linux/files/0913-drm-amdgpu-atom-add-support-for-new-SetPixelClock-ta.patch')
-rw-r--r-- | common/recipes-kernel/linux/files/0913-drm-amdgpu-atom-add-support-for-new-SetPixelClock-ta.patch | 101 |
1 files changed, 0 insertions, 101 deletions
diff --git a/common/recipes-kernel/linux/files/0913-drm-amdgpu-atom-add-support-for-new-SetPixelClock-ta.patch b/common/recipes-kernel/linux/files/0913-drm-amdgpu-atom-add-support-for-new-SetPixelClock-ta.patch deleted file mode 100644 index 4adfb3b3..00000000 --- a/common/recipes-kernel/linux/files/0913-drm-amdgpu-atom-add-support-for-new-SetPixelClock-ta.patch +++ /dev/null @@ -1,101 +0,0 @@ -From 29c91eca599b8d27ff614a0d8979b3a1bf6abd65 Mon Sep 17 00:00:00 2001 -From: Alex Deucher <alexander.deucher@amd.com> -Date: Thu, 15 Oct 2015 02:05:31 -0400 -Subject: [PATCH 0913/1110] drm/amdgpu/atom: add support for new SetPixelClock - table -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -New version of the SetPixelClock table for elm/baf. The -new table calculates the pll dividers and handles spread -spectrum calculations and setup. - -Reviewed-by: Christian König <christian.koenig@amd.com> -Signed-off-by: Alex Deucher <alexander.deucher@amd.com> -Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> ---- - drivers/gpu/drm/amd/amdgpu/atombios_crtc.c | 53 +++++++++++++++++++++++------- - 1 file changed, 41 insertions(+), 12 deletions(-) - -diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_crtc.c b/drivers/gpu/drm/amd/amdgpu/atombios_crtc.c -index bd6c530..49a39b1 100644 ---- a/drivers/gpu/drm/amd/amdgpu/atombios_crtc.c -+++ b/drivers/gpu/drm/amd/amdgpu/atombios_crtc.c -@@ -461,6 +461,7 @@ union set_pixel_clock { - PIXEL_CLOCK_PARAMETERS_V3 v3; - PIXEL_CLOCK_PARAMETERS_V5 v5; - PIXEL_CLOCK_PARAMETERS_V6 v6; -+ PIXEL_CLOCK_PARAMETERS_V7 v7; - }; - - /* on DCE5, make sure the voltage is high enough to support the -@@ -566,18 +567,18 @@ static bool is_pixel_clock_source_from_pll(u32 encoder_mode, int pll_id) - } - - void amdgpu_atombios_crtc_program_pll(struct drm_crtc *crtc, -- u32 crtc_id, -- int pll_id, -- u32 encoder_mode, -- u32 encoder_id, -- u32 clock, -- u32 ref_div, -- u32 fb_div, -- u32 frac_fb_div, -- u32 post_div, -- int bpc, -- bool ss_enabled, -- struct amdgpu_atom_ss *ss) -+ u32 crtc_id, -+ int pll_id, -+ u32 encoder_mode, -+ u32 encoder_id, -+ u32 clock, -+ u32 ref_div, -+ u32 fb_div, -+ u32 frac_fb_div, -+ u32 post_div, -+ int bpc, -+ bool ss_enabled, -+ struct amdgpu_atom_ss *ss) - { - struct drm_device *dev = crtc->dev; - struct amdgpu_device *adev = dev->dev_private; -@@ -695,6 +696,34 @@ void amdgpu_atombios_crtc_program_pll(struct drm_crtc *crtc, - args.v6.ucEncoderMode = encoder_mode; - args.v6.ucPpll = pll_id; - break; -+ case 7: -+ args.v7.ulPixelClock = cpu_to_le32(clock * 10); /* 100 hz units */ -+ args.v7.ucMiscInfo = 0; -+ if ((encoder_mode == ATOM_ENCODER_MODE_DVI) && -+ (clock > 165000)) -+ args.v7.ucMiscInfo |= PIXEL_CLOCK_V7_MISC_DVI_DUALLINK_EN; -+ args.v7.ucCRTC = crtc_id; -+ if (encoder_mode == ATOM_ENCODER_MODE_HDMI) { -+ switch (bpc) { -+ case 8: -+ default: -+ args.v7.ucDeepColorRatio = PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_DIS; -+ break; -+ case 10: -+ args.v7.ucDeepColorRatio = PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_5_4; -+ break; -+ case 12: -+ args.v7.ucDeepColorRatio = PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_3_2; -+ break; -+ case 16: -+ args.v7.ucDeepColorRatio = PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_2_1; -+ break; -+ } -+ } -+ args.v7.ucTransmitterID = encoder_id; -+ args.v7.ucEncoderMode = encoder_mode; -+ args.v7.ucPpll = pll_id; -+ break; - default: - DRM_ERROR("Unknown table version %d %d\n", frev, crev); - return; --- -2.7.4 - |