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-rw-r--r--common/recipes-kernel/linux/files/0873-drm-amd-dal-Use-usleep-for-microsecond-sleep.patch600
1 files changed, 600 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/files/0873-drm-amd-dal-Use-usleep-for-microsecond-sleep.patch b/common/recipes-kernel/linux/files/0873-drm-amd-dal-Use-usleep-for-microsecond-sleep.patch
new file mode 100644
index 00000000..35dabb79
--- /dev/null
+++ b/common/recipes-kernel/linux/files/0873-drm-amd-dal-Use-usleep-for-microsecond-sleep.patch
@@ -0,0 +1,600 @@
+From 62a3999b85f0102a285a341b6121b3063079920f Mon Sep 17 00:00:00 2001
+From: Harry Wentland <harry.wentland@amd.com>
+Date: Sat, 27 Feb 2016 16:04:29 -0500
+Subject: [PATCH 0873/1110] drm/amd/dal: Use usleep for microsecond sleep
+
+Signed-off-by: Harry Wentland <harry.wentland@amd.com>
+Acked-by: Harry Wentland<harry.wentland@amd.com>
+---
+ .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_services.c | 5 ---
+ .../amd/dal/dc/audio/dce110/hw_ctx_audio_dce110.c | 2 +-
+ drivers/gpu/drm/amd/dal/dc/core/dc.c | 1 -
+ drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c | 2 +-
+ drivers/gpu/drm/amd/dal/dc/core/dc_target.c | 1 -
+ .../drm/amd/dal/dc/dce100/dce100_hw_sequencer.c | 2 +-
+ .../gpu/drm/amd/dal/dc/dce110/dce110_compressor.c | 2 +-
+ .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c | 2 +-
+ .../drm/amd/dal/dc/dce110/dce110_link_encoder.c | 4 +--
+ .../gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c | 4 +--
+ .../drm/amd/dal/dc/dce110/dce110_opp_regamma_v.c | 2 +-
+ .../drm/amd/dal/dc/dce110/dce110_stream_encoder.c | 6 ++--
+ .../drm/amd/dal/dc/dce110/dce110_transform_scl.c | 2 +-
+ .../gpu/drm/amd/dal/dc/dce80/dce80_compressor.c | 2 +-
+ .../gpu/drm/amd/dal/dc/dce80/dce80_hw_sequencer.c | 2 +-
+ drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.c | 2 +-
+ .../drm/amd/dal/dc/dce80/dce80_stream_encoder.c | 6 ++--
+ .../gpu/drm/amd/dal/dc/dce80/dce80_transform_scl.c | 2 +-
+ drivers/gpu/drm/amd/dal/dc/dm_services.h | 2 --
+ drivers/gpu/drm/amd/dal/dc/i2caux/aux_engine.c | 6 ++--
+ .../amd/dal/dc/i2caux/dce110/aux_engine_dce110.c | 6 ++--
+ .../drm/amd/dal/dc/i2caux/dce80/aux_engine_dce80.c | 2 +-
+ drivers/gpu/drm/amd/dal/dc/i2caux/i2c_engine.c | 2 +-
+ drivers/gpu/drm/amd/dal/dc/i2caux/i2c_hw_engine.c | 2 +-
+ drivers/gpu/drm/amd/dal/dc/i2caux/i2c_sw_engine.c | 40 +++++++++++-----------
+ 25 files changed, 50 insertions(+), 59 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_services.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_services.c
+index d0a17af..d89f9c4 100644
+--- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_services.c
++++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_services.c
+@@ -48,11 +48,6 @@ void dm_sleep_in_milliseconds(struct dc_context *ctx, uint32_t milliseconds)
+ usleep_range(milliseconds*1000, milliseconds*1000+1);
+ }
+
+-void dm_delay_in_microseconds(struct dc_context *ctx, uint32_t microseconds)
+-{
+- udelay(microseconds);
+-}
+-
+ /******************************************************************************
+ * IRQ Interfaces.
+ *****************************************************************************/
+diff --git a/drivers/gpu/drm/amd/dal/dc/audio/dce110/hw_ctx_audio_dce110.c b/drivers/gpu/drm/amd/dal/dc/audio/dce110/hw_ctx_audio_dce110.c
+index 64d3dbf..d8a674d 100644
+--- a/drivers/gpu/drm/amd/dal/dc/audio/dce110/hw_ctx_audio_dce110.c
++++ b/drivers/gpu/drm/amd/dal/dc/audio/dce110/hw_ctx_audio_dce110.c
+@@ -891,7 +891,7 @@ static void enable_afmt_clock(
+ */
+ do {
+ /* Wait for 1us between subsequent register reads.*/
+- dm_delay_in_microseconds(hw_ctx->ctx, 1);
++ udelay(1);
+ value = dm_read_reg(hw_ctx->ctx,
+ mmAFMT_CNTL + engine_offs);
+ } while (get_reg_field_value(value,
+diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
+index d547fb9..4a52d43 100644
+--- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
+@@ -907,7 +907,6 @@ bool dc_commit_surfaces_to_target(
+ new_surface_count,
+ dc_target);
+
+-
+ if (!resource_attach_surfaces_to_context(
+ new_surfaces, new_surface_count, dc_target, context)) {
+ BREAK_TO_DEBUGGER();
+diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
+index 619e910..48e3e4d 100644
+--- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
++++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
+@@ -79,7 +79,7 @@ static void wait_for_training_aux_rd_interval(
+ training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL * 4000;
+ }
+
+- dm_delay_in_microseconds(link->ctx, default_wait_in_micro_secs);
++ udelay(default_wait_in_micro_secs);
+
+ dal_logger_write(link->ctx->logger,
+ LOG_MAJOR_HW_TRACE,
+diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_target.c b/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
+index 44fe442..53bb64b 100644
+--- a/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
++++ b/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
+@@ -124,7 +124,6 @@ struct dc_target *dc_create_target_for_streams(
+
+ return &target->protected.public;
+
+-
+ target_alloc_fail:
+ return NULL;
+ }
+diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c
+index c759081..0c17aa1 100644
+--- a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c
+@@ -213,7 +213,7 @@ static bool dce100_pipe_control_lock(
+ break;
+
+ counter++;
+- dm_delay_in_microseconds(ctx, delay_us);
++ udelay(delay_us);
+ }
+
+ if (counter == counter_limit) {
+diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_compressor.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_compressor.c
+index 5b55ce8..7a647cd 100644
+--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_compressor.c
++++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_compressor.c
+@@ -317,7 +317,7 @@ static void wait_for_fbc_state_changed(
+ FBC_STATUS,
+ FBC_ENABLE_STATUS) == enabled)
+ break;
+- dm_delay_in_microseconds(cp110->base.ctx, 10);
++ udelay(10);
+ counter++;
+ }
+
+diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
+index 1b49201..e6d1c3a 100644
+--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
+@@ -323,7 +323,7 @@ static bool dce110_pipe_control_lock(
+ break;
+
+ counter++;
+- dm_delay_in_microseconds(ctx, delay_us);
++ udelay(delay_us);
+ }
+
+ if (counter == counter_limit) {
+diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
+index 9efed4f..71ef1de 100644
+--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
++++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
+@@ -1738,7 +1738,7 @@ void dce110_link_encoder_update_mst_stream_allocation_table(
+ * after this bit is cleared */
+
+ do {
+- dm_delay_in_microseconds(ctx, 10);
++ udelay(10);
+
+ value0 = dm_read_reg(ctx,
+ LINK_REG(DP_MSE_SAT_UPDATE));
+@@ -1889,7 +1889,7 @@ void dce110_link_encoder_set_lcd_backlight_level(
+ BL_PWM_GRP1_REG_UPDATE_PENDING))
+ break;
+
+- dm_delay_in_microseconds(ctx, 10);
++ udelay(10);
+ }
+ }
+
+diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
+index 077278d..e7fc5bd 100644
+--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
++++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
+@@ -744,7 +744,7 @@ void dce110_allocate_mem_input(
+ if (field)
+ break;
+
+- dm_delay_in_microseconds(mi->ctx, retry_delay);
++ udelay(retry_delay);
+ retry_count--;
+
+ } while (retry_count > 0);
+@@ -815,7 +815,7 @@ static void deallocate_dmif_buffer_helper(
+
+ do {
+ value = dm_read_reg(ctx, mmPIPE0_DMIF_BUFFER_CONTROL + offset);
+- dm_delay_in_microseconds(ctx, 10);
++ udelay(10);
+ count--;
+ } while (count > 0 &&
+ !get_reg_field_value(
+diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma_v.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma_v.c
+index 0004c9e..3b3a917 100644
+--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma_v.c
++++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma_v.c
+@@ -78,7 +78,7 @@ static void power_on_lut(struct output_pixel_processor *opp,
+ COL_MAN_GAMMA_CORR_MEM_PWR_DIS))
+ break;
+
+- dm_delay_in_microseconds(opp->ctx, 2);
++ udelay(2);
+ }
+ }
+
+diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.c
+index 2107309..dcca860 100644
+--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.c
++++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.c
+@@ -682,7 +682,7 @@ void dce110_stream_encoder_set_mst_bandwidth(
+ DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK))
+ break;
+
+- dm_delay_in_microseconds(ctx, 10);
++ udelay(10);
+
+ ++retries;
+ } while (retries < DP_MST_UPDATE_MAX_RETRY);
+@@ -1017,7 +1017,7 @@ void dce110_stream_encoder_dp_blank(
+ DP_VID_STREAM_STATUS))
+ break;
+
+- dm_delay_in_microseconds(ctx, 10);
++ udelay(10);
+
+ ++retries;
+ } while (retries < max_retries);
+@@ -1102,7 +1102,7 @@ void dce110_stream_encoder_dp_unblank(
+ /* wait 100us for DIG/DP logic to prime
+ * (i.e. a few video lines)
+ */
+- dm_delay_in_microseconds(ctx, 100);
++ udelay(100);
+
+ /* the hardware would start sending video at the start of the next DP
+ * frame (i.e. rising edge of the vblank).
+diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_scl.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_scl.c
+index f8376f8..65f9e01 100644
+--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_scl.c
++++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_scl.c
+@@ -244,7 +244,7 @@ static void program_filter(
+ DCFE_MEM_PWR_STATUS,
+ SCL_COEFF_MEM_PWR_STATE);
+ i++)
+- dm_delay_in_microseconds(xfm110->base.ctx, 1);
++ udelay(1);
+
+ ASSERT(i < 10);
+
+diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_compressor.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_compressor.c
+index d7d0088..dc008e7 100644
+--- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_compressor.c
++++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_compressor.c
+@@ -329,7 +329,7 @@ static void wait_for_fbc_state_changed(
+ FBC_STATUS,
+ FBC_ENABLE_STATUS) == enabled)
+ break;
+- dm_delay_in_microseconds(cp80->base.ctx, 10);
++ udelay(10);
+ counter++;
+ }
+
+diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_hw_sequencer.c
+index ef55de3..caec585 100644
+--- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_hw_sequencer.c
+@@ -201,7 +201,7 @@ static bool dce80_pipe_control_lock(
+ break;
+
+ counter++;
+- dm_delay_in_microseconds(ctx, delay_us);
++ udelay(delay_us);
+ }
+
+ if (counter == counter_limit) {
+diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.c
+index d9bc223..c73c118 100644
+--- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.c
++++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.c
+@@ -137,7 +137,7 @@ static void allocate_mem_input(
+ if (field)
+ break;
+
+- dm_delay_in_microseconds(mi->ctx, retry_delay);
++ udelay(retry_delay);
+ retry_count--;
+
+ } while (retry_count > 0);
+diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_stream_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_stream_encoder.c
+index d45a1e4..f0a7ee1 100644
+--- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_stream_encoder.c
++++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_stream_encoder.c
+@@ -658,7 +658,7 @@ void dce80_stream_encoder_set_mst_bandwidth(
+ DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK))
+ break;
+
+- dm_delay_in_microseconds(ctx, 10);
++ udelay(10);
+
+ ++retries;
+ } while (retries < DP_MST_UPDATE_MAX_RETRY);
+@@ -998,7 +998,7 @@ void dce80_stream_encoder_dp_blank(
+ DP_VID_STREAM_STATUS))
+ break;
+
+- dm_delay_in_microseconds(ctx, 10);
++ udelay(10);
+
+ ++retries;
+ } while (retries < max_retries);
+@@ -1083,7 +1083,7 @@ void dce80_stream_encoder_dp_unblank(
+ /* wait 100us for DIG/DP logic to prime
+ * (i.e. a few video lines)
+ */
+- dm_delay_in_microseconds(ctx, 100);
++ udelay(100);
+
+ /* the hardware would start sending video at the start of the next DP
+ * frame (i.e. rising edge of the vblank).
+diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_scl.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_scl.c
+index c9b3af5..0025e05 100644
+--- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_scl.c
++++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_scl.c
+@@ -246,7 +246,7 @@ static void program_filter(
+ DCFE_MEM_LIGHT_SLEEP_CNTL,
+ SCL_MEM_PWR_STATE);
+ i++)
+- dm_delay_in_microseconds(xfm80->base.ctx, 1);
++ udelay(1);
+
+ ASSERT(i < 10);
+
+diff --git a/drivers/gpu/drm/amd/dal/dc/dm_services.h b/drivers/gpu/drm/amd/dal/dc/dm_services.h
+index 8acdcd4..bf315ac 100644
+--- a/drivers/gpu/drm/amd/dal/dc/dm_services.h
++++ b/drivers/gpu/drm/amd/dal/dc/dm_services.h
+@@ -257,8 +257,6 @@ bool dm_pp_apply_display_requirements(
+
+ void dm_sleep_in_milliseconds(struct dc_context *ctx, uint32_t milliseconds);
+
+-void dm_delay_in_microseconds(struct dc_context *ctx, uint32_t microseconds);
+-
+ enum platform_method {
+ PM_GET_AVAILABLE_METHODS = 1 << 0,
+ PM_GET_LID_STATE = 1 << 1,
+diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/aux_engine.c b/drivers/gpu/drm/amd/dal/dc/i2caux/aux_engine.c
+index 725e183..a281dc0 100644
+--- a/drivers/gpu/drm/amd/dal/dc/i2caux/aux_engine.c
++++ b/drivers/gpu/drm/amd/dal/dc/i2caux/aux_engine.c
+@@ -203,7 +203,7 @@ static void process_read_request(
+ I2CAUX_TRANSACTION_STATUS_FAILED_PROTOCOL_ERROR;
+ ctx->operation_succeeded = false;
+ } else
+- dm_delay_in_microseconds(engine->base.ctx, 400);
++ udelay(400);
+ break;
+ case AUX_CHANNEL_OPERATION_FAILED_TIMEOUT:
+ ++ctx->timed_out_retry_aux;
+@@ -330,7 +330,7 @@ static void process_write_reply(
+ I2CAUX_TRANSACTION_STATUS_FAILED_TIMEOUT;
+ ctx->operation_succeeded = false;
+ } else
+- dm_delay_in_microseconds(engine->base.ctx, 300);
++ udelay(300);
+ } else {
+ ctx->status = I2CAUX_TRANSACTION_STATUS_SUCCEEDED;
+ ctx->defer_retry_aux = 0;
+@@ -401,7 +401,7 @@ static void process_write_request(
+ I2CAUX_TRANSACTION_STATUS_FAILED_PROTOCOL_ERROR;
+ ctx->operation_succeeded = false;
+ } else
+- dm_delay_in_microseconds(engine->base.ctx, 400);
++ udelay(400);
+ break;
+ case AUX_CHANNEL_OPERATION_FAILED_TIMEOUT:
+ ++ctx->timed_out_retry_aux;
+diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/aux_engine_dce110.c b/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/aux_engine_dce110.c
+index d2f49b8..8a23528 100644
+--- a/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/aux_engine_dce110.c
++++ b/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/aux_engine_dce110.c
+@@ -137,7 +137,7 @@ static bool acquire_engine(
+
+ /*poll HW to make sure reset it done*/
+ do {
+- dm_delay_in_microseconds(engine->base.ctx, 1);
++ udelay(1);
+
+ value = dm_read_reg(engine->base.ctx, addr);
+
+@@ -161,7 +161,7 @@ static bool acquire_engine(
+ counter = 0;
+
+ do {
+- dm_delay_in_microseconds(engine->base.ctx, 1);
++ udelay(1);
+
+ value = dm_read_reg(engine->base.ctx, addr);
+
+@@ -640,7 +640,7 @@ static enum aux_channel_operation_result get_channel_status(
+ if (aux_sw_done)
+ break;
+
+- dm_delay_in_microseconds(engine->base.ctx, 10);
++ udelay(10);
+
+ time_elapsed += 10;
+ } while (time_elapsed < aux_engine->timeout_period);
+diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/dce80/aux_engine_dce80.c b/drivers/gpu/drm/amd/dal/dc/i2caux/dce80/aux_engine_dce80.c
+index b732860..4b81f67 100644
+--- a/drivers/gpu/drm/amd/dal/dc/i2caux/dce80/aux_engine_dce80.c
++++ b/drivers/gpu/drm/amd/dal/dc/i2caux/dce80/aux_engine_dce80.c
+@@ -593,7 +593,7 @@ static enum aux_channel_operation_result get_channel_status(
+ if (aux_sw_done)
+ break;
+
+- dm_delay_in_microseconds(engine->base.ctx, 10);
++ udelay(10);
+
+ time_elapsed += 10;
+ } while (time_elapsed < aux_engine->timeout_period);
+diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/i2c_engine.c b/drivers/gpu/drm/amd/dal/dc/i2caux/i2c_engine.c
+index dccb1c5..144f51d 100644
+--- a/drivers/gpu/drm/amd/dal/dc/i2caux/i2c_engine.c
++++ b/drivers/gpu/drm/amd/dal/dc/i2caux/i2c_engine.c
+@@ -66,7 +66,7 @@ bool dal_i2c_engine_acquire(
+
+ /* i2c_engine is busy by VBios, lets wait and retry */
+
+- dm_delay_in_microseconds(engine->ctx, 10);
++ udelay(10);
+
+ ++counter;
+ } while (counter < 2);
+diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/i2c_hw_engine.c b/drivers/gpu/drm/amd/dal/dc/i2caux/i2c_hw_engine.c
+index b02ba79..00a8f07 100644
+--- a/drivers/gpu/drm/amd/dal/dc/i2caux/i2c_hw_engine.c
++++ b/drivers/gpu/drm/amd/dal/dc/i2caux/i2c_hw_engine.c
+@@ -220,7 +220,7 @@ enum i2c_channel_operation_result dal_i2c_hw_engine_wait_on_operation_result(
+ if (result != expected_result)
+ break;
+
+- dm_delay_in_microseconds(engine->base.base.ctx, 1);
++ udelay(1);
+
+ ++i;
+ } while (i < timeout);
+diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/i2c_sw_engine.c b/drivers/gpu/drm/amd/dal/dc/i2caux/i2c_sw_engine.c
+index 2ee5118..ee85f7e 100644
+--- a/drivers/gpu/drm/amd/dal/dc/i2caux/i2c_sw_engine.c
++++ b/drivers/gpu/drm/amd/dal/dc/i2caux/i2c_sw_engine.c
+@@ -84,7 +84,7 @@ static bool wait_for_scl_high(
+ uint32_t scl_retry = 0;
+ uint32_t scl_retry_max = I2C_SW_TIMEOUT_DELAY / clock_delay_div_4;
+
+- dm_delay_in_microseconds(ctx, clock_delay_div_4);
++ udelay(clock_delay_div_4);
+
+ /* 3 milliseconds delay
+ * to wake up some displays from "low power" state.
+@@ -94,7 +94,7 @@ static bool wait_for_scl_high(
+ if (read_bit_from_ddc(ddc, SCL))
+ return true;
+
+- dm_delay_in_microseconds(ctx, clock_delay_div_4);
++ udelay(clock_delay_div_4);
+
+ ++scl_retry;
+ } while (scl_retry <= scl_retry_max);
+@@ -114,7 +114,7 @@ static bool start_sync(
+
+ write_bit_to_ddc(ddc_handle, SCL, true);
+
+- dm_delay_in_microseconds(ctx, clock_delay_div_4);
++ udelay(clock_delay_div_4);
+
+ do {
+ write_bit_to_ddc(ddc_handle, SDA, true);
+@@ -124,7 +124,7 @@ static bool start_sync(
+ continue;
+ }
+
+- dm_delay_in_microseconds(ctx, clock_delay_div_4);
++ udelay(clock_delay_div_4);
+
+ write_bit_to_ddc(ddc_handle, SCL, true);
+
+@@ -133,11 +133,11 @@ static bool start_sync(
+
+ write_bit_to_ddc(ddc_handle, SDA, false);
+
+- dm_delay_in_microseconds(ctx, clock_delay_div_4);
++ udelay(clock_delay_div_4);
+
+ write_bit_to_ddc(ddc_handle, SCL, false);
+
+- dm_delay_in_microseconds(ctx, clock_delay_div_4);
++ udelay(clock_delay_div_4);
+
+ return true;
+ } while (retry <= I2C_SW_RETRIES);
+@@ -157,11 +157,11 @@ static bool stop_sync(
+
+ write_bit_to_ddc(ddc_handle, SCL, false);
+
+- dm_delay_in_microseconds(ctx, clock_delay_div_4);
++ udelay(clock_delay_div_4);
+
+ write_bit_to_ddc(ddc_handle, SDA, false);
+
+- dm_delay_in_microseconds(ctx, clock_delay_div_4);
++ udelay(clock_delay_div_4);
+
+ write_bit_to_ddc(ddc_handle, SCL, true);
+
+@@ -171,7 +171,7 @@ static bool stop_sync(
+ write_bit_to_ddc(ddc_handle, SDA, true);
+
+ do {
+- dm_delay_in_microseconds(ctx, clock_delay_div_4);
++ udelay(clock_delay_div_4);
+
+ if (read_bit_from_ddc(ddc_handle, SDA))
+ return true;
+@@ -194,11 +194,11 @@ static bool write_byte(
+ /* bits are transmitted serially, starting from MSB */
+
+ do {
+- dm_delay_in_microseconds(ctx, clock_delay_div_4);
++ udelay(clock_delay_div_4);
+
+ write_bit_to_ddc(ddc_handle, SDA, (byte >> shift) & 1);
+
+- dm_delay_in_microseconds(ctx, clock_delay_div_4);
++ udelay(clock_delay_div_4);
+
+ write_bit_to_ddc(ddc_handle, SCL, true);
+
+@@ -214,11 +214,11 @@ static bool write_byte(
+ * after the SCL pulse we use to send our last data bit.
+ * If the SDA goes high after that bit, it's a NACK */
+
+- dm_delay_in_microseconds(ctx, clock_delay_div_4);
++ udelay(clock_delay_div_4);
+
+ write_bit_to_ddc(ddc_handle, SDA, true);
+
+- dm_delay_in_microseconds(ctx, clock_delay_div_4);
++ udelay(clock_delay_div_4);
+
+ write_bit_to_ddc(ddc_handle, SCL, true);
+
+@@ -229,11 +229,11 @@ static bool write_byte(
+
+ ack = !read_bit_from_ddc(ddc_handle, SDA);
+
+- dm_delay_in_microseconds(ctx, clock_delay_div_4 << 1);
++ udelay(clock_delay_div_4 << 1);
+
+ write_bit_to_ddc(ddc_handle, SCL, false);
+
+- dm_delay_in_microseconds(ctx, clock_delay_div_4 << 1);
++ udelay(clock_delay_div_4 << 1);
+
+ return ack;
+ }
+@@ -263,7 +263,7 @@ static bool read_byte(
+
+ write_bit_to_ddc(ddc_handle, SCL, false);
+
+- dm_delay_in_microseconds(ctx, clock_delay_div_4 << 1);
++ udelay(clock_delay_div_4 << 1);
+
+ --shift;
+ } while (shift >= 0);
+@@ -272,14 +272,14 @@ static bool read_byte(
+
+ *byte = data;
+
+- dm_delay_in_microseconds(ctx, clock_delay_div_4);
++ udelay(clock_delay_div_4);
+
+ /* send the acknowledge bit:
+ * SDA low means ACK, SDA high means NACK */
+
+ write_bit_to_ddc(ddc_handle, SDA, !more);
+
+- dm_delay_in_microseconds(ctx, clock_delay_div_4);
++ udelay(clock_delay_div_4);
+
+ write_bit_to_ddc(ddc_handle, SCL, true);
+
+@@ -288,11 +288,11 @@ static bool read_byte(
+
+ write_bit_to_ddc(ddc_handle, SCL, false);
+
+- dm_delay_in_microseconds(ctx, clock_delay_div_4);
++ udelay(clock_delay_div_4);
+
+ write_bit_to_ddc(ddc_handle, SDA, true);
+
+- dm_delay_in_microseconds(ctx, clock_delay_div_4);
++ udelay(clock_delay_div_4);
+
+ return true;
+ }
+--
+2.7.4
+
generated by cgit 1.2.3-korg (git 2.39.0) at 2024-04-25 12:15:09 +0000