diff options
Diffstat (limited to 'common/recipes-kernel/linux/files/0868-drm-amd-dal-simplify-clock-source-creation-by-unroll.patch')
-rw-r--r-- | common/recipes-kernel/linux/files/0868-drm-amd-dal-simplify-clock-source-creation-by-unroll.patch | 271 |
1 files changed, 0 insertions, 271 deletions
diff --git a/common/recipes-kernel/linux/files/0868-drm-amd-dal-simplify-clock-source-creation-by-unroll.patch b/common/recipes-kernel/linux/files/0868-drm-amd-dal-simplify-clock-source-creation-by-unroll.patch deleted file mode 100644 index a961978b..00000000 --- a/common/recipes-kernel/linux/files/0868-drm-amd-dal-simplify-clock-source-creation-by-unroll.patch +++ /dev/null @@ -1,271 +0,0 @@ -From ac4532f549eb83f60bc38503b3dc63960e2b453b Mon Sep 17 00:00:00 2001 -From: Tony Cheng <Tony.Cheng@amd.com> -Date: Sat, 27 Feb 2016 17:09:52 -0500 -Subject: [PATCH 0868/1110] drm/amd/dal: simplify clock source creation by - unrolling loop - -- also fix bug where we don't handle dp clk create failure - -Signed-off-by: Tony Cheng <Tony.Cheng@amd.com> -Acked-by: Harry Wentland <harry.wentland@amd.com> ---- - .../gpu/drm/amd/dal/dc/dce100/dce100_resource.c | 50 +++++++---------- - .../gpu/drm/amd/dal/dc/dce110/dce110_resource.c | 53 +++++++----------- - drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c | 64 +++++++--------------- - 3 files changed, 61 insertions(+), 106 deletions(-) - -diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c -index 642c82a..03a5ab0 100644 ---- a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c -+++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c -@@ -58,14 +58,6 @@ - #define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7 - #endif - --enum dce100_clk_src_array_id { -- DCE100_CLK_SRC0 = 0, -- DCE100_CLK_SRC1, -- DCE100_CLK_SRC2, -- -- DCE100_CLK_SRC_TOTAL --}; -- - static const struct dce110_timing_generator_offsets dce100_tg_offsets[] = { - { - .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL), -@@ -936,7 +928,6 @@ bool dce100_construct_resource_pool( - struct dc_context *ctx = dc->ctx; - struct firmware_info info; - struct dc_bios *bp; -- int regular_pll_offset = 0; - - pool->adapter_srv = as; - pool->funcs = &dce100_res_pool_funcs; -@@ -953,30 +944,31 @@ bool dce100_construct_resource_pool( - if (dal_adapter_service_get_firmware_info(as, &info) && - info.external_clock_source_frequency_for_dp != 0) { - pool->dp_clock_source = -- dce100_clock_source_create( -- ctx, -- bp, -- CLOCK_SOURCE_ID_EXTERNAL, -- NULL); -+ dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL); -+ -+ pool->clock_sources[0] = -+ dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &dce100_clk_src_reg_offsets[0]); -+ pool->clock_sources[1] = -+ dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &dce100_clk_src_reg_offsets[1]); -+ pool->clock_sources[2] = -+ dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &dce100_clk_src_reg_offsets[2]); -+ pool->clk_src_count = 3; -+ - } else { - pool->dp_clock_source = -- dce100_clock_source_create( -- ctx, -- bp, -- CLOCK_SOURCE_ID_PLL0, -- &dce100_clk_src_reg_offsets[0]); -- regular_pll_offset = 1; -+ dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &dce100_clk_src_reg_offsets[0]); -+ pool->clock_sources[0] = -+ dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &dce100_clk_src_reg_offsets[1]); -+ pool->clock_sources[1] = -+ dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &dce100_clk_src_reg_offsets[2]); -+ pool->clk_src_count = 2; - } - -- pool->clk_src_count = DCE100_CLK_SRC_TOTAL - regular_pll_offset; -- -- for (i = 0; i < pool->clk_src_count; ++i, ++regular_pll_offset) -- pool->clock_sources[i] = -- dce100_clock_source_create( -- ctx, -- bp, -- CLOCK_SOURCE_ID_PLL0 + regular_pll_offset, -- &dce100_clk_src_reg_offsets[regular_pll_offset]); -+ if (pool->dp_clock_source == NULL) { -+ dm_error("DC: failed to create dp clock source!\n"); -+ BREAK_TO_DEBUGGER(); -+ goto clk_src_create_fail; -+ } - - for (i = 0; i < pool->clk_src_count; i++) { - if (pool->clock_sources[i] == NULL) { -diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c -index 557c2fe..cde8d64 100644 ---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c -+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c -@@ -59,13 +59,6 @@ - #define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7 - #endif - --enum dce110_clk_src_array_id { -- DCE110_CLK_SRC0 = 0, -- DCE110_CLK_SRC1, -- -- DCE110_CLK_SRC_TOTAL --}; -- - static const struct dce110_timing_generator_offsets dce110_tg_offsets[] = { - { - .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL), -@@ -291,6 +284,10 @@ static const struct dce110_clk_src_reg_offsets dce110_clk_src_reg_offsets[] = { - { - .pll_cntl = mmBPHYC_PLL1_PLL_CNTL, - .pixclk_resync_cntl = mmPIXCLK1_RESYNC_CNTL -+ }, -+ { -+ .pll_cntl = mmBPHYC_PLL2_PLL_CNTL, -+ .pixclk_resync_cntl = mmPIXCLK2_RESYNC_CNTL - } - }; - -@@ -1091,35 +1088,23 @@ bool dce110_construct_resource_pool( - if (dal_adapter_service_get_firmware_info(as, &info) && - info.external_clock_source_frequency_for_dp != 0) { - pool->dp_clock_source = -- dce110_clock_source_create( -- ctx, -- bp, -- CLOCK_SOURCE_ID_EXTERNAL, -- NULL); -- pool->clk_src_count = DCE110_CLK_SRC_TOTAL; -- } else { -- pool->dp_clock_source = -- dce110_clock_source_create( -- ctx, -- bp, -- CLOCK_SOURCE_ID_PLL0, -- &dce110_clk_src_reg_offsets[0]); -- pool->clk_src_count = DCE110_CLK_SRC_TOTAL - 1; -+ dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL); -+ -+ pool->clock_sources[0] = -+ dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &dce110_clk_src_reg_offsets[0]); -+ pool->clock_sources[1] = -+ dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &dce110_clk_src_reg_offsets[1]); -+ -+ pool->clk_src_count = 2; -+ -+ /* TODO: find out if CZ support 3 PLLs */ - } - -- pool->clock_sources[DCE110_CLK_SRC0] = -- dce110_clock_source_create( -- ctx, -- bp, -- CLOCK_SOURCE_ID_PLL0, -- &dce110_clk_src_reg_offsets[0]); -- -- pool->clock_sources[DCE110_CLK_SRC1] = -- dce110_clock_source_create( -- ctx, -- bp, -- CLOCK_SOURCE_ID_PLL1, -- &dce110_clk_src_reg_offsets[1]); -+ if (pool->dp_clock_source == NULL) { -+ dm_error("DC: failed to create dp clock source!\n"); -+ BREAK_TO_DEBUGGER(); -+ goto clk_src_create_fail; -+ } - - for (i = 0; i < pool->clk_src_count; i++) { - if (pool->clock_sources[i] == NULL) { -diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c -index e4f2bef..fd97afe 100644 ---- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c -+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c -@@ -61,14 +61,6 @@ - #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x4EDE - #endif - --enum dce80_clk_src_array_id { -- DCE80_CLK_SRC0 = 0, -- DCE80_CLK_SRC1, -- DCE80_CLK_SRC2, -- -- DCE80_CLK_SRC_TOTAL --}; -- - #define DCE11_DIG_FE_CNTL 0x4a00 - #define DCE11_DIG_BE_CNTL 0x4a47 - #define DCE11_DP_SEC 0x4ac3 -@@ -1046,7 +1038,6 @@ bool dce80_construct_resource_pool( - struct dc_context *ctx = dc->ctx; - struct firmware_info info; - struct dc_bios *bp; -- int regular_pll_offset = 0; - - pool->adapter_srv = as; - pool->funcs = &dce80_res_pool_funcs; -@@ -1063,44 +1054,31 @@ bool dce80_construct_resource_pool( - if (dal_adapter_service_get_firmware_info(as, &info) && - info.external_clock_source_frequency_for_dp != 0) { - pool->dp_clock_source = -- dce80_clock_source_create( -- ctx, -- bp, -- CLOCK_SOURCE_ID_EXTERNAL, -- NULL); -+ dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL); -+ -+ pool->clock_sources[0] = -+ dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &dce80_clk_src_reg_offsets[0]); -+ pool->clock_sources[1] = -+ dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &dce80_clk_src_reg_offsets[1]); -+ pool->clock_sources[2] = -+ dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &dce80_clk_src_reg_offsets[2]); -+ pool->clk_src_count = 3; -+ - } else { - pool->dp_clock_source = -- dce80_clock_source_create( -- ctx, -- bp, -- CLOCK_SOURCE_ID_PLL0, -- &dce80_clk_src_reg_offsets[0]); -- regular_pll_offset = 1; -+ dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &dce80_clk_src_reg_offsets[0]); -+ pool->clock_sources[0] = -+ dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &dce80_clk_src_reg_offsets[1]); -+ pool->clock_sources[1] = -+ dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &dce80_clk_src_reg_offsets[2]); -+ pool->clk_src_count = 2; - } - -- pool->clk_src_count = DCE80_CLK_SRC_TOTAL - regular_pll_offset; -- -- for (i = 0; i < DCE80_CLK_SRC_TOTAL; ++i, ++regular_pll_offset) -- pool->clock_sources[DCE80_CLK_SRC0 + i] = -- dce80_clock_source_create( -- ctx, -- bp, -- CLOCK_SOURCE_ID_PLL0 + regular_pll_offset, -- &dce80_clk_src_reg_offsets[regular_pll_offset]); -- -- pool->clock_sources[DCE80_CLK_SRC1] = -- dce80_clock_source_create( -- ctx, -- bp, -- CLOCK_SOURCE_ID_PLL1, -- &dce80_clk_src_reg_offsets[1]); -- -- pool->clock_sources[DCE80_CLK_SRC2] = -- dce80_clock_source_create( -- ctx, -- bp, -- CLOCK_SOURCE_ID_PLL2, -- &dce80_clk_src_reg_offsets[2]); -+ if (pool->dp_clock_source == NULL) { -+ dm_error("DC: failed to create dp clock source!\n"); -+ BREAK_TO_DEBUGGER(); -+ goto clk_src_create_fail; -+ } - - for (i = 0; i < pool->clk_src_count; i++) { - if (pool->clock_sources[i] == NULL) { --- -2.7.4 - |