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-rw-r--r--common/recipes-kernel/linux/files/0847-drm-amd-dal-Refactor-PPLib-interfaces.patch626
1 files changed, 0 insertions, 626 deletions
diff --git a/common/recipes-kernel/linux/files/0847-drm-amd-dal-Refactor-PPLib-interfaces.patch b/common/recipes-kernel/linux/files/0847-drm-amd-dal-Refactor-PPLib-interfaces.patch
deleted file mode 100644
index f5648011..00000000
--- a/common/recipes-kernel/linux/files/0847-drm-amd-dal-Refactor-PPLib-interfaces.patch
+++ /dev/null
@@ -1,626 +0,0 @@
-From 4f8dfe4d331cfa5ecb96693591fc21a871bd341b Mon Sep 17 00:00:00 2001
-From: Jun Lei <Jun.Lei@amd.com>
-Date: Wed, 17 Feb 2016 16:28:47 -0500
-Subject: [PATCH 0847/1110] drm/amd/dal: Refactor PPLib interfaces
-
-Signed-off-by: Jun Lei <Jun.Lei@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_services.c | 66 +++++-----
- drivers/gpu/drm/amd/dal/dc/core/dc.c | 8 +-
- drivers/gpu/drm/amd/dal/dc/core/dc_resource.c | 11 +-
- drivers/gpu/drm/amd/dal/dc/dc_types.h | 1 +
- drivers/gpu/drm/amd/dal/dc/dm_services.h | 146 +--------------------
- drivers/gpu/drm/amd/dal/dc/dm_services_types.h | 102 ++++++++++++++
- drivers/gpu/drm/amd/dal/dc/inc/core_types.h | 2 +-
- drivers/gpu/drm/amd/dal/dc/inc/resource.h | 2 +-
- 8 files changed, 155 insertions(+), 183 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_services.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_services.c
-index b155270..116d34d 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_services.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_services.c
-@@ -75,7 +75,7 @@ int32_t dm_memcmp(const void *p1, const void *p2, uint32_t count)
- return memcmp(p1, p2, count);
- }
-
--int32_t dm_strncmp(const int8_t *p1, const int8_t *p2, uint32_t count)
-+int32_t dm_strncmp(const char *p1, const char *p2, uint32_t count)
- {
- return strncmp(p1, p2, count);
- }
-@@ -150,8 +150,8 @@ bool dm_get_platform_info(struct dc_context *ctx,
-
- bool dm_pp_pre_dce_clock_change(
- struct dc_context *ctx,
-- struct dal_to_power_info *input,
-- struct power_to_dal_info *output)
-+ struct dm_pp_gpu_clock_range *requested_state,
-+ struct dm_pp_gpu_clock_range *actual_state)
- {
- /*TODO*/
- return false;
-@@ -175,7 +175,7 @@ bool dm_pp_apply_safe_state(
-
- bool dm_pp_apply_display_requirements(
- const struct dc_context *ctx,
-- const struct dc_pp_display_configuration *pp_display_cfg)
-+ const struct dm_pp_display_configuration *pp_display_cfg)
- {
- #ifdef CONFIG_DRM_AMD_POWERPLAY
- struct amdgpu_device *adev = ctx->driver_context;
-@@ -248,26 +248,26 @@ bool dm_pp_apply_display_requirements(
-
- bool dc_service_get_system_clocks_range(
- const struct dc_context *ctx,
-- struct dal_system_clock_range *sys_clks)
-+ struct dm_pp_gpu_clock_range *sys_clks)
- {
- #ifdef CONFIG_DRM_AMD_POWERPLAY
- struct amdgpu_device *adev = ctx->driver_context;
- #endif
-
- /* Default values, in case PPLib is not compiled-in. */
-- sys_clks->max_mclk = 80000;
-- sys_clks->min_mclk = 80000;
-+ sys_clks->mclk.max_khz = 800000;
-+ sys_clks->mclk.min_khz = 800000;
-
-- sys_clks->max_sclk = 60000;
-- sys_clks->min_sclk = 30000;
-+ sys_clks->sclk.max_khz = 600000;
-+ sys_clks->sclk.min_khz = 300000;
-
- #ifdef CONFIG_DRM_AMD_POWERPLAY
- if (adev->pm.dpm_enabled) {
-- sys_clks->max_mclk = amdgpu_dpm_get_mclk(adev, false);
-- sys_clks->min_mclk = amdgpu_dpm_get_mclk(adev, true);
-+ sys_clks->mclk.max_khz = amdgpu_dpm_get_mclk(adev, false);
-+ sys_clks->mclk.min_khz = amdgpu_dpm_get_mclk(adev, true);
-
-- sys_clks->max_sclk = amdgpu_dpm_get_sclk(adev, false);
-- sys_clks->min_sclk = amdgpu_dpm_get_sclk(adev, true);
-+ sys_clks->sclk.max_khz = amdgpu_dpm_get_sclk(adev, false);
-+ sys_clks->sclk.min_khz = amdgpu_dpm_get_sclk(adev, true);
- }
- #endif
-
-@@ -275,8 +275,8 @@ bool dc_service_get_system_clocks_range(
- }
-
- static void get_default_clock_levels(
-- enum dc_pp_clock_type clk_type,
-- struct dc_pp_clock_levels *clks)
-+ enum dm_pp_clock_type clk_type,
-+ struct dm_pp_clock_levels *clks)
- {
- uint32_t disp_clks_in_khz[6] = {
- 300000, 400000, 496560, 626090, 685720, 757900 };
-@@ -285,17 +285,17 @@ static void get_default_clock_levels(
- uint32_t mclks_in_khz[2] = { 333000, 800000 };
-
- switch (clk_type) {
-- case DC_PP_CLOCK_TYPE_DISPLAY_CLK:
-+ case DM_PP_CLOCK_TYPE_DISPLAY_CLK:
- clks->num_levels = 6;
- dm_memmove(clks->clocks_in_khz, disp_clks_in_khz,
- sizeof(disp_clks_in_khz));
- break;
-- case DC_PP_CLOCK_TYPE_ENGINE_CLK:
-+ case DM_PP_CLOCK_TYPE_ENGINE_CLK:
- clks->num_levels = 6;
- dm_memmove(clks->clocks_in_khz, sclks_in_khz,
- sizeof(sclks_in_khz));
- break;
-- case DC_PP_CLOCK_TYPE_MEMORY_CLK:
-+ case DM_PP_CLOCK_TYPE_MEMORY_CLK:
- clks->num_levels = 2;
- dm_memmove(clks->clocks_in_khz, mclks_in_khz,
- sizeof(mclks_in_khz));
-@@ -308,23 +308,23 @@ static void get_default_clock_levels(
-
- #ifdef CONFIG_DRM_AMD_POWERPLAY
- static enum amd_pp_clock_type dc_to_pp_clock_type(
-- enum dc_pp_clock_type dc_pp_clk_type)
-+ enum dm_pp_clock_type dm_pp_clk_type)
- {
- enum amd_pp_clock_type amd_pp_clk_type = 0;
-
-- switch (dc_pp_clk_type) {
-- case DC_PP_CLOCK_TYPE_DISPLAY_CLK:
-+ switch (dm_pp_clk_type) {
-+ case DM_PP_CLOCK_TYPE_DISPLAY_CLK:
- amd_pp_clk_type = amd_pp_disp_clock;
- break;
-- case DC_PP_CLOCK_TYPE_ENGINE_CLK:
-+ case DM_PP_CLOCK_TYPE_ENGINE_CLK:
- amd_pp_clk_type = amd_pp_sys_clock;
- break;
-- case DC_PP_CLOCK_TYPE_MEMORY_CLK:
-+ case DM_PP_CLOCK_TYPE_MEMORY_CLK:
- amd_pp_clk_type = amd_pp_mem_clock;
- break;
- default:
- DRM_ERROR("DM_PPLIB: invalid clock type: %d!\n",
-- dc_pp_clk_type);
-+ dm_pp_clk_type);
- break;
- }
-
-@@ -333,18 +333,18 @@ static enum amd_pp_clock_type dc_to_pp_clock_type(
-
- static void pp_to_dc_clock_levels(
- const struct amd_pp_clocks *pp_clks,
-- struct dc_pp_clock_levels *dc_clks,
-- enum dc_pp_clock_type dc_clk_type)
-+ struct dm_pp_clock_levels *dc_clks,
-+ enum dm_pp_clock_type dc_clk_type)
- {
- uint32_t i;
-
-- if (pp_clks->count > DC_PP_MAX_CLOCK_LEVELS) {
-+ if (pp_clks->count > DM_PP_MAX_CLOCK_LEVELS) {
- DRM_INFO("DM_PPLIB: Warning: %s clock: number of levels %d exceeds maximum of %d!\n",
- DC_DECODE_PP_CLOCK_TYPE(dc_clk_type),
- pp_clks->count,
-- DC_PP_MAX_CLOCK_LEVELS);
-+ DM_PP_MAX_CLOCK_LEVELS);
-
-- dc_clks->num_levels = DC_PP_MAX_CLOCK_LEVELS;
-+ dc_clks->num_levels = DM_PP_MAX_CLOCK_LEVELS;
- } else
- dc_clks->num_levels = pp_clks->count;
-
-@@ -361,8 +361,8 @@ static void pp_to_dc_clock_levels(
-
- bool dm_pp_get_clock_levels_by_type(
- const struct dc_context *ctx,
-- enum dc_pp_clock_type clk_type,
-- struct dc_pp_clock_levels *dc_clks)
-+ enum dm_pp_clock_type clk_type,
-+ struct dm_pp_clock_levels *dc_clks)
- {
- #ifdef CONFIG_DRM_AMD_POWERPLAY
- struct amdgpu_device *adev = ctx->driver_context;
-@@ -402,7 +402,7 @@ bool dm_pp_get_clock_levels_by_type(
- validation_clks.memory_max_clock *= 10;
-
- /* Determine the highest non-boosted level from the Validation Clocks */
-- if (clk_type == DC_PP_CLOCK_TYPE_ENGINE_CLK) {
-+ if (clk_type == DM_PP_CLOCK_TYPE_ENGINE_CLK) {
- for (i = 0; i < dc_clks->num_levels; i++) {
- if (dc_clks->clocks_in_khz[i] > validation_clks.engine_max_clock) {
- /* This clock is higher the validation clock.
-@@ -414,7 +414,7 @@ bool dm_pp_get_clock_levels_by_type(
- break;
- }
- }
-- } else if (clk_type == DC_PP_CLOCK_TYPE_MEMORY_CLK) {
-+ } else if (clk_type == DM_PP_CLOCK_TYPE_MEMORY_CLK) {
- for (i = 0; i < dc_clks->num_levels; i++) {
- if (dc_clks->clocks_in_khz[i] > validation_clks.memory_max_clock) {
- DRM_INFO("DM_PPLIB: reducing memory clock level from %d to %d\n",
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index 7eaf7ef..d02f3c0 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -259,12 +259,12 @@ static struct adapter_service *create_as(
-
- static void bw_calcs_data_update_from_pplib(struct dc *dc)
- {
-- struct dc_pp_clock_levels clks = {0};
-+ struct dm_pp_clock_levels clks = {0};
-
- /*do system clock*/
- dm_pp_get_clock_levels_by_type(
- dc->ctx,
-- DC_PP_CLOCK_TYPE_ENGINE_CLK,
-+ DM_PP_CLOCK_TYPE_ENGINE_CLK,
- &clks);
- /* convert all the clock fro kHz to fix point mHz */
- dc->bw_vbios.high_sclk = bw_frc_to_fixed(
-@@ -277,7 +277,7 @@ static void bw_calcs_data_update_from_pplib(struct dc *dc)
- /*do display clock*/
- dm_pp_get_clock_levels_by_type(
- dc->ctx,
-- DC_PP_CLOCK_TYPE_DISPLAY_CLK,
-+ DM_PP_CLOCK_TYPE_DISPLAY_CLK,
- &clks);
-
- dc->bw_vbios.high_voltage_max_dispclk = bw_frc_to_fixed(
-@@ -290,7 +290,7 @@ static void bw_calcs_data_update_from_pplib(struct dc *dc)
- /*do memory clock*/
- dm_pp_get_clock_levels_by_type(
- dc->ctx,
-- DC_PP_CLOCK_TYPE_MEMORY_CLK,
-+ DM_PP_CLOCK_TYPE_MEMORY_CLK,
- &clks);
-
- dc->bw_vbios.low_yclk = bw_frc_to_fixed(
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-index 1bb4adb..5e32289 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-@@ -476,7 +476,7 @@ static uint32_t get_min_vblank_time_us(const struct validate_context *context)
-
- static void fill_display_configs(
- const struct validate_context *context,
-- struct dc_pp_display_configuration *pp_display_cfg)
-+ struct dm_pp_display_configuration *pp_display_cfg)
- {
- uint8_t i, j, k;
- uint8_t num_cfgs = 0;
-@@ -487,7 +487,7 @@ static void fill_display_configs(
- for (j = 0; j < target->public.stream_count; j++) {
- const struct core_stream *stream =
- DC_STREAM_TO_CORE(target->public.streams[j]);
-- struct dc_pp_single_disp_config *cfg =
-+ struct dm_pp_single_disp_config *cfg =
- &pp_display_cfg->disp_configs[num_cfgs];
- const struct pipe_ctx *pipe_ctx = NULL;
-
-@@ -507,8 +507,9 @@ static void fill_display_configs(
- stream->sink->link->ddi_channel_mapping.raw;
- cfg->transmitter =
- stream->sink->link->link_enc->transmitter;
-- cfg->link_settings =
-- stream->sink->link->public.cur_link_settings;
-+ cfg->link_settings.lane_count = stream->sink->link->public.cur_link_settings.lane_count;
-+ cfg->link_settings.link_rate = stream->sink->link->public.cur_link_settings.link_rate;
-+ cfg->link_settings.link_spread = stream->sink->link->public.cur_link_settings.link_spread;
- cfg->sym_clock = stream->public.timing.pix_clk_khz;
- switch (stream->public.timing.display_color_depth) {
- case COLOR_DEPTH_101010:
-@@ -539,7 +540,7 @@ void pplib_apply_safe_state(
- void pplib_apply_display_requirements(
- const struct dc *dc,
- const struct validate_context *context,
-- struct dc_pp_display_configuration *pp_display_cfg)
-+ struct dm_pp_display_configuration *pp_display_cfg)
- {
-
- pp_display_cfg->all_displays_in_sync =
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_types.h b/drivers/gpu/drm/amd/dal/dc/dc_types.h
-index 8d81d08..6b87b1d 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_types.h
-@@ -30,6 +30,7 @@
- #include "irq_types.h"
- #include "dc_dp_types.h"
- #include "dc_hw_types.h"
-+#include "signal_types.h"
-
- /* forward declarations */
- struct dc;
-diff --git a/drivers/gpu/drm/amd/dal/dc/dm_services.h b/drivers/gpu/drm/amd/dal/dc/dm_services.h
-index 604aa43..5ba8be8 100644
---- a/drivers/gpu/drm/amd/dal/dc/dm_services.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dm_services.h
-@@ -54,7 +54,7 @@ void dm_memmove(void *dst, const void *src, uint32_t size);
-
- int32_t dm_memcmp(const void *p1, const void *p2, uint32_t count);
-
--int32_t dm_strncmp(const int8_t *p1, const int8_t *p2, uint32_t count);
-+int32_t dm_strncmp(const char *p1, const char *p2, uint32_t count);
-
- irq_handler_idx dm_register_interrupt(
- struct dc_context *ctx,
-@@ -205,53 +205,6 @@ uint32_t dm_bios_cmd_table_para_revision(
- * Power Play (PP) interfaces
- **************************************/
-
--enum dal_to_power_clocks_state {
-- PP_CLOCKS_STATE_INVALID,
-- PP_CLOCKS_STATE_ULTRA_LOW,
-- PP_CLOCKS_STATE_LOW,
-- PP_CLOCKS_STATE_NOMINAL,
-- PP_CLOCKS_STATE_PERFORMANCE
--};
--
--/* clocks in khz */
--struct dal_to_power_info {
-- enum dal_to_power_clocks_state required_clock;
-- uint32_t min_sclk;
-- uint32_t min_mclk;
-- uint32_t min_deep_sleep_sclk;
--};
--
--/* clocks in khz */
--struct power_to_dal_info {
-- uint32_t min_sclk;
-- uint32_t max_sclk;
-- uint32_t min_mclk;
-- uint32_t max_mclk;
--};
--
--/* clocks in khz */
--struct dal_system_clock_range {
-- uint32_t min_sclk;
-- uint32_t max_sclk;
--
-- uint32_t min_mclk;
-- uint32_t max_mclk;
--
-- uint32_t min_dclk;
-- uint32_t max_dclk;
--
-- /* Wireless Display */
-- uint32_t min_eclk;
-- uint32_t max_eclk;
--};
--
--/* clocks in khz */
--struct dal_to_power_dclk {
-- uint32_t optimal; /* input: best optimizes for stutter efficiency */
-- uint32_t minimal; /* input: the lowest clk that DAL can support */
-- uint32_t established; /* output: the actually set one */
--};
--
- /* DAL calls this function to notify PP about clocks it needs for the Mode Set.
- * This is done *before* it changes DCE clock.
- *
-@@ -270,75 +223,8 @@ struct dal_to_power_dclk {
- */
- bool dm_pp_pre_dce_clock_change(
- struct dc_context *ctx,
-- struct dal_to_power_info *input,
-- struct power_to_dal_info *output);
--
--struct dc_pp_single_disp_config {
-- enum signal_type signal;
-- uint8_t transmitter;
-- uint8_t ddi_channel_mapping;
-- uint8_t pipe_idx;
-- uint32_t src_height;
-- uint32_t src_width;
-- uint32_t v_refresh;
-- uint32_t sym_clock; /* HDMI only */
-- struct dc_link_settings link_settings; /* DP only */
--};
--
--struct dc_pp_display_configuration {
-- bool nb_pstate_switch_disable;/* controls NB PState switch */
-- bool cpu_cc6_disable; /* controls CPU CState switch ( on or off) */
-- bool cpu_pstate_disable;
-- uint32_t cpu_pstate_separation_time;
--
-- uint32_t min_memory_clock_khz;
-- uint32_t min_engine_clock_khz;
-- uint32_t min_engine_clock_deep_sleep_khz;
--
-- uint32_t avail_mclk_switch_time_us;
-- uint32_t avail_mclk_switch_time_in_disp_active_us;
--
-- uint32_t disp_clk_khz;
--
-- bool all_displays_in_sync;
--
-- uint8_t display_count;
-- struct dc_pp_single_disp_config disp_configs[MAX_COFUNC_PATH];
--
-- /*Controller Index of primary display - used in MCLK SMC switching hang
-- * SW Workaround*/
-- uint8_t crtc_index;
-- /*htotal*1000/pixelclk - used in MCLK SMC switching hang SW Workaround*/
-- uint32_t line_time_in_us;
--};
--
--enum dc_pp_clocks_state {
-- DC_PP_CLOCKS_STATE_INVALID = 0,
-- DC_PP_CLOCKS_STATE_ULTRA_LOW,
-- DC_PP_CLOCKS_STATE_LOW,
-- DC_PP_CLOCKS_STATE_NOMINAL,
-- DC_PP_CLOCKS_STATE_PERFORMANCE,
--
-- /* Starting from DCE11, Max 8 levels of DPM state supported. */
-- DC_PP_CLOCKS_DPM_STATE_LEVEL_INVALID = DC_PP_CLOCKS_STATE_INVALID,
-- DC_PP_CLOCKS_DPM_STATE_LEVEL_0 = DC_PP_CLOCKS_STATE_ULTRA_LOW,
-- DC_PP_CLOCKS_DPM_STATE_LEVEL_1 = DC_PP_CLOCKS_STATE_LOW,
-- DC_PP_CLOCKS_DPM_STATE_LEVEL_2 = DC_PP_CLOCKS_STATE_NOMINAL,
-- /* to be backward compatible */
-- DC_PP_CLOCKS_DPM_STATE_LEVEL_3 = DC_PP_CLOCKS_STATE_PERFORMANCE,
-- DC_PP_CLOCKS_DPM_STATE_LEVEL_4 = DC_PP_CLOCKS_DPM_STATE_LEVEL_3 + 1,
-- DC_PP_CLOCKS_DPM_STATE_LEVEL_5 = DC_PP_CLOCKS_DPM_STATE_LEVEL_4 + 1,
-- DC_PP_CLOCKS_DPM_STATE_LEVEL_6 = DC_PP_CLOCKS_DPM_STATE_LEVEL_5 + 1,
-- DC_PP_CLOCKS_DPM_STATE_LEVEL_7 = DC_PP_CLOCKS_DPM_STATE_LEVEL_6 + 1,
--};
--
--struct dc_pp_static_clock_info {
-- uint32_t max_sclk_khz;
-- uint32_t max_mclk_khz;
--
-- /* max possible display block clocks state */
-- enum dc_pp_clocks_state max_clocks_state;
--};
-+ struct dm_pp_gpu_clock_range *requested_state,
-+ struct dm_pp_gpu_clock_range *actual_state);
-
- /* The returned clocks range are 'static' system clocks which will be used for
- * mode validation purposes.
-@@ -348,25 +234,7 @@ struct dc_pp_static_clock_info {
- */
- bool dc_service_get_system_clocks_range(
- const struct dc_context *ctx,
-- struct dal_system_clock_range *sys_clks);
--
--enum dc_pp_clock_type {
-- DC_PP_CLOCK_TYPE_DISPLAY_CLK = 1,
-- DC_PP_CLOCK_TYPE_ENGINE_CLK, /* System clock */
-- DC_PP_CLOCK_TYPE_MEMORY_CLK
--};
--
--#define DC_DECODE_PP_CLOCK_TYPE(clk_type) \
-- (clk_type) == DC_PP_CLOCK_TYPE_DISPLAY_CLK ? "Display" : \
-- (clk_type) == DC_PP_CLOCK_TYPE_ENGINE_CLK ? "Engine" : \
-- (clk_type) == DC_PP_CLOCK_TYPE_MEMORY_CLK ? "Memory" : "Invalid"
--
--#define DC_PP_MAX_CLOCK_LEVELS 8
--
--struct dc_pp_clock_levels {
-- uint32_t num_levels;
-- uint32_t clocks_in_khz[DC_PP_MAX_CLOCK_LEVELS];
--};
-+ struct dm_pp_gpu_clock_range *sys_clks);
-
- /* Gets valid clocks levels from pplib
- *
-@@ -378,8 +246,8 @@ struct dc_pp_clock_levels {
- */
- bool dm_pp_get_clock_levels_by_type(
- const struct dc_context *ctx,
-- enum dc_pp_clock_type clk_type,
-- struct dc_pp_clock_levels *clk_level_info);
-+ enum dm_pp_clock_type clk_type,
-+ struct dm_pp_clock_levels *clk_level_info);
-
-
- bool dm_pp_apply_safe_state(
-@@ -398,7 +266,7 @@ bool dm_pp_apply_safe_state(
- */
- bool dm_pp_apply_display_requirements(
- const struct dc_context *ctx,
-- const struct dc_pp_display_configuration *pp_display_cfg);
-+ const struct dm_pp_display_configuration *pp_display_cfg);
-
-
- /****** end of PP interfaces ******/
-diff --git a/drivers/gpu/drm/amd/dal/dc/dm_services_types.h b/drivers/gpu/drm/amd/dal/dc/dm_services_types.h
-index 7c8b31f..a74fb85 100644
---- a/drivers/gpu/drm/amd/dal/dc/dm_services_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dm_services_types.h
-@@ -162,4 +162,106 @@ static inline uint64_t div_u64_rem(uint64_t x, uint32_t y, uint32_t *rem)
-
- #endif
-
-+#include "dc_types.h"
-+
-+struct dm_pp_clock_range {
-+ int min_khz;
-+ int max_khz;
-+};
-+
-+enum dm_pp_clocks_state {
-+ DM_PP_CLOCKS_STATE_INVALID,
-+ DM_PP_CLOCKS_STATE_ULTRA_LOW,
-+ DM_PP_CLOCKS_STATE_LOW,
-+ DM_PP_CLOCKS_STATE_NOMINAL,
-+ DM_PP_CLOCKS_STATE_PERFORMANCE,
-+
-+ /* Starting from DCE11, Max 8 levels of DPM state supported. */
-+ DM_PP_CLOCKS_DPM_STATE_LEVEL_INVALID = DM_PP_CLOCKS_STATE_INVALID,
-+ DM_PP_CLOCKS_DPM_STATE_LEVEL_0 = DM_PP_CLOCKS_STATE_ULTRA_LOW,
-+ DM_PP_CLOCKS_DPM_STATE_LEVEL_1 = DM_PP_CLOCKS_STATE_LOW,
-+ DM_PP_CLOCKS_DPM_STATE_LEVEL_2 = DM_PP_CLOCKS_STATE_NOMINAL,
-+ /* to be backward compatible */
-+ DM_PP_CLOCKS_DPM_STATE_LEVEL_3 = DM_PP_CLOCKS_STATE_PERFORMANCE,
-+ DM_PP_CLOCKS_DPM_STATE_LEVEL_4 = DM_PP_CLOCKS_DPM_STATE_LEVEL_3 + 1,
-+ DM_PP_CLOCKS_DPM_STATE_LEVEL_5 = DM_PP_CLOCKS_DPM_STATE_LEVEL_4 + 1,
-+ DM_PP_CLOCKS_DPM_STATE_LEVEL_6 = DM_PP_CLOCKS_DPM_STATE_LEVEL_5 + 1,
-+ DM_PP_CLOCKS_DPM_STATE_LEVEL_7 = DM_PP_CLOCKS_DPM_STATE_LEVEL_6 + 1,
-+};
-+
-+struct dm_pp_gpu_clock_range {
-+ enum dm_pp_clocks_state clock_state;
-+ struct dm_pp_clock_range sclk;
-+ struct dm_pp_clock_range mclk;
-+ struct dm_pp_clock_range eclk;
-+ struct dm_pp_clock_range dclk;
-+};
-+
-+enum dm_pp_clock_type {
-+ DM_PP_CLOCK_TYPE_DISPLAY_CLK = 1,
-+ DM_PP_CLOCK_TYPE_ENGINE_CLK, /* System clock */
-+ DM_PP_CLOCK_TYPE_MEMORY_CLK
-+};
-+
-+#define DC_DECODE_PP_CLOCK_TYPE(clk_type) \
-+ (clk_type) == DM_PP_CLOCK_TYPE_DISPLAY_CLK ? "Display" : \
-+ (clk_type) == DM_PP_CLOCK_TYPE_ENGINE_CLK ? "Engine" : \
-+ (clk_type) == DM_PP_CLOCK_TYPE_MEMORY_CLK ? "Memory" : "Invalid"
-+
-+#define DM_PP_MAX_CLOCK_LEVELS 8
-+
-+struct dm_pp_clock_levels {
-+ uint32_t num_levels;
-+ uint32_t clocks_in_khz[DM_PP_MAX_CLOCK_LEVELS];
-+};
-+
-+struct dm_pp_single_disp_config {
-+ enum signal_type signal;
-+ uint8_t transmitter;
-+ uint8_t ddi_channel_mapping;
-+ uint8_t pipe_idx;
-+ uint32_t src_height;
-+ uint32_t src_width;
-+ uint32_t v_refresh;
-+ uint32_t sym_clock; /* HDMI only */
-+ struct dc_link_settings link_settings; /* DP only */
-+};
-+
-+#define MAX_DISPLAY_CONFIGS 6
-+
-+struct dm_pp_display_configuration {
-+ bool nb_pstate_switch_disable;/* controls NB PState switch */
-+ bool cpu_cc6_disable; /* controls CPU CState switch ( on or off) */
-+ bool cpu_pstate_disable;
-+ uint32_t cpu_pstate_separation_time;
-+
-+ uint32_t min_memory_clock_khz;
-+ uint32_t min_engine_clock_khz;
-+ uint32_t min_engine_clock_deep_sleep_khz;
-+
-+ uint32_t avail_mclk_switch_time_us;
-+ uint32_t avail_mclk_switch_time_in_disp_active_us;
-+
-+ uint32_t disp_clk_khz;
-+
-+ bool all_displays_in_sync;
-+
-+ uint8_t display_count;
-+ struct dm_pp_single_disp_config disp_configs[MAX_DISPLAY_CONFIGS];
-+
-+ /*Controller Index of primary display - used in MCLK SMC switching hang
-+ * SW Workaround*/
-+ uint8_t crtc_index;
-+ /*htotal*1000/pixelclk - used in MCLK SMC switching hang SW Workaround*/
-+ uint32_t line_time_in_us;
-+};
-+
-+struct dm_pp_static_clock_info {
-+ uint32_t max_sclk_khz;
-+ uint32_t max_mclk_khz;
-+
-+ /* max possible display block clocks state */
-+ enum dm_pp_clocks_state max_clocks_state;
-+};
-+
- #endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-index 70b4a85..a5444cb 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-@@ -346,7 +346,7 @@ struct validate_context {
- /* The output from BW and WM calculations. */
- struct bw_calcs_output bw_results;
- /* Note: this is a big structure, do *not* put on stack! */
-- struct dc_pp_display_configuration pp_display_cfg;
-+ struct dm_pp_display_configuration pp_display_cfg;
- };
-
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/resource.h b/drivers/gpu/drm/amd/dal/dc/inc/resource.h
-index 983d484..717bf13 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/resource.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/resource.h
-@@ -72,7 +72,7 @@ void pplib_apply_safe_state(const struct dc *dc);
- void pplib_apply_display_requirements(
- const struct dc *dc,
- const struct validate_context *context,
-- struct dc_pp_display_configuration *pp_display_cfg);
-+ struct dm_pp_display_configuration *pp_display_cfg);
-
- void build_info_frame(struct pipe_ctx *pipe_ctx);
-
---
-2.7.4
-