diff options
Diffstat (limited to 'common/recipes-kernel/linux/files/0824-drm-amd-dal-fix-stack-corruption-during-timing-sync.patch')
| -rw-r--r-- | common/recipes-kernel/linux/files/0824-drm-amd-dal-fix-stack-corruption-during-timing-sync.patch | 46 |
1 files changed, 46 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/files/0824-drm-amd-dal-fix-stack-corruption-during-timing-sync.patch b/common/recipes-kernel/linux/files/0824-drm-amd-dal-fix-stack-corruption-during-timing-sync.patch new file mode 100644 index 00000000..9298275b --- /dev/null +++ b/common/recipes-kernel/linux/files/0824-drm-amd-dal-fix-stack-corruption-during-timing-sync.patch @@ -0,0 +1,46 @@ +From e16926637ab52359896219cab89e4a4bd78c8e87 Mon Sep 17 00:00:00 2001 +From: Mykola Lysenko <Mykola.Lysenko@amd.com> +Date: Fri, 19 Feb 2016 05:45:19 -0500 +Subject: [PATCH 0824/1110] drm/amd/dal: fix stack corruption during timing + sync + +Issue happens when more than 3 displays enabled. During +fbdev initialization one surface allocated with smallest +size selected among available displays. This is why same +timing set on all displays and decided to enable timing sync. + +Array on stack was for 3 elements only. Now it is allocated +in heap with size relevant to number of targets + +Signed-off-by: Mykola Lysenko <Mykola.Lysenko@amd.com> +Acked-by: Harry Wentland <harry.wentland@amd.com> +--- + drivers/gpu/drm/amd/dal/dc/core/dc.c | 5 ++--- + 1 file changed, 2 insertions(+), 3 deletions(-) + +diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c +index 1d1cd89..666e248 100644 +--- a/drivers/gpu/drm/amd/dal/dc/core/dc.c ++++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c +@@ -470,7 +470,7 @@ static void program_timing_sync( + uint8_t j; + uint8_t group_size = 0; + uint8_t tg_count = ctx->res_ctx.pool.pipe_count; +- struct timing_generator *tg_set[3]; ++ struct timing_generator *tg_set[MAX_PIPES]; + + for (i = 0; i < tg_count; i++) { + if (!ctx->res_ctx.pipe_ctx[i].stream) +@@ -487,8 +487,7 @@ static void program_timing_sync( + continue; + + if (is_same_timing( +- &ctx->res_ctx.pipe_ctx[j].stream->public +- .timing, ++ &ctx->res_ctx.pipe_ctx[j].stream->public.timing, + &ctx->res_ctx.pipe_ctx[i].stream->public + .timing)) { + tg_set[group_size] = +-- +2.7.4 + |