diff options
Diffstat (limited to 'common/recipes-kernel/linux/files/0776-drm-amd-dal-Refactor-link_settings-to-public.patch')
| -rw-r--r-- | common/recipes-kernel/linux/files/0776-drm-amd-dal-Refactor-link_settings-to-public.patch | 760 |
1 files changed, 760 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/files/0776-drm-amd-dal-Refactor-link_settings-to-public.patch b/common/recipes-kernel/linux/files/0776-drm-amd-dal-Refactor-link_settings-to-public.patch new file mode 100644 index 00000000..f1be2b5e --- /dev/null +++ b/common/recipes-kernel/linux/files/0776-drm-amd-dal-Refactor-link_settings-to-public.patch @@ -0,0 +1,760 @@ +From 7630cf685d14c02a4e783d194c4f4c0918101b73 Mon Sep 17 00:00:00 2001 +From: Chris Park <Chris.Park@amd.com> +Date: Fri, 5 Feb 2016 15:52:42 -0500 +Subject: [PATCH 0776/1110] drm/amd/dal: Refactor link_settings to public + +Definition is moved from link_service_types.h to dc_types.h. +Given dc_ prefix for public struct. + +Signed-off-by: Chris Park <Chris.Park@amd.com> +Acked-by: Jordan Lazare <Jordan.Lazare@amd.com> +--- + drivers/gpu/drm/amd/dal/dc/core/dc_link.c | 6 +- + drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c | 61 ++++++------- + drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c | 2 +- + drivers/gpu/drm/amd/dal/dc/dc.h | 10 +-- + drivers/gpu/drm/amd/dal/dc/dc_dp_types.h | 100 +++++++++++++++++++++ + drivers/gpu/drm/amd/dal/dc/dc_types.h | 1 + + .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c | 4 +- + .../drm/amd/dal/dc/dce110/dce110_link_encoder.c | 6 +- + .../drm/amd/dal/dc/dce110/dce110_link_encoder.h | 4 +- + drivers/gpu/drm/amd/dal/dc/dm_services.h | 2 +- + drivers/gpu/drm/amd/dal/dc/inc/dc_link_dp.h | 8 +- + drivers/gpu/drm/amd/dal/dc/inc/link_encoder.h | 6 +- + drivers/gpu/drm/amd/dal/dc/inc/link_hwss.h | 2 +- + drivers/gpu/drm/amd/dal/dc/inc/stream_encoder.h | 2 +- + .../drm/amd/dal/dc/virtual/virtual_link_encoder.c | 4 +- + .../gpu/drm/amd/dal/include/bios_parser_types.h | 8 +- + .../gpu/drm/amd/dal/include/link_service_types.h | 80 +---------------- + 17 files changed, 168 insertions(+), 138 deletions(-) + create mode 100644 drivers/gpu/drm/amd/dal/dc/dc_dp_types.h + +diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c +index c1e3d33..9e04b45 100644 +--- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c ++++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c +@@ -1141,7 +1141,7 @@ static enum dc_status enable_link_dp(struct core_stream *stream) + enum dc_status status; + bool skip_video_pattern; + struct core_link *link = stream->sink->link; +- struct link_settings link_settings = {0}; ++ struct dc_link_settings link_settings = {0}; + enum dp_panel_mode panel_mode; + + /* get link settings for video mode timing */ +@@ -1215,7 +1215,7 @@ static void enable_link_hdmi(struct core_stream *stream) + stream->public.timing.flags.LTE_340MCSC_SCRAMBLE); + + dm_memset(&stream->sink->link->public.cur_link_settings, 0, +- sizeof(struct link_settings)); ++ sizeof(struct dc_link_settings)); + + link->link_enc->funcs->enable_tmds_output( + link->link_enc, +@@ -1341,7 +1341,7 @@ void core_link_resume(struct core_link *link) + + static struct fixed31_32 get_pbn_per_slot(struct core_stream *stream) + { +- struct link_settings *link_settings = ++ struct dc_link_settings *link_settings = + &stream->sink->link->public.cur_link_settings; + uint32_t link_rate_in_mbps = + link_settings->link_rate * LINK_RATE_REF_FREQ_IN_MHZ; +diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c +index 54d1f9f..f69743a 100644 +--- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c ++++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c +@@ -11,7 +11,7 @@ + #include "dpcd_defs.h" + + /* maximum pre emphasis level allowed for each voltage swing level*/ +-static const enum pre_emphasis voltage_swing_to_pre_emphasis[] = { ++static const enum dc_pre_emphasis voltage_swing_to_pre_emphasis[] = { + PRE_EMPHASIS_LEVEL3, + PRE_EMPHASIS_LEVEL2, + PRE_EMPHASIS_LEVEL1, +@@ -30,7 +30,7 @@ enum { + LINK_TRAINING_MAX_CR_RETRY = 100 + }; + +-static const struct link_settings link_training_fallback_table[] = { ++static const struct dc_link_settings link_training_fallback_table[] = { + /* 2160 Mbytes/sec*/ + { LANE_COUNT_FOUR, LINK_RATE_HIGH2, LINK_SPREAD_DISABLED }, + /* 1080 Mbytes/sec*/ +@@ -277,10 +277,10 @@ static void dpcd_set_lt_pattern_and_lane_settings( + dpcd_lt_buffer, + size_in_bytes + sizeof(dpcd_pattern.raw) ); + +- link->public.ln_setting = lt_settings->lane_settings[0]; ++ link->public.cur_lane_setting = lt_settings->lane_settings[0]; + } + +-static bool is_cr_done(enum lane_count ln_count, ++static bool is_cr_done(enum dc_lane_count ln_count, + union lane_status *dpcd_lane_status) + { + bool done = true; +@@ -294,7 +294,7 @@ static bool is_cr_done(enum lane_count ln_count, + + } + +-static bool is_ch_eq_done(enum lane_count ln_count, ++static bool is_ch_eq_done(enum dc_lane_count ln_count, + union lane_status *dpcd_lane_status, + union lane_align_status_updated *lane_status_updated) + { +@@ -342,10 +342,10 @@ static uint8_t get_nibble_at_index(const uint8_t *buf, + return nibble; + } + +-static enum pre_emphasis get_max_pre_emphasis_for_voltage_swing( +- enum voltage_swing voltage) ++static enum dc_pre_emphasis get_max_pre_emphasis_for_voltage_swing( ++ enum dc_voltage_swing voltage) + { +- enum pre_emphasis pre_emphasis; ++ enum dc_pre_emphasis pre_emphasis; + pre_emphasis = PRE_EMPHASIS_MAX_LEVEL; + + if (voltage <= VOLTAGE_SWING_MAX_LEVEL) +@@ -360,7 +360,7 @@ static void find_max_drive_settings( + struct link_training_settings *max_lt_setting) + { + uint32_t lane; +- struct lane_settings max_requested; ++ struct dc_lane_settings max_requested; + + max_requested.VOLTAGE_SWING = + link_training_setting-> +@@ -514,10 +514,10 @@ static void get_lane_status_and_drive_settings( + lane++) { + + request_settings.lane_settings[lane].VOLTAGE_SWING = +- (enum voltage_swing)(dpcd_lane_adjust[lane].bits. ++ (enum dc_voltage_swing)(dpcd_lane_adjust[lane].bits. + VOLTAGE_SWING_LANE); + request_settings.lane_settings[lane].PRE_EMPHASIS = +- (enum pre_emphasis)(dpcd_lane_adjust[lane].bits. ++ (enum dc_pre_emphasis)(dpcd_lane_adjust[lane].bits. + PRE_EMPHASIS_LANE); + } + +@@ -599,7 +599,7 @@ static void dpcd_set_lane_settings( + dpcd_lane[0].bits.MAX_SWING_REACHED, + dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED); + +- link->public.ln_setting = link_training_setting->lane_settings[0]; ++ link->public.cur_lane_setting = link_training_setting->lane_settings[0]; + + } + +@@ -633,7 +633,7 @@ static bool perform_post_lt_adj_req_sequence( + struct core_link *link, + struct link_training_settings *lt_settings) + { +- enum lane_count lane_count = ++ enum dc_lane_count lane_count = + lt_settings->link_settings.lane_count; + + uint32_t adj_req_count; +@@ -753,7 +753,7 @@ static bool perform_channel_equalization_sequence( + struct link_training_settings req_settings; + enum hw_dp_training_pattern hw_tr_pattern; + uint32_t retries_ch_eq; +- enum lane_count lane_count = lt_settings->link_settings.lane_count; ++ enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; + union lane_align_status_updated dpcd_lane_status_updated = {{0}}; + union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {{{0}}};; + +@@ -816,7 +816,7 @@ static bool perform_clock_recovery_sequence( + uint32_t retry_count; + uint32_t lane; + struct link_training_settings req_settings; +- enum lane_count lane_count = ++ enum dc_lane_count lane_count = + lt_settings->link_settings.lane_count; + enum hw_dp_training_pattern hw_tr_pattern = HW_DP_TRAINING_PATTERN_1; + union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX]; +@@ -924,7 +924,7 @@ static bool perform_clock_recovery_sequence( + + bool perform_link_training( + struct core_link *link, +- const struct link_settings *link_setting, ++ const struct dc_link_settings *link_setting, + bool skip_video_pattern) + { + bool status; +@@ -1027,8 +1027,8 @@ static bool perform_clock_recovery_sequence( + + /*TODO add more check to see if link support request link configuration */ + static bool is_link_setting_supported( +- const struct link_settings *link_setting, +- const struct link_settings *max_link_setting) ++ const struct dc_link_settings *link_setting, ++ const struct dc_link_settings *max_link_setting) + { + if (link_setting->lane_count > max_link_setting->lane_count || + link_setting->link_rate > max_link_setting->link_rate) +@@ -1042,23 +1042,24 @@ static const uint32_t get_link_training_fallback_table_len( + return ARRAY_SIZE(link_training_fallback_table); + } + +-static const struct link_settings *get_link_training_fallback_table( ++static const struct dc_link_settings *get_link_training_fallback_table( + struct core_link *link, uint32_t i) + { + return &link_training_fallback_table[i]; + } + +-static bool exceeded_limit_link_setting(const struct link_settings *link_setting, +- const struct link_settings *limit_link_setting) ++static bool exceeded_limit_link_setting( ++ const struct dc_link_settings *link_setting, ++ const struct dc_link_settings *limit_link_setting) + { + return (link_setting->lane_count * link_setting->link_rate + > limit_link_setting->lane_count * limit_link_setting->link_rate ? + true : false); + } + +-static enum link_rate get_max_link_rate(struct core_link *link) ++static enum dc_link_rate get_max_link_rate(struct core_link *link) + { +- enum link_rate max_link_rate = LINK_RATE_HIGH; ++ enum dc_link_rate max_link_rate = LINK_RATE_HIGH; + + if (link->link_enc->features.flags.bits.IS_HBR2_CAPABLE) + max_link_rate = LINK_RATE_HIGH2; +@@ -1071,12 +1072,12 @@ static enum link_rate get_max_link_rate(struct core_link *link) + + bool dp_hbr_verify_link_cap( + struct core_link *link, +- struct link_settings *known_limit_link_setting) ++ struct dc_link_settings *known_limit_link_setting) + { +- struct link_settings max_link_cap = {0}; ++ struct dc_link_settings max_link_cap = {0}; + bool success; + bool skip_link_training; +- const struct link_settings *cur; ++ const struct dc_link_settings *cur; + bool skip_video_pattern; + uint32_t i; + +@@ -1212,7 +1213,7 @@ static uint32_t bandwidth_in_kbps_from_timing( + } + + static uint32_t bandwidth_in_kbps_from_link_settings( +- const struct link_settings *link_setting) ++ const struct dc_link_settings *link_setting) + { + uint32_t link_rate_in_kbps = link_setting->link_rate * + LINK_RATE_REF_FREQ_IN_KHZ; +@@ -1233,7 +1234,7 @@ bool dp_validate_mode_timing( + uint32_t req_bw; + uint32_t max_bw; + +- const struct link_settings *link_setting; ++ const struct dc_link_settings *link_setting; + + /*always DP fail safe mode*/ + if (timing->pix_clk_khz == (uint32_t)25175 && +@@ -1275,10 +1276,10 @@ bool dp_validate_mode_timing( + } + + void decide_link_settings(struct core_stream *stream, +- struct link_settings *link_setting) ++ struct dc_link_settings *link_setting) + { + +- const struct link_settings *cur_ls; ++ const struct dc_link_settings *cur_ls; + struct core_link* link; + uint32_t req_bw; + uint32_t link_bw; +diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c +index 2d78e52..a3e0da9 100644 +--- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c ++++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c +@@ -54,7 +54,7 @@ void dp_receiver_power_ctrl(struct core_link *link, bool on) + void dp_enable_link_phy( + struct core_link *link, + enum signal_type signal, +- const struct link_settings *link_settings) ++ const struct dc_link_settings *link_settings) + { + struct link_encoder *link_enc = link->link_enc; + +diff --git a/drivers/gpu/drm/amd/dal/dc/dc.h b/drivers/gpu/drm/amd/dal/dc/dc.h +index 45d39c7..c09af66 100644 +--- a/drivers/gpu/drm/amd/dal/dc/dc.h ++++ b/drivers/gpu/drm/amd/dal/dc/dc.h +@@ -284,11 +284,11 @@ struct dc_link { + /* caps is the same as reported_link_cap. link_traing use + * reported_link_cap. Will clean up. TODO + */ +- struct link_settings reported_link_cap; +- struct link_settings verified_link_cap; +- struct link_settings max_link_setting; +- struct link_settings cur_link_settings; +- struct lane_settings ln_setting; ++ struct dc_link_settings reported_link_cap; ++ struct dc_link_settings verified_link_cap; ++ struct dc_link_settings max_link_setting; ++ struct dc_link_settings cur_link_settings; ++ struct dc_lane_settings cur_lane_setting; + }; + + /* +diff --git a/drivers/gpu/drm/amd/dal/dc/dc_dp_types.h b/drivers/gpu/drm/amd/dal/dc/dc_dp_types.h +new file mode 100644 +index 0000000..e271ea9 +--- /dev/null ++++ b/drivers/gpu/drm/amd/dal/dc/dc_dp_types.h +@@ -0,0 +1,100 @@ ++/* ++ * Copyright 2016 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in ++ * all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ * ++ * Authors: AMD ++ * ++ */ ++ ++#ifndef DC_DP_TYPES_H ++#define DC_DP_TYPES_H ++ ++enum dc_lane_count { ++ LANE_COUNT_UNKNOWN = 0, ++ LANE_COUNT_ONE = 1, ++ LANE_COUNT_TWO = 2, ++ LANE_COUNT_FOUR = 4, ++ LANE_COUNT_EIGHT = 8, ++ LANE_COUNT_DP_MAX = LANE_COUNT_FOUR ++}; ++ ++/* This is actually a reference clock (27MHz) multiplier ++ * 162MBps bandwidth for 1.62GHz like rate, ++ * 270MBps for 2.70GHz, ++ * 324MBps for 3.24Ghz, ++ * 540MBps for 5.40GHz ++ * 810MBps for 8.10GHz ++ */ ++enum dc_link_rate { ++ LINK_RATE_UNKNOWN = 0, ++ LINK_RATE_LOW = 0x06, ++ LINK_RATE_HIGH = 0x0A, ++ LINK_RATE_RBR2 = 0x0C, ++ LINK_RATE_HIGH2 = 0x14, ++ LINK_RATE_HIGH3 = 0x1E ++}; ++ ++enum dc_link_spread { ++ LINK_SPREAD_DISABLED = 0x00, ++ /* 0.5 % downspread 30 kHz */ ++ LINK_SPREAD_05_DOWNSPREAD_30KHZ = 0x10, ++ /* 0.5 % downspread 33 kHz */ ++ LINK_SPREAD_05_DOWNSPREAD_33KHZ = 0x11 ++}; ++ ++enum dc_voltage_swing { ++ VOLTAGE_SWING_LEVEL0 = 0, /* direct HW translation! */ ++ VOLTAGE_SWING_LEVEL1, ++ VOLTAGE_SWING_LEVEL2, ++ VOLTAGE_SWING_LEVEL3, ++ VOLTAGE_SWING_MAX_LEVEL = VOLTAGE_SWING_LEVEL3 ++}; ++ ++enum dc_pre_emphasis { ++ PRE_EMPHASIS_DISABLED = 0, /* direct HW translation! */ ++ PRE_EMPHASIS_LEVEL1, ++ PRE_EMPHASIS_LEVEL2, ++ PRE_EMPHASIS_LEVEL3, ++ PRE_EMPHASIS_MAX_LEVEL = PRE_EMPHASIS_LEVEL3 ++}; ++/* Post Cursor 2 is optional for transmitter ++ * and it applies only to the main link operating at HBR2 ++ */ ++enum dc_post_cursor2 { ++ POST_CURSOR2_DISABLED = 0, /* direct HW translation! */ ++ POST_CURSOR2_LEVEL1, ++ POST_CURSOR2_LEVEL2, ++ POST_CURSOR2_LEVEL3, ++ POST_CURSOR2_MAX_LEVEL = POST_CURSOR2_LEVEL3, ++}; ++ ++struct dc_link_settings { ++ enum dc_lane_count lane_count; ++ enum dc_link_rate link_rate; ++ enum dc_link_spread link_spread; ++}; ++ ++struct dc_lane_settings { ++ enum dc_voltage_swing VOLTAGE_SWING; ++ enum dc_pre_emphasis PRE_EMPHASIS; ++ enum dc_post_cursor2 POST_CURSOR2; ++}; ++ ++#endif /* DC_DP_TYPES_H */ +diff --git a/drivers/gpu/drm/amd/dal/dc/dc_types.h b/drivers/gpu/drm/amd/dal/dc/dc_types.h +index 2abdda7..1701953 100644 +--- a/drivers/gpu/drm/amd/dal/dc/dc_types.h ++++ b/drivers/gpu/drm/amd/dal/dc/dc_types.h +@@ -28,6 +28,7 @@ + #include "fixed32_32.h" + #include "fixed31_32.h" + #include "irq_types.h" ++#include "dc_dp_types.h" + + /* forward declarations */ + struct dc; +diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c +index e721398..cee25d8 100644 +--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c ++++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c +@@ -616,7 +616,7 @@ static void update_info_frame(struct core_stream *stream) + + static void enable_stream(struct core_stream *stream) + { +- enum lane_count lane_count = ++ enum dc_lane_count lane_count = + stream->sink->link->public.cur_link_settings.lane_count; + + struct dc_crtc_timing *timing = &stream->public.timing; +@@ -697,7 +697,7 @@ static void disable_stream(struct core_stream *stream) + } + + static void unblank_stream(struct core_stream *stream, +- struct link_settings *link_settings) ++ struct dc_link_settings *link_settings) + { + struct encoder_unblank_param params = { { 0 } }; + +diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c +index 7f663de..3c78431 100644 +--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c ++++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c +@@ -564,7 +564,7 @@ static uint8_t get_frontend_source( + + static void configure_encoder( + struct dce110_link_encoder *enc110, +- const struct link_settings *link_settings) ++ const struct dc_link_settings *link_settings) + { + struct dc_context *ctx = enc110->base.ctx; + uint32_t addr; +@@ -1351,7 +1351,7 @@ void dce110_link_encoder_enable_tmds_output( + /* enables DP PHY output */ + void dce110_link_encoder_enable_dp_output( + struct link_encoder *enc, +- const struct link_settings *link_settings, ++ const struct dc_link_settings *link_settings, + enum clock_source_id clock_source) + { + struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); +@@ -1394,7 +1394,7 @@ void dce110_link_encoder_enable_dp_output( + /* enables DP PHY output in MST mode */ + void dce110_link_encoder_enable_dp_mst_output( + struct link_encoder *enc, +- const struct link_settings *link_settings, ++ const struct dc_link_settings *link_settings, + enum clock_source_id clock_source) + { + struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); +diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h +index 1269833..64a81f2 100644 +--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h ++++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h +@@ -107,13 +107,13 @@ void dce110_link_encoder_enable_tmds_output( + /* enables DP PHY output */ + void dce110_link_encoder_enable_dp_output( + struct link_encoder *enc, +- const struct link_settings *link_settings, ++ const struct dc_link_settings *link_settings, + enum clock_source_id clock_source); + + /* enables DP PHY output in MST mode */ + void dce110_link_encoder_enable_dp_mst_output( + struct link_encoder *enc, +- const struct link_settings *link_settings, ++ const struct dc_link_settings *link_settings, + enum clock_source_id clock_source); + + /* disable PHY output */ +diff --git a/drivers/gpu/drm/amd/dal/dc/dm_services.h b/drivers/gpu/drm/amd/dal/dc/dm_services.h +index 33f700e..604aa43 100644 +--- a/drivers/gpu/drm/amd/dal/dc/dm_services.h ++++ b/drivers/gpu/drm/amd/dal/dc/dm_services.h +@@ -282,7 +282,7 @@ struct dc_pp_single_disp_config { + uint32_t src_width; + uint32_t v_refresh; + uint32_t sym_clock; /* HDMI only */ +- struct link_settings link_settings; /* DP only */ ++ struct dc_link_settings link_settings; /* DP only */ + }; + + struct dc_pp_display_configuration { +diff --git a/drivers/gpu/drm/amd/dal/dc/inc/dc_link_dp.h b/drivers/gpu/drm/amd/dal/dc/inc/dc_link_dp.h +index 682c0b4..a0ab6b3 100644 +--- a/drivers/gpu/drm/amd/dal/dc/inc/dc_link_dp.h ++++ b/drivers/gpu/drm/amd/dal/dc/inc/dc_link_dp.h +@@ -28,11 +28,11 @@ + + struct core_link; + struct core_stream; +-struct link_settings; ++struct dc_link_settings; + + bool dp_hbr_verify_link_cap( + struct core_link *link, +- struct link_settings *known_limit_link_setting); ++ struct dc_link_settings *known_limit_link_setting); + + bool dp_validate_mode_timing( + struct core_link *link, +@@ -40,11 +40,11 @@ bool dp_validate_mode_timing( + + void decide_link_settings( + struct core_stream *stream, +- struct link_settings *link_setting); ++ struct dc_link_settings *link_setting); + + bool perform_link_training( + struct core_link *link, +- const struct link_settings *link_setting, ++ const struct dc_link_settings *link_setting, + bool skip_video_pattern); + + bool is_mst_supported(struct core_link *link); +diff --git a/drivers/gpu/drm/amd/dal/dc/inc/link_encoder.h b/drivers/gpu/drm/amd/dal/dc/inc/link_encoder.h +index 1f53c8f..54e75dc 100644 +--- a/drivers/gpu/drm/amd/dal/dc/inc/link_encoder.h ++++ b/drivers/gpu/drm/amd/dal/dc/inc/link_encoder.h +@@ -16,7 +16,7 @@ struct dc_context; + struct adapter_service; + struct encoder_set_dp_phy_pattern_param; + struct link_mst_stream_allocation_table; +-struct link_settings; ++struct dc_link_settings; + struct link_training_settings; + struct core_stream; + +@@ -94,10 +94,10 @@ struct link_encoder_funcs { + bool dual_link, + uint32_t pixel_clock); + void (*enable_dp_output)(struct link_encoder *enc, +- const struct link_settings *link_settings, ++ const struct dc_link_settings *link_settings, + enum clock_source_id clock_source); + void (*enable_dp_mst_output)(struct link_encoder *enc, +- const struct link_settings *link_settings, ++ const struct dc_link_settings *link_settings, + enum clock_source_id clock_source); + void (*disable_output)(struct link_encoder *link_enc, + enum signal_type signal); +diff --git a/drivers/gpu/drm/amd/dal/dc/inc/link_hwss.h b/drivers/gpu/drm/amd/dal/dc/inc/link_hwss.h +index d9a48c0..551caa3 100644 +--- a/drivers/gpu/drm/amd/dal/dc/inc/link_hwss.h ++++ b/drivers/gpu/drm/amd/dal/dc/inc/link_hwss.h +@@ -43,7 +43,7 @@ enum dc_status core_link_write_dpcd( + void dp_enable_link_phy( + struct core_link *link, + enum signal_type signal, +- const struct link_settings *link_settings); ++ const struct dc_link_settings *link_settings); + + void dp_receiver_power_ctrl(struct core_link *link, bool on); + +diff --git a/drivers/gpu/drm/amd/dal/dc/inc/stream_encoder.h b/drivers/gpu/drm/amd/dal/dc/inc/stream_encoder.h +index 6bb1d00..47cf6de 100644 +--- a/drivers/gpu/drm/amd/dal/dc/inc/stream_encoder.h ++++ b/drivers/gpu/drm/amd/dal/dc/inc/stream_encoder.h +@@ -35,7 +35,7 @@ struct encoder_info_frame { + + struct encoder_unblank_param { + struct hw_crtc_timing crtc_timing; +- struct link_settings link_settings; ++ struct dc_link_settings link_settings; + }; + + struct encoder_set_dp_phy_pattern_param { +diff --git a/drivers/gpu/drm/amd/dal/dc/virtual/virtual_link_encoder.c b/drivers/gpu/drm/amd/dal/dc/virtual/virtual_link_encoder.c +index ade443d..36886a4 100644 +--- a/drivers/gpu/drm/amd/dal/dc/virtual/virtual_link_encoder.c ++++ b/drivers/gpu/drm/amd/dal/dc/virtual/virtual_link_encoder.c +@@ -49,12 +49,12 @@ static void virtual_link_encoder_enable_tmds_output( + + static void virtual_link_encoder_enable_dp_output( + struct link_encoder *enc, +- const struct link_settings *link_settings, ++ const struct dc_link_settings *link_settings, + enum clock_source_id clock_source) {} + + static void virtual_link_encoder_enable_dp_mst_output( + struct link_encoder *enc, +- const struct link_settings *link_settings, ++ const struct dc_link_settings *link_settings, + enum clock_source_id clock_source) {} + + static void virtual_link_encoder_disable_output( +diff --git a/drivers/gpu/drm/amd/dal/include/bios_parser_types.h b/drivers/gpu/drm/amd/dal/include/bios_parser_types.h +index 550ac87..83766fe 100644 +--- a/drivers/gpu/drm/amd/dal/include/bios_parser_types.h ++++ b/drivers/gpu/drm/amd/dal/include/bios_parser_types.h +@@ -96,7 +96,7 @@ struct bp_encoder_control { + enum engine_id engine_id; + enum transmitter transmitter; + enum signal_type signal; +- enum lane_count lanes_number; ++ enum dc_lane_count lanes_number; + enum dc_color_depth color_depth; + bool enable_dp_audio; + uint32_t pixel_clock; /* khz */ +@@ -105,8 +105,8 @@ struct bp_encoder_control { + struct bp_external_encoder_control { + enum bp_external_encoder_control_action action; + enum engine_id engine_id; +- enum link_rate link_rate; +- enum lane_count lanes_number; ++ enum dc_link_rate link_rate; ++ enum dc_lane_count lanes_number; + enum signal_type signal; + enum dc_color_depth color_depth; + bool coherent; +@@ -130,7 +130,7 @@ struct bp_transmitter_control { + enum bp_transmitter_control_action action; + enum engine_id engine_id; + enum transmitter transmitter; /* PhyId */ +- enum lane_count lanes_number; ++ enum dc_lane_count lanes_number; + enum clock_source_id pll_id; /* needed for DCE 4.0 */ + enum signal_type signal; + enum dc_color_depth color_depth; /* not used for DCE6.0 */ +diff --git a/drivers/gpu/drm/amd/dal/include/link_service_types.h b/drivers/gpu/drm/amd/dal/include/link_service_types.h +index 7db598b..a14c4af 100644 +--- a/drivers/gpu/drm/amd/dal/include/link_service_types.h ++++ b/drivers/gpu/drm/amd/dal/include/link_service_types.h +@@ -52,33 +52,6 @@ struct link_validation_flags { + uint32_t START_OF_VALIDATION:1; + }; + +-/* Post Cursor 2 is optional for transmitter +- * and it applies only to the main link operating at HBR2 +- */ +-enum post_cursor2 { +- POST_CURSOR2_DISABLED = 0, /* direct HW translation! */ +- POST_CURSOR2_LEVEL1, +- POST_CURSOR2_LEVEL2, +- POST_CURSOR2_LEVEL3, +- POST_CURSOR2_MAX_LEVEL = POST_CURSOR2_LEVEL3, +-}; +- +-enum voltage_swing { +- VOLTAGE_SWING_LEVEL0 = 0, /* direct HW translation! */ +- VOLTAGE_SWING_LEVEL1, +- VOLTAGE_SWING_LEVEL2, +- VOLTAGE_SWING_LEVEL3, +- VOLTAGE_SWING_MAX_LEVEL = VOLTAGE_SWING_LEVEL3 +-}; +- +-enum pre_emphasis { +- PRE_EMPHASIS_DISABLED = 0, /* direct HW translation! */ +- PRE_EMPHASIS_LEVEL1, +- PRE_EMPHASIS_LEVEL2, +- PRE_EMPHASIS_LEVEL3, +- PRE_EMPHASIS_MAX_LEVEL = PRE_EMPHASIS_LEVEL3 +-}; +- + enum dpcd_value_mask { + DPCD_VALUE_MASK_MAX_LANE_COUNT_LANE_COUNT = 0x1F, + DPCD_VALUE_MASK_MAX_LANE_COUNT_TPS3_SUPPORTED = 0x40, +@@ -109,43 +82,6 @@ enum edp_revision { + EDP_REVISION_13 = 0x02 + }; + +-enum lane_count { +- LANE_COUNT_UNKNOWN = 0, +- LANE_COUNT_ONE = 1, +- LANE_COUNT_TWO = 2, +- LANE_COUNT_FOUR = 4, +- LANE_COUNT_EIGHT = 8, +- LANE_COUNT_DP_MAX = LANE_COUNT_FOUR +-}; +- +-/* This is actually a reference clock (27MHz) multiplier +- * 162MBps bandwidth for 1.62GHz like rate, +- * 270MBps for 2.70GHz, +- * 324MBps for 3.24Ghz, +- * 540MBps for 5.40GHz +- * 810MBps for 8.10GHz +- */ +-enum link_rate { +- LINK_RATE_UNKNOWN = 0, +- LINK_RATE_LOW = 0x06, +- LINK_RATE_HIGH = 0x0A, +- LINK_RATE_RBR2 = 0x0C, +- LINK_RATE_HIGH2 = 0x14, +- LINK_RATE_HIGH3 = 0x1E +-}; +- +-enum { +- LINK_RATE_REF_FREQ_IN_KHZ = 27000 /*27MHz*/ +-}; +- +-enum link_spread { +- LINK_SPREAD_DISABLED = 0x00, +- /* 0.5 % downspread 30 kHz */ +- LINK_SPREAD_05_DOWNSPREAD_30KHZ = 0x10, +- /* 0.5 % downspread 33 kHz */ +- LINK_SPREAD_05_DOWNSPREAD_33KHZ = 0x11 +-}; +- + /* DPCD_ADDR_DOWNSTREAM_PORT_PRESENT register value */ + union dpcd_downstream_port { + struct { +@@ -186,21 +122,13 @@ union dpcd_sink_count { + uint8_t raw; + }; + +-struct link_settings { +- enum lane_count lane_count; +- enum link_rate link_rate; +- enum link_spread link_spread; +-}; +- +-struct lane_settings { +- enum voltage_swing VOLTAGE_SWING; +- enum pre_emphasis PRE_EMPHASIS; +- enum post_cursor2 POST_CURSOR2; ++enum { ++ LINK_RATE_REF_FREQ_IN_KHZ = 27000 /*27MHz*/ + }; + + struct link_training_settings { +- struct link_settings link_settings; +- struct lane_settings lane_settings[LANE_COUNT_DP_MAX]; ++ struct dc_link_settings link_settings; ++ struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]; + bool allow_invalid_msa_timing_param; + }; + +-- +2.7.4 + |