1 files changed, 332 insertions, 0 deletions

diff --git a/common/recipes-kernel/linux/files/0772-drm-amd-dal-Move-link-settings-to-public-interface.patch b/common/recipes-kernel/linux/files/0772-drm-amd-dal-Move-link-settings-to-public-interface.patch
new file mode 100644
index 00000000..399d87e3
--- /dev/null
+++ b/common/recipes-kernel/linux/files/0772-drm-amd-dal-Move-link-settings-to-public-interface.patch
@@ -0,0 +1,332 @@
+From 5f22fe3b2e8832d59299095cd32be5a95ebe8bea Mon Sep 17 00:00:00 2001
+From: Chris Park <Chris.Park@amd.com>
+Date: Fri, 5 Feb 2016 12:43:22 -0500
+Subject: [PATCH 0772/1110] drm/amd/dal: Move link settings to public interface
+
+DC to move lane_settings to public
+
+Signed-off-by: Chris Park <Chris.Park@amd.com>
+Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
+---
+ drivers/gpu/drm/amd/dal/dc/core/dc_link.c          |  8 ++--
+ drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c       | 55 +++++++++++-----------
+ drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c     |  4 +-
+ drivers/gpu/drm/amd/dal/dc/core/dc_resource.c      |  2 +-
+ drivers/gpu/drm/amd/dal/dc/dc.h                    |  9 ++++
+ .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c    |  5 +-
+ drivers/gpu/drm/amd/dal/dc/inc/core_types.h        |  7 ---
+ 7 files changed, 47 insertions(+), 43 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
+index b0ef028..c1e3d33 100644
+--- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
++++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
+@@ -1160,7 +1160,7 @@ static enum dc_status enable_link_dp(struct core_stream *stream)
+ 			skip_video_pattern = false;
+ 
+ 	if (perform_link_training(link, &link_settings, skip_video_pattern)) {
+-		link->cur_link_settings = link_settings;
++		link->public.cur_link_settings = link_settings;
+ 		status = DC_OK;
+ 	}
+ 	else
+@@ -1176,7 +1176,7 @@ static enum dc_status enable_link_dp_mst(struct core_stream *stream)
+ 	/* sink signal type after MST branch is MST. Multiple MST sinks
+ 	 * share one link. Link DP PHY is enable or training only once.
+ 	 */
+-	if (link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN)
++	if (link->public.cur_link_settings.lane_count != LANE_COUNT_UNKNOWN)
+ 		return DC_OK;
+ 
+ 	return enable_link_dp(stream);
+@@ -1214,7 +1214,7 @@ static void enable_link_hdmi(struct core_stream *stream)
+ 			normalized_pix_clk,
+ 			stream->public.timing.flags.LTE_340MCSC_SCRAMBLE);
+ 
+-	dm_memset(&stream->sink->link->cur_link_settings, 0,
++	dm_memset(&stream->sink->link->public.cur_link_settings, 0,
+ 			sizeof(struct link_settings));
+ 
+ 	link->link_enc->funcs->enable_tmds_output(
+@@ -1342,7 +1342,7 @@ void core_link_resume(struct core_link *link)
+ static struct fixed31_32 get_pbn_per_slot(struct core_stream *stream)
+ {
+ 	struct link_settings *link_settings =
+-			&stream->sink->link->cur_link_settings;
++			&stream->sink->link->public.cur_link_settings;
+ 	uint32_t link_rate_in_mbps =
+ 			link_settings->link_rate * LINK_RATE_REF_FREQ_IN_MHZ;
+ 	struct fixed31_32 mbps = dal_fixed31_32_from_int(
+diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
+index 83d5e03..54d1f9f 100644
+--- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
++++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
+@@ -277,7 +277,7 @@ static void dpcd_set_lt_pattern_and_lane_settings(
+ 				dpcd_lt_buffer,
+ 				size_in_bytes + sizeof(dpcd_pattern.raw) );
+ 
+-	link->ln_setting = lt_settings->lane_settings[0];
++	link->public.ln_setting = lt_settings->lane_settings[0];
+ }
+ 
+ static bool is_cr_done(enum lane_count ln_count,
+@@ -599,7 +599,7 @@ static void dpcd_set_lane_settings(
+ 		dpcd_lane[0].bits.MAX_SWING_REACHED,
+ 		dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
+ 
+-	link->ln_setting = link_training_setting->lane_settings[0];
++	link->public.ln_setting = link_training_setting->lane_settings[0];
+ 
+ }
+ 
+@@ -1142,7 +1142,7 @@ bool dp_hbr_verify_link_cap(
+ 		}
+ 
+ 		if (success)
+-			link->verified_link_cap = *cur;
++			link->public.verified_link_cap = *cur;
+ 
+ 		/* always disable the link before trying another
+ 		 * setting or before returning we'll enable it later
+@@ -1158,14 +1158,14 @@ bool dp_hbr_verify_link_cap(
+ 		/* If all LT fails for all settings,
+ 		 * set verified = failed safe (1 lane low)
+ 		 */
+-		link->verified_link_cap.lane_count = LANE_COUNT_ONE;
+-		link->verified_link_cap.link_rate = LINK_RATE_LOW;
++		link->public.verified_link_cap.lane_count = LANE_COUNT_ONE;
++		link->public.verified_link_cap.link_rate = LINK_RATE_LOW;
+ 
+-		link->verified_link_cap.link_spread =
++		link->public.verified_link_cap.link_spread =
+ 		LINK_SPREAD_DISABLED;
+ 	}
+ 
+-	link->max_link_setting = link->verified_link_cap;
++	link->public.max_link_setting = link->public.verified_link_cap;
+ 
+ 	return success;
+ }
+@@ -1244,12 +1244,12 @@ bool dp_validate_mode_timing(
+ 	/* For static validation we always use reported
+ 	 * link settings for other cases, when no modelist
+ 	 * changed we can use verified link setting*/
+-	link_setting = &link->reported_link_cap;
++	link_setting = &link->public.reported_link_cap;
+ 
+ 	/* TODO: DYNAMIC_VALIDATION needs to be implemented */
+ 	/*if (flags.DYNAMIC_VALIDATION == 1 &&
+-		link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN)
+-		link_setting = &link->verified_link_cap;
++		link->public.verified_link_cap.lane_count != LANE_COUNT_UNKNOWN)
++		link_setting = &link->public.verified_link_cap;
+ 	*/
+ 
+ 	req_bw = bandwidth_in_kbps_from_timing(timing);
+@@ -1292,15 +1292,15 @@ void decide_link_settings(struct core_stream *stream,
+ 	 */
+ 	link = stream->sink->link;
+ 
+-	if ((link->reported_link_cap.lane_count != LANE_COUNT_UNKNOWN) &&
+-		(link->reported_link_cap.link_rate <=
+-				link->verified_link_cap.link_rate)) {
++	if ((link->public.reported_link_cap.lane_count != LANE_COUNT_UNKNOWN) &&
++		(link->public.reported_link_cap.link_rate <=
++				link->public.verified_link_cap.link_rate)) {
+ 
+ 		link_bw = bandwidth_in_kbps_from_link_settings(
+-				&link->reported_link_cap);
++				&link->public.reported_link_cap);
+ 
+ 		if (req_bw < link_bw) {
+-			*link_setting = link->reported_link_cap;
++			*link_setting = link->public.reported_link_cap;
+ 			return;
+ 		}
+ 	}
+@@ -1319,7 +1319,7 @@ void decide_link_settings(struct core_stream *stream,
+ 		if (req_bw < link_bw) {
+ 			if (is_link_setting_supported(
+ 				cur_ls,
+-				&link->max_link_setting)) {
++				&link->public.max_link_setting)) {
+ 				*link_setting = *cur_ls;
+ 				return;
+ 			}
+@@ -1327,10 +1327,10 @@ void decide_link_settings(struct core_stream *stream,
+ 	}
+ 
+ 	BREAK_TO_DEBUGGER();
+-	ASSERT(link->verified_link_cap.lane_count !=
++	ASSERT(link->public.verified_link_cap.lane_count !=
+ 		LANE_COUNT_UNKNOWN);
+ 
+-	*link_setting = link->verified_link_cap;
++	*link_setting = link->public.verified_link_cap;
+ }
+ 
+ /*************************Short Pulse IRQ***************************/
+@@ -1349,7 +1349,7 @@ static bool hpd_rx_irq_check_link_loss_status(
+ 	sink_status_changed = false;
+ 	return_code = false;
+ 
+-	if (link->cur_link_settings.lane_count == 0)
++	if (link->public.cur_link_settings.lane_count == 0)
+ 		return return_code;
+ 	/*1. Check that we can handle interrupt: Not in FS DOS,
+ 	 *  Not in "Display Timeout" state, Link is trained.
+@@ -1375,7 +1375,7 @@ static bool hpd_rx_irq_check_link_loss_status(
+ 
+ 		/*parse lane status*/
+ 		for (lane = 0;
+-			lane < link->cur_link_settings.lane_count;
++			lane < link->public.cur_link_settings.lane_count;
+ 			lane++) {
+ 
+ 			/* check status of lanes 0,1
+@@ -1441,7 +1441,7 @@ static bool allow_hpd_rx_irq(const struct core_link *link)
+ 	 * 3) We know we're dealing with an active dongle
+ 	 */
+ 
+-	if ((link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
++	if ((link->public.cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
+ 		(link->public.type == dc_connection_mst_branch) ||
+ 		is_dp_active_dongle(link))
+ 		return true;
+@@ -1502,7 +1502,8 @@ bool dc_link_handle_hpd_rx_irq(const struct dc_link *dc_link)
+ 	if (hpd_rx_irq_check_link_loss_status(
+ 		link,
+ 		&hpd_irq_dpcd_data)) {
+-		perform_link_training(link, &link->cur_link_settings, true);
++		perform_link_training(link,
++			&link->public.cur_link_settings, true);
+ 		status = false;
+ 	}
+ 
+@@ -1708,11 +1709,11 @@ static void retrieve_link_cap(struct core_link *link)
+ 	link->dpcd_caps.max_down_spread.raw = dpcd_data[
+ 		DPCD_ADDRESS_MAX_DOWNSPREAD - DPCD_ADDRESS_DPCD_REV];
+ 
+-	link->reported_link_cap.lane_count =
++	link->public.reported_link_cap.lane_count =
+ 		link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT;
+-	link->reported_link_cap.link_rate = dpcd_data[
++	link->public.reported_link_cap.link_rate = dpcd_data[
+ 		DPCD_ADDRESS_MAX_LINK_RATE - DPCD_ADDRESS_DPCD_REV];
+-	link->reported_link_cap.link_spread =
++	link->public.reported_link_cap.link_spread =
+ 		link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ?
+ 		LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
+ 
+@@ -1753,10 +1754,10 @@ void detect_dp_sink_caps(struct core_link *link)
+ 	 */
+ 
+ 	if (is_mst_supported(link)) {
+-		link->verified_link_cap = link->reported_link_cap;
++		link->public.verified_link_cap = link->public.reported_link_cap;
+ 	} else {
+ 		dp_hbr_verify_link_cap(link,
+-			&link->reported_link_cap);
++			&link->public.reported_link_cap);
+ 	}
+ 	/* TODO save sink caps in link->sink */
+ }
+diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
+index e8f4ec8..2d78e52 100644
+--- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
++++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
+@@ -89,8 +89,8 @@ void dp_disable_link_phy(struct core_link *link, enum signal_type signal)
+ 	link->link_enc->funcs->disable_output(link->link_enc, signal);
+ 
+ 	/* Clear current link setting.*/
+-	dm_memset(&link->cur_link_settings, 0,
+-			sizeof(link->cur_link_settings));
++	dm_memset(&link->public.cur_link_settings, 0,
++			sizeof(link->public.cur_link_settings));
+ }
+ 
+ void dp_disable_link_phy_mst(struct core_link *link, struct core_stream *stream)
+diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
+index 8cb756e..6375678 100644
+--- a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
++++ b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
+@@ -500,7 +500,7 @@ static void fill_display_configs(
+ 			cfg->transmitter =
+ 				stream->sink->link->link_enc->transmitter;
+ 			cfg->link_settings =
+-					stream->sink->link->cur_link_settings;
++				stream->sink->link->public.cur_link_settings;
+ 			cfg->sym_clock = stream->public.timing.pix_clk_khz;
+ 			switch (stream->public.timing.display_color_depth) {
+ 			case COLOR_DEPTH_101010:
+diff --git a/drivers/gpu/drm/amd/dal/dc/dc.h b/drivers/gpu/drm/amd/dal/dc/dc.h
+index 70fd7d2..45d39c7 100644
+--- a/drivers/gpu/drm/amd/dal/dc/dc.h
++++ b/drivers/gpu/drm/amd/dal/dc/dc.h
+@@ -31,6 +31,7 @@
+ #include "audio_types.h"
+ #include "logger_types.h"
+ #include "gpio_types.h"
++#include "link_service_types.h"
+ 
+ #define MAX_SINKS_PER_LINK 4
+ 
+@@ -280,6 +281,14 @@ struct dc_link {
+ 	enum signal_type connector_signal;
+ 	enum dc_irq_source irq_source_hpd;
+ 	enum dc_irq_source irq_source_hpd_rx;/* aka DP Short Pulse  */
++	/* caps is the same as reported_link_cap. link_traing use
++	 * reported_link_cap. Will clean up.  TODO
++	 */
++	struct link_settings reported_link_cap;
++	struct link_settings verified_link_cap;
++	struct link_settings max_link_setting;
++	struct link_settings cur_link_settings;
++	struct lane_settings ln_setting;
+ };
+ 
+ /*
+diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
+index 6ae14d9..e721398 100644
+--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
+@@ -617,7 +617,7 @@ static void update_info_frame(struct core_stream *stream)
+ static void enable_stream(struct core_stream *stream)
+ {
+ 	enum lane_count lane_count =
+-			stream->sink->link->cur_link_settings.lane_count;
++			stream->sink->link->public.cur_link_settings.lane_count;
+ 
+ 	struct dc_crtc_timing *timing = &stream->public.timing;
+ 	struct core_link *link = stream->sink->link;
+@@ -869,7 +869,8 @@ static enum dc_status apply_single_controller_ctx_to_hw(uint8_t controller_idx,
+ 		core_link_enable_stream(stream->sink->link, stream);
+ 
+ 	if (dc_is_dp_signal(stream->signal))
+-		unblank_stream(stream, &stream->sink->link->cur_link_settings);
++		unblank_stream(stream,
++			&stream->sink->link->public.cur_link_settings);
+ 
+ 	return DC_OK;
+ }
+diff --git a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
+index 17155e3..6a81518 100644
+--- a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
++++ b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
+@@ -232,13 +232,6 @@ struct core_link {
+ 	struct graphics_object_id link_id;
+ 	union ddi_channel_mapping ddi_channel_mapping;
+ 	struct connector_device_tag_info device_tag;
+-	/* caps is the same as reported_link_cap. link_traing use
+-	 * reported_link_cap. Will clean up.  TODO */
+-	struct link_settings reported_link_cap;
+-	struct link_settings verified_link_cap;
+-	struct link_settings max_link_setting;
+-	struct link_settings cur_link_settings;
+-	struct lane_settings ln_setting;
+ 	struct dpcd_caps dpcd_caps;
+ 	unsigned int dpcd_sink_count;
+ 
+-- 
+2.7.4
+