diff options
Diffstat (limited to 'common/recipes-kernel/linux/files/0770-drm-amd-dal-Force-bw-programming-for-DCE-10-until-we.patch')
| -rw-r--r-- | common/recipes-kernel/linux/files/0770-drm-amd-dal-Force-bw-programming-for-DCE-10-until-we.patch | 76 |
1 files changed, 0 insertions, 76 deletions
diff --git a/common/recipes-kernel/linux/files/0770-drm-amd-dal-Force-bw-programming-for-DCE-10-until-we.patch b/common/recipes-kernel/linux/files/0770-drm-amd-dal-Force-bw-programming-for-DCE-10-until-we.patch deleted file mode 100644 index 0f8a5d26..00000000 --- a/common/recipes-kernel/linux/files/0770-drm-amd-dal-Force-bw-programming-for-DCE-10-until-we.patch +++ /dev/null @@ -1,76 +0,0 @@ -From 8d6ca8f203b0911f9916825d80a98cf5a57fa859 Mon Sep 17 00:00:00 2001 -From: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com> -Date: Thu, 4 Feb 2016 18:04:18 -0500 -Subject: [PATCH 0770/1110] drm/amd/dal: Force bw programming for DCE 10 until - we start calculate BW. - -Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com> -Acked-by: Jordan Lazare <Jordan.Lazare@amd.com> ---- - .../drm/amd/dal/dc/dce100/dce100_hw_sequencer.c | 28 ---------------------- - .../gpu/drm/amd/dal/dc/dce100/dce100_resource.c | 3 ++- - 2 files changed, 2 insertions(+), 29 deletions(-) - -diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c -index 82c5e15..a1dbac4 100644 ---- a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c -+++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c -@@ -335,33 +335,6 @@ static void dal_dc_clock_gating_dce100_power_up(struct dc_context *ctx, bool ena - } - } - --/** -- * Call display_engine_clock_dce80 to perform the Dclk programming. -- */ --static void set_display_clock(struct validate_context *context) --{ -- /* Program the display engine clock. -- * Check DFS bypass mode support or not. DFSbypass feature is only when -- * BIOS GPU info table reports support. */ -- -- if (/*dal_adapter_service_is_dfs_bypass_enabled()*/ false) { -- /*TODO: set_display_clock_dfs_bypass( -- hws, -- path_set, -- context->res_ctx.pool.display_clock, -- context->res_ctx.min_clocks.min_dclk_khz);*/ -- } else -- dal_display_clock_set_clock(context->res_ctx.pool.display_clock, -- 681000); -- -- /* TODO: When changing display engine clock, DMCU WaitLoop must be -- * reconfigured in order to maintain the same delays within DMCU -- * programming sequences. */ -- -- /* TODO: Start GTC counter */ --} -- -- - static void set_displaymarks( - const struct dc *dc, struct validate_context *context) - { -@@ -381,7 +354,6 @@ bool dce100_hw_sequencer_construct(struct dc *dc) - dc->hwss.enable_fe_clock = dce100_enable_fe_clock; - dc->hwss.pipe_control_lock = dce100_pipe_control_lock; - dc->hwss.set_blender_mode = dce100_set_blender_mode; -- dc->hwss.set_display_clock = set_display_clock; - dc->hwss.set_displaymarks = set_displaymarks; - return true; - } -diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c -index e67ba81..783d47e 100644 ---- a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c -+++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c -@@ -773,7 +773,8 @@ enum dc_status dce100_validate_bandwidth( - const struct dc *dc, - struct validate_context *context) - { -- /* TODO implement when needed */ -+ /* TODO implement when needed but for now hardcode max value*/ -+ context->bw_results.dispclk_khz = 681000; - - return DC_OK; - } --- -2.7.4 - |