diff options
Diffstat (limited to 'common/recipes-kernel/linux/files/0766-drm-amd-dal-add-HBR3-definitions.patch')
-rw-r--r-- | common/recipes-kernel/linux/files/0766-drm-amd-dal-add-HBR3-definitions.patch | 305 |
1 files changed, 0 insertions, 305 deletions
diff --git a/common/recipes-kernel/linux/files/0766-drm-amd-dal-add-HBR3-definitions.patch b/common/recipes-kernel/linux/files/0766-drm-amd-dal-add-HBR3-definitions.patch deleted file mode 100644 index 0d3317d8..00000000 --- a/common/recipes-kernel/linux/files/0766-drm-amd-dal-add-HBR3-definitions.patch +++ /dev/null @@ -1,305 +0,0 @@ -From 9dc947a01ca2df8de3acaabca5af1f5e037356bb Mon Sep 17 00:00:00 2001 -From: Mykola Lysenko <Mykola.Lysenko@amd.com> -Date: Wed, 3 Feb 2016 17:20:29 -0500 -Subject: [PATCH 0766/1110] drm/amd/dal: add HBR3 definitions - -Also enable TP3 usage during link training - -Signed-off-by: Mykola Lysenko <Mykola.Lysenko@amd.com> -Acked-by: Jordan Lazare <Jordan.Lazare@amd.com> ---- - drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c | 50 ++++++++++++++++++---- - drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c | 3 ++ - .../drm/amd/dal/dc/dce110/dce110_link_encoder.c | 13 +++--- - .../drm/amd/dal/dc/dce110/dce110_link_encoder.h | 4 ++ - drivers/gpu/drm/amd/dal/dc/inc/core_types.h | 1 + - drivers/gpu/drm/amd/dal/dc/inc/link_encoder.h | 2 + - drivers/gpu/drm/amd/dal/include/dpcd_defs.h | 8 ++-- - .../gpu/drm/amd/dal/include/link_service_types.h | 8 +++- - 8 files changed, 70 insertions(+), 19 deletions(-) - -diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c -index 742ab75..83d5e03 100644 ---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c -+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c -@@ -162,6 +162,9 @@ static enum dpcd_training_patterns - case HW_DP_TRAINING_PATTERN_3: - dpcd_tr_pattern = DPCD_TRAINING_PATTERN_3; - break; -+ case HW_DP_TRAINING_PATTERN_4: -+ dpcd_tr_pattern = DPCD_TRAINING_PATTERN_4; -+ break; - default: - ASSERT(0); - dal_logger_write(link->ctx->logger, -@@ -720,6 +723,29 @@ static bool perform_post_lt_adj_req_sequence( - - } - -+static enum hw_dp_training_pattern get_supported_tp(struct core_link *link) -+{ -+ enum hw_dp_training_pattern highest_tp = HW_DP_TRAINING_PATTERN_2; -+ struct encoder_feature_support *features = &link->link_enc->features; -+ struct dpcd_caps *dpcd_caps = &link->dpcd_caps; -+ -+ if (features->flags.bits.IS_TPS3_CAPABLE) -+ highest_tp = HW_DP_TRAINING_PATTERN_3; -+ -+ if (features->flags.bits.IS_TPS4_CAPABLE) -+ highest_tp = HW_DP_TRAINING_PATTERN_4; -+ -+ if (dpcd_caps->max_down_spread.bits.TPS4_SUPPORTED && -+ highest_tp >= HW_DP_TRAINING_PATTERN_4) -+ return HW_DP_TRAINING_PATTERN_4; -+ -+ if (dpcd_caps->max_ln_count.bits.TPS3_SUPPORTED && -+ highest_tp >= HW_DP_TRAINING_PATTERN_3) -+ return HW_DP_TRAINING_PATTERN_3; -+ -+ return HW_DP_TRAINING_PATTERN_2; -+} -+ - static bool perform_channel_equalization_sequence( - struct core_link *link, - struct link_training_settings *lt_settings) -@@ -731,8 +757,7 @@ static bool perform_channel_equalization_sequence( - union lane_align_status_updated dpcd_lane_status_updated = {{0}}; - union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {{{0}}};; - -- /*TODO hw_tr_pattern = HW_DP_TRAINING_PATTERN_3;*/ -- hw_tr_pattern = HW_DP_TRAINING_PATTERN_2; -+ hw_tr_pattern = get_supported_tp(link); - - dp_set_hw_training_pattern(link, hw_tr_pattern); - -@@ -1031,6 +1056,18 @@ static bool exceeded_limit_link_setting(const struct link_settings *link_setting - true : false); - } - -+static enum link_rate get_max_link_rate(struct core_link *link) -+{ -+ enum link_rate max_link_rate = LINK_RATE_HIGH; -+ -+ if (link->link_enc->features.flags.bits.IS_HBR2_CAPABLE) -+ max_link_rate = LINK_RATE_HIGH2; -+ -+ if (link->link_enc->features.flags.bits.IS_HBR3_CAPABLE) -+ max_link_rate = LINK_RATE_HIGH3; -+ -+ return max_link_rate; -+} - - bool dp_hbr_verify_link_cap( - struct core_link *link, -@@ -1048,7 +1085,7 @@ bool dp_hbr_verify_link_cap( - - /* TODO confirm this is correct for cz */ - max_link_cap.lane_count = LANE_COUNT_FOUR; -- max_link_cap.link_rate = LINK_RATE_HIGH2; -+ max_link_cap.link_rate = get_max_link_rate(link); - max_link_cap.link_spread = LINK_SPREAD_05_DOWNSPREAD_30KHZ; - - /* TODO implement override and monitor patch later */ -@@ -1641,7 +1678,6 @@ static void retrieve_link_cap(struct core_link *link) - - union down_stream_port_count down_strm_port_count; - union edp_configuration_cap edp_config_cap; -- union max_down_spread max_down_spread; - union dp_downstream_port_present ds_port = { 0 }; - - dm_memset(dpcd_data, '\0', sizeof(dpcd_data)); -@@ -1649,8 +1685,6 @@ static void retrieve_link_cap(struct core_link *link) - '\0', sizeof(union down_stream_port_count)); - dm_memset(&edp_config_cap, '\0', - sizeof(union edp_configuration_cap)); -- dm_memset(&max_down_spread, '\0', -- sizeof(union max_down_spread)); - - core_link_read_dpcd(link, DPCD_ADDRESS_DPCD_REV, - dpcd_data, sizeof(dpcd_data)); -@@ -1671,7 +1705,7 @@ static void retrieve_link_cap(struct core_link *link) - link->dpcd_caps.max_ln_count.raw = dpcd_data[ - DPCD_ADDRESS_MAX_LANE_COUNT - DPCD_ADDRESS_DPCD_REV]; - -- max_down_spread.raw = dpcd_data[ -+ link->dpcd_caps.max_down_spread.raw = dpcd_data[ - DPCD_ADDRESS_MAX_DOWNSPREAD - DPCD_ADDRESS_DPCD_REV]; - - link->reported_link_cap.lane_count = -@@ -1679,7 +1713,7 @@ static void retrieve_link_cap(struct core_link *link) - link->reported_link_cap.link_rate = dpcd_data[ - DPCD_ADDRESS_MAX_LINK_RATE - DPCD_ADDRESS_DPCD_REV]; - link->reported_link_cap.link_spread = -- max_down_spread.bits.MAX_DOWN_SPREAD ? -+ link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ? - LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED; - - edp_config_cap.raw = dpcd_data[ -diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c -index 39aa734..e8f4ec8 100644 ---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c -+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c -@@ -120,6 +120,9 @@ bool dp_set_hw_training_pattern( - case HW_DP_TRAINING_PATTERN_3: - test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN3; - break; -+ case HW_DP_TRAINING_PATTERN_4: -+ test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN4; -+ break; - default: - break; - } -diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c -index f714215..78460fc 100644 ---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c -+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c -@@ -279,12 +279,13 @@ static void set_link_training_complete( - dm_write_reg(ctx, addr, value); - } - --static void set_dp_phy_pattern_training_pattern( -- struct dce110_link_encoder *enc110, -+void dce110_link_encoder_set_dp_phy_pattern_training_pattern( -+ struct link_encoder *enc, - uint32_t index) - { -+ struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); - /* Write Training Pattern */ -- struct dc_context *ctx = enc110->base.ctx; -+ struct dc_context *ctx = enc->ctx; - uint32_t addr = LINK_REG(DP_DPHY_TRAINING_PATTERN_SEL); - - dm_write_reg(ctx, addr, index); -@@ -1555,13 +1556,13 @@ void dce110_link_encoder_dp_set_phy_pattern( - - switch (param->dp_phy_pattern) { - case DP_TEST_PATTERN_TRAINING_PATTERN1: -- set_dp_phy_pattern_training_pattern(enc110, 0); -+ dce110_link_encoder_set_dp_phy_pattern_training_pattern(enc, 0); - break; - case DP_TEST_PATTERN_TRAINING_PATTERN2: -- set_dp_phy_pattern_training_pattern(enc110, 1); -+ dce110_link_encoder_set_dp_phy_pattern_training_pattern(enc, 1); - break; - case DP_TEST_PATTERN_TRAINING_PATTERN3: -- set_dp_phy_pattern_training_pattern(enc110, 2); -+ dce110_link_encoder_set_dp_phy_pattern_training_pattern(enc, 2); - break; - case DP_TEST_PATTERN_D102: - set_dp_phy_pattern_d102(enc110); -diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h -index 46e2971..1269833 100644 ---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h -+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h -@@ -152,5 +152,9 @@ void dce110_link_encoder_connect_dig_be_to_fe( - enum engine_id engine, - bool connect); - -+void dce110_link_encoder_set_dp_phy_pattern_training_pattern( -+ struct link_encoder *enc, -+ uint32_t index); -+ - - #endif /* __DC_LINK_ENCODER__DCE110_H__ */ -diff --git a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h -index 7d63ebb..17155e3 100644 ---- a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h -+++ b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h -@@ -174,6 +174,7 @@ struct link_caps { - struct dpcd_caps { - union dpcd_rev dpcd_rev; - union max_lane_count max_ln_count; -+ union max_down_spread max_down_spread; - - /* dongle type (DP converter, CV smart dongle) */ - enum display_dongle_type dongle_type; -diff --git a/drivers/gpu/drm/amd/dal/dc/inc/link_encoder.h b/drivers/gpu/drm/amd/dal/dc/inc/link_encoder.h -index ab99b27..1f53c8f 100644 ---- a/drivers/gpu/drm/amd/dal/dc/inc/link_encoder.h -+++ b/drivers/gpu/drm/amd/dal/dc/inc/link_encoder.h -@@ -45,8 +45,10 @@ struct encoder_feature_support { - * for external DP chip supported */ - uint32_t CPLIB_DP_AUTHENTICATION:1; - uint32_t IS_HBR2_CAPABLE:1; -+ uint32_t IS_HBR3_CAPABLE:1; - uint32_t IS_HBR2_VALIDATED:1; - uint32_t IS_TPS3_CAPABLE:1; -+ uint32_t IS_TPS4_CAPABLE:1; - uint32_t IS_AUDIO_CAPABLE:1; - uint32_t IS_VCE_SUPPORTED:1; - uint32_t IS_CONVERTER:1; -diff --git a/drivers/gpu/drm/amd/dal/include/dpcd_defs.h b/drivers/gpu/drm/amd/dal/include/dpcd_defs.h -index bd410cc..deaf506 100644 ---- a/drivers/gpu/drm/amd/dal/include/dpcd_defs.h -+++ b/drivers/gpu/drm/amd/dal/include/dpcd_defs.h -@@ -241,7 +241,8 @@ enum dpcd_address { - enum dpcd_revision { - DPCD_REV_10 = 0x10, - DPCD_REV_11 = 0x11, -- DPCD_REV_12 = 0x12 -+ DPCD_REV_12 = 0x12, -+ DPCD_REV_13 = 0x13 - }; - - enum dp_pwr_state { -@@ -341,7 +342,8 @@ enum dpcd_training_patterns { - DPCD_TRAINING_PATTERN_VIDEOIDLE = 0,/* direct HW translation! */ - DPCD_TRAINING_PATTERN_1, - DPCD_TRAINING_PATTERN_2, -- DPCD_TRAINING_PATTERN_3 -+ DPCD_TRAINING_PATTERN_3, -+ DPCD_TRAINING_PATTERN_4 = 7 - }; - - /* This enum is for use with PsrSinkPsrStatus.bits.sinkSelfRefreshStatus -@@ -394,7 +396,7 @@ union max_down_spread { - uint8_t MAX_DOWN_SPREAD:1; - uint8_t RESERVED:5; - uint8_t NO_AUX_HANDSHAKE_LINK_TRAINING:1; -- uint8_t RESERVED1:1; -+ uint8_t TPS4_SUPPORTED:1; - } bits; - uint8_t raw; - }; -diff --git a/drivers/gpu/drm/amd/dal/include/link_service_types.h b/drivers/gpu/drm/amd/dal/include/link_service_types.h -index d2e6256..7db598b 100644 ---- a/drivers/gpu/drm/amd/dal/include/link_service_types.h -+++ b/drivers/gpu/drm/amd/dal/include/link_service_types.h -@@ -123,13 +123,15 @@ enum lane_count { - * 270MBps for 2.70GHz, - * 324MBps for 3.24Ghz, - * 540MBps for 5.40GHz -+ * 810MBps for 8.10GHz - */ - enum link_rate { - LINK_RATE_UNKNOWN = 0, - LINK_RATE_LOW = 0x06, - LINK_RATE_HIGH = 0x0A, - LINK_RATE_RBR2 = 0x0C, -- LINK_RATE_HIGH2 = 0x14 -+ LINK_RATE_HIGH2 = 0x14, -+ LINK_RATE_HIGH3 = 0x1E - }; - - enum { -@@ -205,7 +207,8 @@ struct link_training_settings { - enum hw_dp_training_pattern { - HW_DP_TRAINING_PATTERN_1 = 0, - HW_DP_TRAINING_PATTERN_2, -- HW_DP_TRAINING_PATTERN_3 -+ HW_DP_TRAINING_PATTERN_3, -+ HW_DP_TRAINING_PATTERN_4 - }; - - /*TODO: Move this enum test harness*/ -@@ -226,6 +229,7 @@ enum dp_test_pattern { - DP_TEST_PATTERN_TRAINING_PATTERN1, - DP_TEST_PATTERN_TRAINING_PATTERN2, - DP_TEST_PATTERN_TRAINING_PATTERN3, -+ DP_TEST_PATTERN_TRAINING_PATTERN4, - - /* link test patterns*/ - DP_TEST_PATTERN_COLOR_SQUARES, --- -2.7.4 - |