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-rw-r--r--common/recipes-kernel/linux/files/0739-drm-amd-dal-Clean-up-dc_temp.h.patch1390
1 files changed, 0 insertions, 1390 deletions
diff --git a/common/recipes-kernel/linux/files/0739-drm-amd-dal-Clean-up-dc_temp.h.patch b/common/recipes-kernel/linux/files/0739-drm-amd-dal-Clean-up-dc_temp.h.patch
deleted file mode 100644
index c19661c4..00000000
--- a/common/recipes-kernel/linux/files/0739-drm-amd-dal-Clean-up-dc_temp.h.patch
+++ /dev/null
@@ -1,1390 +0,0 @@
-From 7aaf1d3c2261a553a0d07b48afd1666475344727 Mon Sep 17 00:00:00 2001
-From: Jordan Lazare <Jordan.Lazare@amd.com>
-Date: Mon, 25 Jan 2016 17:55:30 -0500
-Subject: [PATCH 0739/1110] drm/amd/dal: Clean up dc_temp.h
-
-Signed-off-by: Jordan Lazare <Jordan.Lazare@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c | 10 +-
- drivers/gpu/drm/amd/dal/dc/core/dc.c | 45 --
- drivers/gpu/drm/amd/dal/dc/dc.h | 12 +-
- drivers/gpu/drm/amd/dal/dc/dc_temp.h | 507 ---------------------
- drivers/gpu/drm/amd/dal/dc/dc_types.h | 257 ++++++++++-
- .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c | 1 +
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.h | 4 +
- .../gpu/drm/amd/dal/dc/dce110/dce110_ipp_gamma.c | 1 +
- .../gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c | 4 +-
- .../gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h | 2 +-
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c | 1 +
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.h | 2 +
- .../gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma.c | 1 +
- .../amd/dal/dc/dce110/dce110_transform_bit_depth.c | 2 +-
- drivers/gpu/drm/amd/dal/dc/inc/core_types.h | 1 +
- drivers/gpu/drm/amd/dal/dc/inc/gamma_types.h | 117 +++++
- drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h | 9 +
- drivers/gpu/drm/amd/dal/dc/inc/ipp.h | 1 +
- drivers/gpu/drm/amd/dal/dc/inc/mem_input.h | 2 +-
- drivers/gpu/drm/amd/dal/dc/inc/opp.h | 62 ++-
- drivers/gpu/drm/amd/dal/dc/inc/transform.h | 2 +
- drivers/gpu/drm/amd/dal/include/fixed32_32.h | 2 +
- .../gpu/drm/amd/dal/include/video_gamma_types.h | 1 +
- 23 files changed, 474 insertions(+), 572 deletions(-)
- delete mode 100644 drivers/gpu/drm/amd/dal/dc/dc_temp.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/inc/gamma_types.h
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-index 5fe5ca4..70d5dae 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-@@ -59,6 +59,7 @@ struct dm_connector_state {
- container_of((x), struct dm_connector_state, base)
-
- #define AMDGPU_CRTC_MODE_PRIVATE_FLAGS_GAMMASET 1
-+#define MAX_TARGET_NUM 6
-
- void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
- {
-@@ -314,15 +315,6 @@ static int dm_crtc_cursor_move(struct drm_crtc *crtc,
- return -EINVAL;
- }
-
--#if BUILD_FEATURE_TIMING_SYNC
-- {
-- struct drm_device *dev = crtc->dev;
-- struct amdgpu_device *adev = dev->dev_private;
-- struct amdgpu_display_manager *dm = &adev->dm;
--
-- dc_print_sync_report(dm->dc);
-- }
--#endif
- return 0;
- }
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index 51a8589..1a17090 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -55,11 +55,6 @@ struct dc_target_sync_report {
- uint32_t v_count;
- };
-
--struct dc_sync_report {
-- uint32_t targets_num;
-- struct dc_target_sync_report trg_reports[MAX_TARGET_NUM];
--};
--
- /*******************************************************************************
- * Private functions
- ******************************************************************************/
-@@ -794,46 +789,6 @@ void dc_resume(const struct dc *dc)
- core_link_resume(dc->links[i]);
- }
-
--void dc_print_sync_report(
-- const struct dc *dc)
--{
-- uint32_t i;
-- const struct core_target *core_target;
-- const struct core_stream *core_stream;
-- struct dc_context *dc_ctx = dc->ctx;
-- struct dc_target_sync_report *target_sync_report;
-- struct dc_sync_report sync_report = { 0 };
--
-- if (dc->current_context.target_count > MAX_TARGET_NUM) {
-- DC_ERROR("Target count: %d > %d!\n",
-- dc->current_context.target_count,
-- MAX_TARGET_NUM);
-- return;
-- }
--
-- sync_report.targets_num = dc->current_context.target_count;
--
-- /* Step 1: get data for sync validation */
-- for (i = 0; i < dc->current_context.target_count; i++) {
--
-- core_target = dc->current_context.targets[i];
-- target_sync_report = &sync_report.trg_reports[i];
-- core_stream = DC_STREAM_TO_CORE(core_target->public.streams[0]);
--
-- dc->hwss.get_crtc_positions(
-- core_stream->tg,
-- &target_sync_report->h_count,
-- &target_sync_report->v_count);
--
-- DC_SYNC_INFO("GSL:target[%d]: h: %d\t v: %d\n",
-- i,
-- target_sync_report->h_count,
-- target_sync_report->v_count);
-- }
--
-- /* Step 2: validate that display pipes are synchronized (based on
-- * data from Step 1). */
--}
-
- bool dc_read_dpcd(
- struct dc *dc,
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc.h b/drivers/gpu/drm/amd/dal/dc/dc.h
-index a06a8a7..fcc79ed 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc.h
-@@ -68,7 +68,7 @@ struct dc_surface {
- struct rect clip_rect;
-
- union plane_size plane_size;
-- union plane_tiling_info tiling_info;
-+ union dc_tiling_info tiling_info;
- struct plane_colorimetry colorimetry;
-
- enum surface_pixel_format format;
-@@ -351,6 +351,16 @@ struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params);
- /*******************************************************************************
- * Cursor interfaces - To manages the cursor within a target
- ******************************************************************************/
-+/* TODO: Deprecated once we switch to dc_set_cursor_position */
-+bool dc_target_set_cursor_attributes(
-+ struct dc_target *dc_target,
-+ const struct dc_cursor_attributes *attributes);
-+
-+bool dc_target_set_cursor_position(
-+ struct dc_target *dc_target,
-+ const struct dc_cursor_position *position);
-+
-+/* Newer interfaces */
- struct dc_cursor {
- struct dc_plane_address address;
- struct dc_cursor_attributes attributes;
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_temp.h b/drivers/gpu/drm/amd/dal/dc/dc_temp.h
-deleted file mode 100644
-index fc5b810..0000000
---- a/drivers/gpu/drm/amd/dal/dc/dc_temp.h
-+++ /dev/null
-@@ -1,507 +0,0 @@
--/*
-- * Copyright 2012-15 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- * Authors: AMD
-- *
-- */
--#ifndef DC_TEMP_H_
--#define DC_TEMP_H_
--
--#include "dc_types.h"
--
--#define MAX_SURFACE_NUM 2
--
--enum clamping_range {
-- CLAMPING_FULL_RANGE = 0, /* No Clamping */
-- CLAMPING_LIMITED_RANGE_8BPC, /* 8 bpc: Clamping 1 to FE */
-- CLAMPING_LIMITED_RANGE_10BPC, /* 10 bpc: Clamping 4 to 3FB */
-- CLAMPING_LIMITED_RANGE_12BPC, /* 12 bpc: Clamping 10 to FEF */
-- /* Use programmable clampping value on FMT_CLAMP_COMPONENT_R/G/B. */
-- CLAMPING_LIMITED_RANGE_PROGRAMMABLE
--};
--
--struct clamping_and_pixel_encoding_params {
-- enum dc_pixel_encoding pixel_encoding; /* Pixel Encoding */
-- enum clamping_range clamping_level; /* Clamping identifier */
-- enum dc_color_depth c_depth; /* Deep color use. */
--};
--
--struct bit_depth_reduction_params {
-- struct {
-- /* truncate/round */
-- /* trunc/round enabled*/
-- uint32_t TRUNCATE_ENABLED:1;
-- /* 2 bits: 0=6 bpc, 1=8 bpc, 2 = 10bpc*/
-- uint32_t TRUNCATE_DEPTH:2;
-- /* truncate or round*/
-- uint32_t TRUNCATE_MODE:1;
--
-- /* spatial dither */
-- /* Spatial Bit Depth Reduction enabled*/
-- uint32_t SPATIAL_DITHER_ENABLED:1;
-- /* 2 bits: 0=6 bpc, 1 = 8 bpc, 2 = 10bpc*/
-- uint32_t SPATIAL_DITHER_DEPTH:2;
-- /* 0-3 to select patterns*/
-- uint32_t SPATIAL_DITHER_MODE:2;
-- /* Enable RGB random dithering*/
-- uint32_t RGB_RANDOM:1;
-- /* Enable Frame random dithering*/
-- uint32_t FRAME_RANDOM:1;
-- /* Enable HighPass random dithering*/
-- uint32_t HIGHPASS_RANDOM:1;
--
-- /* temporal dither*/
-- /* frame modulation enabled*/
-- uint32_t FRAME_MODULATION_ENABLED:1;
-- /* same as for trunc/spatial*/
-- uint32_t FRAME_MODULATION_DEPTH:2;
-- /* 2/4 gray levels*/
-- uint32_t TEMPORAL_LEVEL:1;
-- uint32_t FRC25:2;
-- uint32_t FRC50:2;
-- uint32_t FRC75:2;
-- } flags;
--
-- uint32_t r_seed_value;
-- uint32_t b_seed_value;
-- uint32_t g_seed_value;
--};
--
--enum pipe_gating_control {
-- PIPE_GATING_CONTROL_DISABLE = 0,
-- PIPE_GATING_CONTROL_ENABLE,
-- PIPE_GATING_CONTROL_INIT
--};
--
--enum surface_color_space {
-- SURFACE_COLOR_SPACE_SRGB = 0x0000,
-- SURFACE_COLOR_SPACE_BT601 = 0x0001,
-- SURFACE_COLOR_SPACE_BT709 = 0x0002,
-- SURFACE_COLOR_SPACE_XVYCC_BT601 = 0x0004,
-- SURFACE_COLOR_SPACE_XVYCC_BT709 = 0x0008,
-- SURFACE_COLOR_SPACE_XRRGB = 0x0010
--};
--
--enum {
-- MAX_LANES = 2,
-- MAX_COFUNC_PATH = 6,
-- LAYER_INDEX_PRIMARY = -1,
--};
--
--/* Scaling format */
--enum scaling_transformation {
-- SCALING_TRANSFORMATION_UNINITIALIZED,
-- SCALING_TRANSFORMATION_IDENTITY = 0x0001,
-- SCALING_TRANSFORMATION_CENTER_TIMING = 0x0002,
-- SCALING_TRANSFORMATION_FULL_SCREEN_SCALE = 0x0004,
-- SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE = 0x0008,
-- SCALING_TRANSFORMATION_DAL_DECIDE = 0x0010,
-- SCALING_TRANSFORMATION_INVALID = 0x80000000,
--
-- /* Flag the first and last */
-- SCALING_TRANSFORMATION_BEGING = SCALING_TRANSFORMATION_IDENTITY,
-- SCALING_TRANSFORMATION_END =
-- SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE
--};
--
--struct view_stereo_3d_support {
-- enum view_3d_format format;
-- struct {
-- uint32_t CLONE_MODE:1;
-- uint32_t SCALING:1;
-- uint32_t SINGLE_FRAME_SW_PACKED:1;
-- } features;
--};
--
--struct plane_colorimetry {
-- enum surface_color_space color_space;
-- bool limited_range;
--};
--
--enum tiling_mode {
-- TILING_MODE_INVALID,
-- TILING_MODE_LINEAR,
-- TILING_MODE_TILED,
-- TILING_MODE_COUNT
--};
--
--struct view_position {
-- uint32_t x;
-- uint32_t y;
--};
--
--union plane_tiling_info {
--
-- struct {
-- /* Specifies the number of memory banks for tiling
-- * purposes.
-- * Only applies to 2D and 3D tiling modes.
-- * POSSIBLE VALUES: 2,4,8,16
-- */
-- uint32_t NUM_BANKS:5;
-- /* Specifies the number of tiles in the x direction
-- * to be incorporated into the same bank.
-- * Only applies to 2D and 3D tiling modes.
-- * POSSIBLE VALUES: 1,2,4,8
-- */
-- uint32_t BANK_WIDTH:4;
-- /* Specifies the number of tiles in the y direction to
-- * be incorporated into the same bank.
-- * Only applies to 2D and 3D tiling modes.
-- * POSSIBLE VALUES: 1,2,4,8
-- */
-- uint32_t BANK_HEIGHT:4;
-- /* Specifies the macro tile aspect ratio. Only applies
-- * to 2D and 3D tiling modes.
-- */
-- uint32_t TILE_ASPECT:3;
-- /* Specifies the number of bytes that will be stored
-- * contiguously for each tile.
-- * If the tile data requires more storage than this
-- * amount, it is split into multiple slices.
-- * This field must not be larger than
-- * GB_ADDR_CONFIG.DRAM_ROW_SIZE.
-- * Only applies to 2D and 3D tiling modes.
-- * For color render targets, TILE_SPLIT >= 256B.
-- */
-- uint32_t TILE_SPLIT:3;
-- /* Specifies the addressing within a tile.
-- * 0x0 - DISPLAY_MICRO_TILING
-- * 0x1 - THIN_MICRO_TILING
-- * 0x2 - DEPTH_MICRO_TILING
-- * 0x3 - ROTATED_MICRO_TILING
-- */
-- uint32_t TILE_MODE:2;
-- /* Specifies the number of pipes and how they are
-- * interleaved in the surface.
-- * Refer to memory addressing document for complete
-- * details and constraints.
-- */
-- uint32_t PIPE_CONFIG:5;
-- /* Specifies the tiling mode of the surface.
-- * THIN tiles use an 8x8x1 tile size.
-- * THICK tiles use an 8x8x4 tile size.
-- * 2D tiling modes rotate banks for successive Z slices
-- * 3D tiling modes rotate pipes and banks for Z slices
-- * Refer to memory addressing document for complete
-- * details and constraints.
-- */
-- uint32_t ARRAY_MODE:4;
-- } grph;
--
--
-- struct {
-- /*possible values: 2,4,8,16*/
-- uint32_t NUM_BANKS:5;
-- /*must use enum video_array_mode*/
-- uint32_t ARRAY_MODE:4;
-- /*must use enum addr_pipe_config*/
-- uint32_t PIPE_CONFIG:5;
-- /*possible values 1,2,4,8 */
-- uint32_t BANK_WIDTH_LUMA:4;
-- /*possible values 1,2,4,8 */
-- uint32_t BANK_HEIGHT_LUMA:4;
-- /*must use enum macro_tile_aspect*/
-- uint32_t TILE_ASPECT_LUMA:3;
-- /*must use enum tile_split*/
-- uint32_t TILE_SPLIT_LUMA:3;
-- /*must use micro_tile_mode */
-- uint32_t TILE_MODE_LUMA:2;
-- /*possible values: 1,2,4,8*/
-- uint32_t BANK_WIDTH_CHROMA:4;
-- /*possible values: 1,2,4,8*/
-- uint32_t BANK_HEIGHT_CHROMA:4;
-- /*must use enum macro_tile_aspect*/
-- uint32_t TILE_ASPECT_CHROMA:3;
-- /*must use enum tile_split*/
-- uint32_t TILE_SPLIT_CHROMA:3;
-- /*must use enum micro_tile_mode*/
-- uint32_t TILE_MODE_CHROMA:2;
--
-- } video;
--
-- uint64_t value;
--};
--
--union plane_size {
-- /* Grph or Video will be selected
-- * based on format above:
-- * Use Video structure if
-- * format >= DalPixelFormat_VideoBegin
-- * else use Grph structure
-- */
-- struct {
-- struct rect surface_size;
-- /* Graphic surface pitch in pixels.
-- * In LINEAR_GENERAL mode, pitch
-- * is 32 pixel aligned.
-- */
-- uint32_t surface_pitch;
-- } grph;
--
-- struct {
-- struct rect luma_size;
-- /* Graphic surface pitch in pixels.
-- * In LINEAR_GENERAL mode, pitch is
-- * 32 pixel aligned.
-- */
-- uint32_t luma_pitch;
--
-- struct rect chroma_size;
-- /* Graphic surface pitch in pixels.
-- * In LINEAR_GENERAL mode, pitch is
-- * 32 pixel aligned.
-- */
-- uint32_t chroma_pitch;
-- } video;
--};
--
--enum dc_scaling_transform {
-- SCL_TRANS_CENTERED = 0,
-- SCL_TRANS_ASPECT_RATIO,
-- SCL_TRANS_FULL
--};
--
--struct dev_c_lut {
-- uint8_t red;
-- uint8_t green;
-- uint8_t blue;
--};
--
--struct dev_c_lut16 {
-- uint16_t red;
-- uint16_t green;
-- uint16_t blue;
--};
--
--enum gamma_ramp_type {
-- GAMMA_RAMP_UNINITIALIZED = 0,
-- GAMMA_RAMP_DEFAULT,
-- GAMMA_RAMP_RBG256X3X16,
-- GAMMA_RAMP_DXGI_1,
--};
--
--enum surface_type {
-- OVERLAY_SURFACE = 1, GRAPHIC_SURFACE
--};
--
--#define CONST_RGB_GAMMA_VALUE 2400
--
--enum {
-- RGB_256X3X16 = 256, DX_GAMMA_RAMP_MAX = 1025
--};
--
--struct gamma_ramp_rgb256x3x16 {
-- uint16_t red[RGB_256X3X16];
-- uint16_t green[RGB_256X3X16];
-- uint16_t blue[RGB_256X3X16];
--};
--
--struct dxgi_rgb {
-- struct fixed32_32 red;
-- struct fixed32_32 green;
-- struct fixed32_32 blue;
--};
--
--struct gamma_ramp_dxgi_1 {
-- struct dxgi_rgb scale;
-- struct dxgi_rgb offset;
-- struct dxgi_rgb gamma_curve[DX_GAMMA_RAMP_MAX];
--};
--
--struct gamma_ramp {
-- enum gamma_ramp_type type;
-- union {
-- struct gamma_ramp_rgb256x3x16 gamma_ramp_rgb256x3x16;
-- struct gamma_ramp_dxgi_1 gamma_ramp_dxgi1;
-- };
-- uint32_t size;
--};
--
--struct regamma_ramp {
-- uint16_t gamma[RGB_256X3X16 * 3];
--};
--
--/* used by Graphics and Overlay gamma */
--struct gamma_coeff {
-- int32_t gamma[3];
-- int32_t a0[3]; /* index 0 for red, 1 for green, 2 for blue */
-- int32_t a1[3];
-- int32_t a2[3];
-- int32_t a3[3];
--};
--
--struct regamma_lut {
-- union {
-- struct {
-- uint32_t GRAPHICS_DEGAMMA_SRGB :1;
-- uint32_t OVERLAY_DEGAMMA_SRGB :1;
-- uint32_t GAMMA_RAMP_ARRAY :1;
-- uint32_t APPLY_DEGAMMA :1;
-- uint32_t RESERVED :28;
-- } bits;
-- uint32_t value;
-- } features;
--
-- union {
-- struct regamma_ramp regamma_ramp;
-- struct gamma_coeff gamma_coeff;
-- };
--};
--
--union gamma_flag {
-- struct {
-- uint32_t config_is_changed :1;
-- uint32_t both_pipe_req :1;
-- uint32_t regamma_update :1;
-- uint32_t gamma_update :1;
-- uint32_t reserved :28;
-- } bits;
-- uint32_t u_all;
--};
--
--enum graphics_regamma_adjust {
-- GRAPHICS_REGAMMA_ADJUST_BYPASS = 0, GRAPHICS_REGAMMA_ADJUST_HW, /* without adjustments */
-- GRAPHICS_REGAMMA_ADJUST_SW /* use adjustments */
--};
--
--enum graphics_gamma_lut {
-- GRAPHICS_GAMMA_LUT_LEGACY = 0, /* use only legacy LUT */
-- GRAPHICS_GAMMA_LUT_REGAMMA, /* use only regamma LUT */
-- GRAPHICS_GAMMA_LUT_LEGACY_AND_REGAMMA /* use legacy & regamma LUT's */
--};
--
--enum graphics_degamma_adjust {
-- GRAPHICS_DEGAMMA_ADJUST_BYPASS = 0, GRAPHICS_DEGAMMA_ADJUST_HW, /*without adjustments */
-- GRAPHICS_DEGAMMA_ADJUST_SW /* use adjustments */
--};
--
--struct gamma_parameters {
-- union gamma_flag flag;
-- enum pixel_format surface_pixel_format; /*OS surface pixel format*/
-- struct regamma_lut regamma;
--
-- enum graphics_regamma_adjust regamma_adjust_type;
-- enum graphics_degamma_adjust degamma_adjust_type;
--
-- enum graphics_gamma_lut selected_gamma_lut;
--
-- bool disable_adjustments;
--
-- /* here we grow with parameters if necessary */
--};
--
--struct pixel_format_support {
-- bool INDEX8 :1;
-- bool RGB565 :1;
-- bool ARGB8888 :1;
-- bool ARGB2101010 :1;
-- bool ARGB2101010_XRBIAS :1;
-- bool FP16 :1;
--};
--
--struct render_mode {
-- struct view view;
-- enum pixel_format pixel_format;
--};
--
--struct refresh_rate {
-- uint32_t field_rate;
-- bool INTERLACED :1;
-- bool VIDEO_OPTIMIZED_RATE :1;
--};
--
--struct stereo_3d_view {
-- enum view_3d_format view_3d_format;
-- union {
-- uint32_t raw;
-- struct /*stereo_3d_view_flags*/
-- {
-- bool SINGLE_FRAME_SW_PACKED :1;
-- bool EXCLUSIVE_3D :1;
-- } bits;
-- } flags;
--};
--
--enum solution_importance {
-- SOLUTION_IMPORTANCE_PREFERRED = 1,
-- /* Means we want to use this solution
-- * even in wide topology configurations*/
-- SOLUTION_IMPORTANCE_SAFE,
-- SOLUTION_IMPORTANCE_UNSAFE,
-- SOLUTION_IMPORTANCE_DEFAULT
--/* Temporary state , means Solution object
-- * should define importance by itself
-- */
--};
--
--struct solution {
-- const struct dc_mode_timing *dc_mode_timing;
-- enum solution_importance importance;
-- bool is_custom_mode;
-- uint32_t scl_support[NUM_PIXEL_FORMATS];
-- /* bit vector of the scaling that can be supported on the timing */
-- uint32_t scl_support_guaranteed[NUM_PIXEL_FORMATS];
-- /* subset of m_sclSupport that can be guaranteed supported */
--};
--
--enum timing_select {
-- TIMING_SELECT_DEFAULT,
-- TIMING_SELECT_NATIVE_ONLY,
-- TIMING_SELECT_PRESERVE_ASPECT
--};
--
--enum downscale_state {
-- DOWNSCALESTATE_DEFAULT, // Disabled, but not user selected
-- DOWNSCALESTATE_DISABLED, // User disabled through CCC
-- DOWNSCALESTATE_ENABLED // User enabled through CCC
--};
--struct scaling_support {
-- bool IDENTITY :1;
-- bool FULL_SCREEN_SCALE :1;
-- bool PRESERVE_ASPECT_RATIO_SCALE :1;
-- bool CENTER_TIMING :1;
--};
--
--
--/* TODO: combine the two cursor functions into one to make cursor
-- * programming resistant to changes in OS call sequence. */
--bool dc_target_set_cursor_attributes(
-- struct dc_target *dc_target,
-- const struct dc_cursor_attributes *attributes);
--
--bool dc_target_set_cursor_position(
-- struct dc_target *dc_target,
-- const struct dc_cursor_position *position);
--
--/******************************************************************************
-- * TODO: these definitions only for Timing Sync feature bring-up. Remove
-- * when the feature is complete.
-- *****************************************************************************/
--
--#define MAX_TARGET_NUM 6
--
--void dc_print_sync_report(
-- const struct dc *dc);
--
--/******************************************************************************/
--
--#endif /* DC_TEMP_H_ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_types.h b/drivers/gpu/drm/amd/dal/dc/dc_types.h
-index 60e5603..fe7046f 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_types.h
-@@ -63,6 +63,17 @@ enum dce_environment {
- /********************************/
-
- #define MAX_EDID_BUFFER_SIZE 512
-+#define MAX_SURFACE_NUM 2
-+#define NUM_PIXEL_FORMATS 10
-+
-+enum surface_color_space {
-+ SURFACE_COLOR_SPACE_SRGB = 0x0000,
-+ SURFACE_COLOR_SPACE_BT601 = 0x0001,
-+ SURFACE_COLOR_SPACE_BT709 = 0x0002,
-+ SURFACE_COLOR_SPACE_XVYCC_BT601 = 0x0004,
-+ SURFACE_COLOR_SPACE_XVYCC_BT709 = 0x0008,
-+ SURFACE_COLOR_SPACE_XRRGB = 0x0010
-+};
-
- /*Displayable pixel format in fb*/
- enum surface_pixel_format {
-@@ -174,9 +185,6 @@ enum dc_pixel_encoding {
- * Please increase if pixel_format enum increases
- * num from PIXEL_FORMAT_INDEX8 to PIXEL_FORMAT_444BPP32
- */
--#define NUM_PIXEL_FORMATS 10
--
--
-
- union large_integer {
- struct {
-@@ -211,6 +219,11 @@ enum dc_edid_status {
- EDID_BAD_CHECKSUM,
- };
-
-+struct plane_colorimetry {
-+ enum surface_color_space color_space;
-+ bool limited_range;
-+};
-+
- /* audio capability from EDID*/
- struct dc_cea_audio_mode {
- uint8_t format_code; /* ucData[0] [6:3]*/
-@@ -710,6 +723,47 @@ enum dc_connection_type {
- * returns 0.
- *
- */
-+/* TODO: Deprecated */
-+enum {
-+ RGB_256X3X16 = 256,
-+ DX_GAMMA_RAMP_MAX = 1025
-+};
-+
-+enum gamma_ramp_type {
-+ GAMMA_RAMP_UNINITIALIZED = 0,
-+ GAMMA_RAMP_DEFAULT,
-+ GAMMA_RAMP_RBG256X3X16,
-+ GAMMA_RAMP_DXGI_1,
-+};
-+
-+struct dxgi_rgb {
-+ struct fixed32_32 red;
-+ struct fixed32_32 green;
-+ struct fixed32_32 blue;
-+};
-+
-+struct gamma_ramp_dxgi_1 {
-+ struct dxgi_rgb scale;
-+ struct dxgi_rgb offset;
-+ struct dxgi_rgb gamma_curve[DX_GAMMA_RAMP_MAX];
-+};
-+
-+struct gamma_ramp_rgb256x3x16 {
-+ uint16_t red[RGB_256X3X16];
-+ uint16_t green[RGB_256X3X16];
-+ uint16_t blue[RGB_256X3X16];
-+};
-+
-+struct gamma_ramp {
-+ enum gamma_ramp_type type;
-+ union {
-+ struct gamma_ramp_rgb256x3x16 gamma_ramp_rgb256x3x16;
-+ struct gamma_ramp_dxgi_1 gamma_ramp_dxgi1;
-+ };
-+ uint32_t size;
-+};
-+
-+
- struct dc_gamma_ramp {
- uint32_t (*get_gamma_value) (
- void *context,
-@@ -728,6 +782,201 @@ struct dc_csc_adjustments {
- struct fixed31_32 hue;
- };
-
--#include "dc_temp.h"
-+
-+enum {
-+ MAX_LANES = 2,
-+ MAX_COFUNC_PATH = 6,
-+ LAYER_INDEX_PRIMARY = -1,
-+};
-+
-+/* Scaling format */
-+enum scaling_transformation {
-+ SCALING_TRANSFORMATION_UNINITIALIZED,
-+ SCALING_TRANSFORMATION_IDENTITY = 0x0001,
-+ SCALING_TRANSFORMATION_CENTER_TIMING = 0x0002,
-+ SCALING_TRANSFORMATION_FULL_SCREEN_SCALE = 0x0004,
-+ SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE = 0x0008,
-+ SCALING_TRANSFORMATION_DAL_DECIDE = 0x0010,
-+ SCALING_TRANSFORMATION_INVALID = 0x80000000,
-+
-+ /* Flag the first and last */
-+ SCALING_TRANSFORMATION_BEGING = SCALING_TRANSFORMATION_IDENTITY,
-+ SCALING_TRANSFORMATION_END =
-+ SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE
-+};
-+
-+struct view_stereo_3d_support {
-+ enum view_3d_format format;
-+ struct {
-+ uint32_t CLONE_MODE:1;
-+ uint32_t SCALING:1;
-+ uint32_t SINGLE_FRAME_SW_PACKED:1;
-+ } features;
-+};
-+
-+enum tiling_mode {
-+ TILING_MODE_INVALID,
-+ TILING_MODE_LINEAR,
-+ TILING_MODE_TILED,
-+ TILING_MODE_COUNT
-+};
-+
-+struct view_position {
-+ uint32_t x;
-+ uint32_t y;
-+};
-+
-+struct render_mode {
-+ struct view view;
-+ enum pixel_format pixel_format;
-+};
-+
-+struct pixel_format_support {
-+ bool INDEX8 :1;
-+ bool RGB565 :1;
-+ bool ARGB8888 :1;
-+ bool ARGB2101010 :1;
-+ bool ARGB2101010_XRBIAS :1;
-+ bool FP16 :1;
-+};
-+
-+struct stereo_3d_view {
-+ enum view_3d_format view_3d_format;
-+ union {
-+ uint32_t raw;
-+ struct /*stereo_3d_view_flags*/
-+ {
-+ bool SINGLE_FRAME_SW_PACKED :1;
-+ bool EXCLUSIVE_3D :1;
-+ } bits;
-+ } flags;
-+};
-+
-+/* TODO: Rename to dc_tiling_info */
-+union dc_tiling_info {
-+
-+ struct {
-+ /* Specifies the number of memory banks for tiling
-+ * purposes.
-+ * Only applies to 2D and 3D tiling modes.
-+ * POSSIBLE VALUES: 2,4,8,16
-+ */
-+ uint32_t NUM_BANKS:5;
-+ /* Specifies the number of tiles in the x direction
-+ * to be incorporated into the same bank.
-+ * Only applies to 2D and 3D tiling modes.
-+ * POSSIBLE VALUES: 1,2,4,8
-+ */
-+ uint32_t BANK_WIDTH:4;
-+ /* Specifies the number of tiles in the y direction to
-+ * be incorporated into the same bank.
-+ * Only applies to 2D and 3D tiling modes.
-+ * POSSIBLE VALUES: 1,2,4,8
-+ */
-+ uint32_t BANK_HEIGHT:4;
-+ /* Specifies the macro tile aspect ratio. Only applies
-+ * to 2D and 3D tiling modes.
-+ */
-+ uint32_t TILE_ASPECT:3;
-+ /* Specifies the number of bytes that will be stored
-+ * contiguously for each tile.
-+ * If the tile data requires more storage than this
-+ * amount, it is split into multiple slices.
-+ * This field must not be larger than
-+ * GB_ADDR_CONFIG.DRAM_ROW_SIZE.
-+ * Only applies to 2D and 3D tiling modes.
-+ * For color render targets, TILE_SPLIT >= 256B.
-+ */
-+ uint32_t TILE_SPLIT:3;
-+ /* Specifies the addressing within a tile.
-+ * 0x0 - DISPLAY_MICRO_TILING
-+ * 0x1 - THIN_MICRO_TILING
-+ * 0x2 - DEPTH_MICRO_TILING
-+ * 0x3 - ROTATED_MICRO_TILING
-+ */
-+ uint32_t TILE_MODE:2;
-+ /* Specifies the number of pipes and how they are
-+ * interleaved in the surface.
-+ * Refer to memory addressing document for complete
-+ * details and constraints.
-+ */
-+ uint32_t PIPE_CONFIG:5;
-+ /* Specifies the tiling mode of the surface.
-+ * THIN tiles use an 8x8x1 tile size.
-+ * THICK tiles use an 8x8x4 tile size.
-+ * 2D tiling modes rotate banks for successive Z slices
-+ * 3D tiling modes rotate pipes and banks for Z slices
-+ * Refer to memory addressing document for complete
-+ * details and constraints.
-+ */
-+ uint32_t ARRAY_MODE:4;
-+ } grph;
-+
-+
-+ struct {
-+ /*possible values: 2,4,8,16*/
-+ uint32_t NUM_BANKS:5;
-+ /*must use enum video_array_mode*/
-+ uint32_t ARRAY_MODE:4;
-+ /*must use enum addr_pipe_config*/
-+ uint32_t PIPE_CONFIG:5;
-+ /*possible values 1,2,4,8 */
-+ uint32_t BANK_WIDTH_LUMA:4;
-+ /*possible values 1,2,4,8 */
-+ uint32_t BANK_HEIGHT_LUMA:4;
-+ /*must use enum macro_tile_aspect*/
-+ uint32_t TILE_ASPECT_LUMA:3;
-+ /*must use enum tile_split*/
-+ uint32_t TILE_SPLIT_LUMA:3;
-+ /*must use micro_tile_mode */
-+ uint32_t TILE_MODE_LUMA:2;
-+ /*possible values: 1,2,4,8*/
-+ uint32_t BANK_WIDTH_CHROMA:4;
-+ /*possible values: 1,2,4,8*/
-+ uint32_t BANK_HEIGHT_CHROMA:4;
-+ /*must use enum macro_tile_aspect*/
-+ uint32_t TILE_ASPECT_CHROMA:3;
-+ /*must use enum tile_split*/
-+ uint32_t TILE_SPLIT_CHROMA:3;
-+ /*must use enum micro_tile_mode*/
-+ uint32_t TILE_MODE_CHROMA:2;
-+
-+ } video;
-+
-+ uint64_t value;
-+};
-+
-+union plane_size {
-+ /* Grph or Video will be selected
-+ * based on format above:
-+ * Use Video structure if
-+ * format >= DalPixelFormat_VideoBegin
-+ * else use Grph structure
-+ */
-+ struct {
-+ struct rect surface_size;
-+ /* Graphic surface pitch in pixels.
-+ * In LINEAR_GENERAL mode, pitch
-+ * is 32 pixel aligned.
-+ */
-+ uint32_t surface_pitch;
-+ } grph;
-+
-+ struct {
-+ struct rect luma_size;
-+ /* Graphic surface pitch in pixels.
-+ * In LINEAR_GENERAL mode, pitch is
-+ * 32 pixel aligned.
-+ */
-+ uint32_t luma_pitch;
-+
-+ struct rect chroma_size;
-+ /* Graphic surface pitch in pixels.
-+ * In LINEAR_GENERAL mode, pitch is
-+ * 32 pixel aligned.
-+ */
-+ uint32_t chroma_pitch;
-+ } video;
-+};
-
- #endif /* DC_TYPES_H_ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index af7cf0d..046a9a5 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -30,6 +30,7 @@
- #include "resource.h"
- #include "hw_sequencer.h"
- #include "dc_helpers.h"
-+#include "gamma_types.h"
-
- #include "dce110/dce110_resource.h"
- #include "dce110/dce110_timing_generator.h"
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.h
-index f0e9e7d..709906f 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.h
-@@ -28,6 +28,10 @@
-
- #include "inc/ipp.h"
-
-+
-+struct gamma_parameters;
-+struct dev_c_lut;
-+
- #define TO_DCE110_IPP(input_pixel_processor)\
- container_of(input_pixel_processor, struct dce110_ipp, base)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp_gamma.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp_gamma.c
-index 2aa432a..a30c0da 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp_gamma.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp_gamma.c
-@@ -32,6 +32,7 @@
- #include "dce/dce_11_0_sh_mask.h"
-
- #include "dce110_ipp.h"
-+#include "gamma_types.h"
-
- #define DCP_REG(reg)\
- (reg + ipp110->offsets.dcp_offset)
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
-index 4e809b6..b70c8e1 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
-@@ -179,7 +179,7 @@ static void enable(struct dce110_mem_input *mem_input110)
-
- static void program_tiling(
- struct dce110_mem_input *mem_input110,
-- const union plane_tiling_info *info,
-+ const union dc_tiling_info *info,
- const enum surface_pixel_format pixel_format)
- {
- uint32_t value = 0;
-@@ -458,7 +458,7 @@ bool dce110_mem_input_program_surface_flip_and_addr(
- bool dce110_mem_input_program_surface_config(
- struct mem_input *mem_input,
- enum surface_pixel_format format,
-- union plane_tiling_info *tiling_info,
-+ union dc_tiling_info *tiling_info,
- union plane_size *plane_size,
- enum dc_rotation_angle rotation)
- {
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h
-index 997070b..cd19169 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h
-@@ -109,7 +109,7 @@ bool dce110_mem_input_program_surface_flip_and_addr(
- bool dce110_mem_input_program_surface_config(
- struct mem_input *mem_input,
- enum surface_pixel_format format,
-- union plane_tiling_info *tiling_info,
-+ union dc_tiling_info *tiling_info,
- union plane_size *plane_size,
- enum dc_rotation_angle rotation);
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c
-index 99163ee..7dcfd2e 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c
-@@ -30,6 +30,7 @@
- #include "dce/dce_11_0_sh_mask.h"
-
- #include "dce110_opp.h"
-+#include "gamma_types.h"
-
- enum {
- MAX_LUT_ENTRY = 256,
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.h
-index f9b828c..e53eb74 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.h
-@@ -27,7 +27,9 @@
-
- #include "dc_types.h"
- #include "inc/opp.h"
-+#include "gamma_types.h"
-
-+struct gamma_parameters;
-
- #define FROM_DCE11_OPP(opp)\
- container_of(opp, struct dce110_opp, base)
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma.c
-index dceba7d..f589025 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma.c
-@@ -30,6 +30,7 @@
- #include "dce/dce_11_0_sh_mask.h"
-
- #include "dce110_opp.h"
-+#include "gamma_types.h"
-
- #define DCP_REG(reg)\
- (reg + opp110->offsets.dcp_offset)
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_bit_depth.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_bit_depth.c
-index d0e4b98..a64a507 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_bit_depth.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_bit_depth.c
-@@ -30,7 +30,7 @@
- #include "dce/dce_11_0_sh_mask.h"
-
- #include "dce110_transform.h"
--
-+#include "opp.h"
- #include "include/logger_interface.h"
- #include "include/fixed32_32.h"
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-index d075de1..e3b5918 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-@@ -70,6 +70,7 @@ void enable_surface_flip_reporting(struct dc_surface *dc_surface,
- #include "audio_interface.h"
- #include "scaler_types.h"
- #include "hw_sequencer_types.h"
-+#include "opp.h"
-
- #define DC_STREAM_TO_CORE(dc_stream) container_of( \
- dc_stream, struct core_stream, public)
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/gamma_types.h b/drivers/gpu/drm/amd/dal/dc/inc/gamma_types.h
-new file mode 100644
-index 0000000..048303e
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/gamma_types.h
-@@ -0,0 +1,117 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+#ifndef GAMMA_TYPES_H_
-+#define GAMMA_TYPES_H_
-+
-+#include "dc_types.h"
-+#include "dc_services_types.h"
-+
-+/* TODO: Used in IPP and OPP */
-+struct dev_c_lut {
-+ uint8_t red;
-+ uint8_t green;
-+ uint8_t blue;
-+};
-+
-+struct dev_c_lut16 {
-+ uint16_t red;
-+ uint16_t green;
-+ uint16_t blue;
-+};
-+
-+struct regamma_ramp {
-+ uint16_t gamma[RGB_256X3X16 * 3];
-+};
-+
-+/* used by Graphics and Overlay gamma */
-+struct gamma_coeff {
-+ int32_t gamma[3];
-+ int32_t a0[3]; /* index 0 for red, 1 for green, 2 for blue */
-+ int32_t a1[3];
-+ int32_t a2[3];
-+ int32_t a3[3];
-+};
-+
-+struct regamma_lut {
-+ union {
-+ struct {
-+ uint32_t GRAPHICS_DEGAMMA_SRGB :1;
-+ uint32_t OVERLAY_DEGAMMA_SRGB :1;
-+ uint32_t GAMMA_RAMP_ARRAY :1;
-+ uint32_t APPLY_DEGAMMA :1;
-+ uint32_t RESERVED :28;
-+ } bits;
-+ uint32_t value;
-+ } features;
-+
-+ union {
-+ struct regamma_ramp regamma_ramp;
-+ struct gamma_coeff gamma_coeff;
-+ };
-+};
-+
-+union gamma_flag {
-+ struct {
-+ uint32_t config_is_changed :1;
-+ uint32_t both_pipe_req :1;
-+ uint32_t regamma_update :1;
-+ uint32_t gamma_update :1;
-+ uint32_t reserved :28;
-+ } bits;
-+ uint32_t u_all;
-+};
-+
-+enum graphics_regamma_adjust {
-+ GRAPHICS_REGAMMA_ADJUST_BYPASS = 0, GRAPHICS_REGAMMA_ADJUST_HW, /* without adjustments */
-+ GRAPHICS_REGAMMA_ADJUST_SW /* use adjustments */
-+};
-+
-+enum graphics_gamma_lut {
-+ GRAPHICS_GAMMA_LUT_LEGACY = 0, /* use only legacy LUT */
-+ GRAPHICS_GAMMA_LUT_REGAMMA, /* use only regamma LUT */
-+ GRAPHICS_GAMMA_LUT_LEGACY_AND_REGAMMA /* use legacy & regamma LUT's */
-+};
-+
-+enum graphics_degamma_adjust {
-+ GRAPHICS_DEGAMMA_ADJUST_BYPASS = 0, GRAPHICS_DEGAMMA_ADJUST_HW, /*without adjustments */
-+ GRAPHICS_DEGAMMA_ADJUST_SW /* use adjustments */
-+};
-+
-+struct gamma_parameters {
-+ union gamma_flag flag;
-+ enum pixel_format surface_pixel_format; /*OS surface pixel format*/
-+ struct regamma_lut regamma;
-+
-+ enum graphics_regamma_adjust regamma_adjust_type;
-+ enum graphics_degamma_adjust degamma_adjust_type;
-+
-+ enum graphics_gamma_lut selected_gamma_lut;
-+
-+ bool disable_adjustments;
-+
-+ /* here we grow with parameters if necessary */
-+};
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
-index 0bbf9b5..1dedf7c 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
-@@ -27,6 +27,15 @@
- #define __DC_HW_SEQUENCER_H__
- #include "core_types.h"
-
-+struct gamma_parameters;
-+
-+enum pipe_gating_control {
-+ PIPE_GATING_CONTROL_DISABLE = 0,
-+ PIPE_GATING_CONTROL_ENABLE,
-+ PIPE_GATING_CONTROL_INIT
-+};
-+
-+
- struct hw_sequencer_funcs {
-
- enum dc_status (*apply_ctx_to_hw)(
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/ipp.h b/drivers/gpu/drm/amd/dal/dc/inc/ipp.h
-index e7151cd..8e7cc31 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/ipp.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/ipp.h
-@@ -32,6 +32,7 @@
- #include "include/video_csc_types.h"
- #include "include/hw_sequencer_types.h"
-
-+struct dev_c_lut;
-
- #define MAXTRIX_COEFFICIENTS_NUMBER 12
- #define MAXTRIX_COEFFICIENTS_WRAP_NUMBER (MAXTRIX_COEFFICIENTS_NUMBER + 4)
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/mem_input.h b/drivers/gpu/drm/amd/dal/dc/inc/mem_input.h
-index 2647f84..4d653ab 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/mem_input.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/mem_input.h
-@@ -57,7 +57,7 @@ struct mem_input_funcs {
- bool (*mem_input_program_surface_config)(
- struct mem_input *mem_input,
- enum surface_pixel_format format,
-- union plane_tiling_info *tiling_info,
-+ union dc_tiling_info *tiling_info,
- union plane_size *plane_size,
- enum dc_rotation_angle rotation);
- };
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/opp.h b/drivers/gpu/drm/amd/dal/dc/inc/opp.h
-index 543848a..f2171de 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/opp.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/opp.h
-@@ -26,14 +26,74 @@
- #ifndef __DAL_OPP_H__
- #define __DAL_OPP_H__
-
--#include "dc_temp.h"
-+#include "dc_types.h"
- #include "grph_object_id.h"
- #include "grph_csc_types.h"
-+#include "dc_services_types.h"
-
- struct fixed31_32;
-+struct gamma_parameters;
-
- /* TODO: Need cleanup */
-
-+enum clamping_range {
-+ CLAMPING_FULL_RANGE = 0, /* No Clamping */
-+ CLAMPING_LIMITED_RANGE_8BPC, /* 8 bpc: Clamping 1 to FE */
-+ CLAMPING_LIMITED_RANGE_10BPC, /* 10 bpc: Clamping 4 to 3FB */
-+ CLAMPING_LIMITED_RANGE_12BPC, /* 12 bpc: Clamping 10 to FEF */
-+ /* Use programmable clampping value on FMT_CLAMP_COMPONENT_R/G/B. */
-+ CLAMPING_LIMITED_RANGE_PROGRAMMABLE
-+};
-+
-+struct clamping_and_pixel_encoding_params {
-+ enum dc_pixel_encoding pixel_encoding; /* Pixel Encoding */
-+ enum clamping_range clamping_level; /* Clamping identifier */
-+ enum dc_color_depth c_depth; /* Deep color use. */
-+};
-+
-+struct bit_depth_reduction_params {
-+ struct {
-+ /* truncate/round */
-+ /* trunc/round enabled*/
-+ uint32_t TRUNCATE_ENABLED:1;
-+ /* 2 bits: 0=6 bpc, 1=8 bpc, 2 = 10bpc*/
-+ uint32_t TRUNCATE_DEPTH:2;
-+ /* truncate or round*/
-+ uint32_t TRUNCATE_MODE:1;
-+
-+ /* spatial dither */
-+ /* Spatial Bit Depth Reduction enabled*/
-+ uint32_t SPATIAL_DITHER_ENABLED:1;
-+ /* 2 bits: 0=6 bpc, 1 = 8 bpc, 2 = 10bpc*/
-+ uint32_t SPATIAL_DITHER_DEPTH:2;
-+ /* 0-3 to select patterns*/
-+ uint32_t SPATIAL_DITHER_MODE:2;
-+ /* Enable RGB random dithering*/
-+ uint32_t RGB_RANDOM:1;
-+ /* Enable Frame random dithering*/
-+ uint32_t FRAME_RANDOM:1;
-+ /* Enable HighPass random dithering*/
-+ uint32_t HIGHPASS_RANDOM:1;
-+
-+ /* temporal dither*/
-+ /* frame modulation enabled*/
-+ uint32_t FRAME_MODULATION_ENABLED:1;
-+ /* same as for trunc/spatial*/
-+ uint32_t FRAME_MODULATION_DEPTH:2;
-+ /* 2/4 gray levels*/
-+ uint32_t TEMPORAL_LEVEL:1;
-+ uint32_t FRC25:2;
-+ uint32_t FRC50:2;
-+ uint32_t FRC75:2;
-+ } flags;
-+
-+ uint32_t r_seed_value;
-+ uint32_t b_seed_value;
-+ uint32_t g_seed_value;
-+};
-+
-+
-+
- enum wide_gamut_regamma_mode {
- /* 0x0 - BITS2:0 Bypass */
- WIDE_GAMUT_REGAMMA_MODE_GRAPHICS_BYPASS,
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/transform.h b/drivers/gpu/drm/amd/dal/dc/inc/transform.h
-index d453aac..2280357 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/transform.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/transform.h
-@@ -31,6 +31,8 @@
- #include "calcs/scaler_filter.h"
- #include "grph_object_id.h"
-
-+struct bit_depth_reduction_params;
-+
- enum scaling_type {
- SCALING_TYPE_NO_SCALING = 0,
- SCALING_TYPE_UPSCALING,
-diff --git a/drivers/gpu/drm/amd/dal/include/fixed32_32.h b/drivers/gpu/drm/amd/dal/include/fixed32_32.h
-index 5fca957..1a26eea 100644
---- a/drivers/gpu/drm/amd/dal/include/fixed32_32.h
-+++ b/drivers/gpu/drm/amd/dal/include/fixed32_32.h
-@@ -26,6 +26,8 @@
- #ifndef __DAL_FIXED32_32_H__
- #define __DAL_FIXED32_32_H__
-
-+#include "dc_services_types.h"
-+
- struct fixed32_32 {
- uint64_t value;
- };
-diff --git a/drivers/gpu/drm/amd/dal/include/video_gamma_types.h b/drivers/gpu/drm/amd/dal/include/video_gamma_types.h
-index dc294b6..6f9cd3f 100644
---- a/drivers/gpu/drm/amd/dal/include/video_gamma_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/video_gamma_types.h
-@@ -27,6 +27,7 @@
- #define __DAL_VIDEO_GAMMA_TYPES_H__
-
- #include "set_mode_types.h"
-+#include "gamma_types.h"
-
- enum overlay_gamma_adjust {
- OVERLAY_GAMMA_ADJUST_BYPASS,
---
-2.7.4
-
generated by cgit 1.2.3-korg (git 2.39.0) at 2024-04-23 09:12:37 +0000