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-rw-r--r--common/recipes-kernel/linux/files/0723-drm-amd-dal-dc-clean-up-remove-dvo-related.patch1791
1 files changed, 1791 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/files/0723-drm-amd-dal-dc-clean-up-remove-dvo-related.patch b/common/recipes-kernel/linux/files/0723-drm-amd-dal-dc-clean-up-remove-dvo-related.patch
new file mode 100644
index 00000000..afae08d7
--- /dev/null
+++ b/common/recipes-kernel/linux/files/0723-drm-amd-dal-dc-clean-up-remove-dvo-related.patch
@@ -0,0 +1,1791 @@
+From ea839f5eb154581fccd3db4b8878a251802e15b5 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Fri, 29 Jan 2016 15:36:48 -0500
+Subject: [PATCH 0723/1110] drm/amd/dal: dc clean up - remove dvo related
+
+Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
+Acked-by: Harry Wentland <harry.wentland@amd.com>
+---
+ drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c | 69 +----
+ drivers/gpu/drm/amd/dal/dc/bios/command_table.c | 111 -------
+ drivers/gpu/drm/amd/dal/dc/bios/command_table.h | 3 -
+ .../gpu/drm/amd/dal/dc/bios/command_table_helper.c | 37 ---
+ .../dc/bios/dce110/command_table_helper_dce110.c | 4 -
+ drivers/gpu/drm/amd/dal/dc/dc_bios_types.h | 3 -
+ .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c | 3 +-
+ drivers/gpu/drm/amd/dal/dc/gpio/Makefile | 2 +-
+ .../drm/amd/dal/dc/gpio/dce110/hw_factory_dce110.c | 4 -
+ .../amd/dal/dc/gpio/dce110/hw_translate_dce110.c | 40 ---
+ .../amd/dal/dc/gpio/diagnostics/hw_factory_diag.c | 5 -
+ drivers/gpu/drm/amd/dal/dc/gpio/dvo.c | 138 ---------
+ drivers/gpu/drm/amd/dal/dc/gpio/dvo.h | 42 ---
+ drivers/gpu/drm/amd/dal/dc/gpio/gpio_service.c | 88 ------
+ drivers/gpu/drm/amd/dal/dc/gpio/hw_dvo.c | 318 ---------------------
+ drivers/gpu/drm/amd/dal/dc/gpio/hw_dvo.h | 89 ------
+ drivers/gpu/drm/amd/dal/dc/gpio/hw_factory.h | 4 -
+ .../amd/dal/dc/gpu/dce110/display_clock_dce110.c | 11 +-
+ .../dal/dc/gpu/dce110/pll_clock_source_dce110.c | 4 +-
+ drivers/gpu/drm/amd/dal/dc/gpu/ext_clock_source.c | 1 -
+ drivers/gpu/drm/amd/dal/dc/gpu/pll_clock_source.c | 3 -
+ drivers/gpu/drm/amd/dal/include/audio_types.h | 1 -
+ .../gpu/drm/amd/dal/include/bios_parser_types.h | 31 --
+ .../gpu/drm/amd/dal/include/clock_source_types.h | 5 -
+ .../drm/amd/dal/include/display_clock_interface.h | 1 -
+ drivers/gpu/drm/amd/dal/include/dvo_interface.h | 48 ----
+ .../drm/amd/dal/include/gpio_service_interface.h | 14 -
+ drivers/gpu/drm/amd/dal/include/gpio_types.h | 54 +---
+ .../drm/amd/dal/include/grph_object_ctrl_defs.h | 7 -
+ drivers/gpu/drm/amd/dal/include/grph_object_id.h | 21 --
+ 30 files changed, 12 insertions(+), 1149 deletions(-)
+ delete mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/dvo.c
+ delete mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/dvo.h
+ delete mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/hw_dvo.c
+ delete mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/hw_dvo.h
+ delete mode 100644 drivers/gpu/drm/amd/dal/include/dvo_interface.h
+
+diff --git a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c
+index 3ca165b..8d675f0 100644
+--- a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c
++++ b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c
+@@ -1295,18 +1295,6 @@ static enum bp_result bios_parser_get_divider_for_target_display_clock(
+ return bp->cmd_tbl.compute_memore_engine_pll(bp, bp_params);
+ }
+
+-static enum bp_result bios_parser_dvo_encoder_control(
+- struct dc_bios *dcb,
+- struct bp_dvo_encoder_control *cntl)
+-{
+- struct bios_parser *bp = BP_FROM_DCB(dcb);
+-
+- if (!bp->cmd_tbl.dvo_encoder_control)
+- return BP_RESULT_FAILURE;
+-
+- return bp->cmd_tbl.dvo_encoder_control(bp, cntl);
+-}
+-
+ static enum bp_result bios_parser_enable_crtc(
+ struct dc_bios *dcb,
+ enum controller_id id,
+@@ -3143,78 +3131,27 @@ static enum encoder_id encoder_id_from_bios_object_id(uint32_t bios_object_id)
+ case ENCODER_OBJECT_ID_INTERNAL_DAC2:
+ id = ENCODER_ID_INTERNAL_DAC2;
+ break;
+- case ENCODER_OBJECT_ID_INTERNAL_SDVOA:
+- id = ENCODER_ID_INTERNAL_SDVOA;
+- break;
+- case ENCODER_OBJECT_ID_INTERNAL_SDVOB:
+- id = ENCODER_ID_INTERNAL_SDVOB;
+- break;
+- case ENCODER_OBJECT_ID_SI170B:
+- id = ENCODER_ID_EXTERNAL_SI170B;
+- break;
+- case ENCODER_OBJECT_ID_CH7303:
+- id = ENCODER_ID_EXTERNAL_CH7303;
+- break;
+- case ENCODER_OBJECT_ID_CH7301:
+- id = ENCODER_ID_EXTERNAL_CH7301;
+- break;
+- case ENCODER_OBJECT_ID_INTERNAL_DVO1:
+- id = ENCODER_ID_INTERNAL_DVO1;
+- break;
+- case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
+- id = ENCODER_ID_EXTERNAL_SDVOA;
+- break;
+- case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
+- id = ENCODER_ID_EXTERNAL_SDVOB;
+- break;
+- case ENCODER_OBJECT_ID_TITFP513:
+- id = ENCODER_ID_EXTERNAL_TITFP513;
+- break;
+ case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
+ id = ENCODER_ID_INTERNAL_LVTM1;
+ break;
+- case ENCODER_OBJECT_ID_VT1623:
+- id = ENCODER_ID_EXTERNAL_VT1623;
+- break;
+- case ENCODER_OBJECT_ID_HDMI_SI1930:
+- id = ENCODER_ID_EXTERNAL_SI1930;
+- break;
+ case ENCODER_OBJECT_ID_HDMI_INTERNAL:
+ id = ENCODER_ID_INTERNAL_HDMI;
+ break;
+ case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
+ id = ENCODER_ID_INTERNAL_KLDSCP_TMDS1;
+ break;
+- case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
+- id = ENCODER_ID_INTERNAL_KLDSCP_DVO1;
+- break;
+ case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
+ id = ENCODER_ID_INTERNAL_KLDSCP_DAC1;
+ break;
+ case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
+ id = ENCODER_ID_INTERNAL_KLDSCP_DAC2;
+ break;
+- case ENCODER_OBJECT_ID_SI178:
+- id = ENCODER_ID_EXTERNAL_SI178;
+- break;
+ case ENCODER_OBJECT_ID_MVPU_FPGA:
+ id = ENCODER_ID_EXTERNAL_MVPU_FPGA;
+ break;
+ case ENCODER_OBJECT_ID_INTERNAL_DDI:
+ id = ENCODER_ID_INTERNAL_DDI;
+ break;
+- case ENCODER_OBJECT_ID_VT1625:
+- id = ENCODER_ID_EXTERNAL_VT1625;
+- break;
+- case ENCODER_OBJECT_ID_HDMI_SI1932:
+- id = ENCODER_ID_EXTERNAL_SI1932;
+- break;
+- case ENCODER_OBJECT_ID_DP_AN9801:
+- id = ENCODER_ID_EXTERNAL_AN9801;
+- break;
+- case ENCODER_OBJECT_ID_DP_DP501:
+- id = ENCODER_ID_EXTERNAL_DP501;
+- break;
+ case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
+ id = ENCODER_ID_INTERNAL_UNIPHY;
+ break;
+@@ -3227,9 +3164,6 @@ static enum encoder_id encoder_id_from_bios_object_id(uint32_t bios_object_id)
+ case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
+ id = ENCODER_ID_INTERNAL_UNIPHY2;
+ break;
+- case ENCODER_OBJECT_ID_GENERAL_EXTERNAL_DVO:
+- id = ENCODER_ID_EXTERNAL_GENERIC_DVO;
+- break;
+ case ENCODER_OBJECT_ID_ALMOND: /* ENCODER_OBJECT_ID_NUTMEG */
+ id = ENCODER_ID_EXTERNAL_NUTMEG;
+ break;
+@@ -3241,6 +3175,7 @@ static enum encoder_id encoder_id_from_bios_object_id(uint32_t bios_object_id)
+ break;
+ default:
+ id = ENCODER_ID_UNKNOWN;
++ ASSERT(0);
+ break;
+ }
+
+@@ -4966,8 +4901,6 @@ static const struct dc_vbios_funcs vbios_funcs = {
+
+ .crt_control = bios_parser_crt_control,
+
+- .dvo_encoder_control = bios_parser_dvo_encoder_control,
+-
+ .enable_crtc = bios_parser_enable_crtc,
+
+ .adjust_pixel_clock = bios_parser_adjust_pixel_clock,
+diff --git a/drivers/gpu/drm/amd/dal/dc/bios/command_table.c b/drivers/gpu/drm/amd/dal/dc/bios/command_table.c
+index 87fc14b..cba54f3 100644
+--- a/drivers/gpu/drm/amd/dal/dc/bios/command_table.c
++++ b/drivers/gpu/drm/amd/dal/dc/bios/command_table.c
+@@ -49,7 +49,6 @@
+
+
+ static void init_dig_encoder_control(struct bios_parser *bp);
+-static void init_dvo_encoder_control(struct bios_parser *bp);
+ static void init_transmitter_control(struct bios_parser *bp);
+ static void init_set_pixel_clock(struct bios_parser *bp);
+ static void init_enable_spread_spectrum_on_ppll(struct bios_parser *bp);
+@@ -72,7 +71,6 @@ static void init_set_dce_clock(struct bios_parser *bp);
+ void dal_bios_parser_init_cmd_tbl(struct bios_parser *bp)
+ {
+ init_dig_encoder_control(bp);
+- init_dvo_encoder_control(bp);
+ init_transmitter_control(bp);
+ init_set_pixel_clock(bp);
+ init_enable_spread_spectrum_on_ppll(bp);
+@@ -309,65 +307,6 @@ static enum bp_result encoder_control_digx_v4(
+ /*******************************************************************************
+ ********************************************************************************
+ **
+- ** DVO ENCODER CONTROL
+- **
+- ********************************************************************************
+- *******************************************************************************/
+-
+-static enum bp_result dvo_encoder_control_v3(
+- struct bios_parser *bp,
+- struct bp_dvo_encoder_control *cntl);
+-
+-static void init_dvo_encoder_control(struct bios_parser *bp)
+-{
+- switch (BIOS_CMD_TABLE_PARA_REVISION(DVOEncoderControl)) {
+- case 3:
+- bp->cmd_tbl.dvo_encoder_control = dvo_encoder_control_v3;
+- break;
+- default:
+- bp->cmd_tbl.dvo_encoder_control = NULL;
+- break;
+- }
+-}
+-
+-static enum bp_result dvo_encoder_control_v3(
+- struct bios_parser *bp,
+- struct bp_dvo_encoder_control *cntl)
+-{
+- enum bp_result result = BP_RESULT_FAILURE;
+- DVO_ENCODER_CONTROL_PARAMETERS_V3 params;
+- uint8_t config = 0;
+-
+- if (cntl->memory_rate == DVO_ENCODER_MEMORY_RATE_SDR)
+- config |= DVO_ENCODER_CONFIG_SDR_SPEED;
+-
+- switch (cntl->interface_width) {
+- case DVO_ENCODER_INTERFACE_WIDTH_FULL24BIT:
+- config |= DVO_ENCODER_CONFIG_24BIT;
+- break;
+- case DVO_ENCODER_INTERFACE_WIDTH_HIGH12BIT:
+- config |= DVO_ENCODER_CONFIG_UPPER12BIT;
+- break;
+- default:
+- config |= DVO_ENCODER_CONFIG_LOW12BIT;
+- break;
+- }
+-
+- /* We need to convert from KHz units into 10KHz units */
+- dc_service_memset(&params, 0, sizeof(params));
+- params.ucAction = (uint8_t) cntl->action;
+- params.usPixelClock = cpu_to_le16((uint16_t) (cntl->pixel_clock / 10));
+- params.ucDVOConfig = config;
+-
+- if (EXEC_BIOS_CMD_TABLE(DVOEncoderControl, params))
+- result = BP_RESULT_OK;
+-
+- return result;
+-}
+-
+-/*******************************************************************************
+- ********************************************************************************
+- **
+ ** TRANSMITTER CONTROL
+ **
+ ********************************************************************************
+@@ -1515,17 +1454,6 @@ static void init_adjust_display_pll(struct bios_parser *bp)
+ }
+ }
+
+-static bool adjust_display_pll_bug_patch(ADJUST_DISPLAY_PLL_PARAMETERS *params)
+-{
+- /* vbios bug: pixel clock should not be doubled for DVO with 24bit
+- * interface */
+- if ((params->ucTransmitterID == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
+- && (params->ucDVOConfig == DVO_ENCODER_CONFIG_24BIT))
+- /* the current pixel clock is good. no adjustment is required */
+- return true;
+- return false;
+-}
+-
+ static enum bp_result adjust_display_pll_v2(
+ struct bios_parser *bp,
+ struct bp_adjust_pixel_clock_parameters *bp_params)
+@@ -1545,23 +1473,6 @@ static enum bp_result adjust_display_pll_v2(
+ params.ucEncodeMode =
+ (uint8_t)bp->cmd_helper->encoder_mode_bp_to_atom(
+ bp_params->signal_type, false);
+- params.ucDVOConfig = (uint8_t)(bp_params->dvo_config);
+-
+- if (adjust_display_pll_bug_patch(&params)
+- || EXEC_BIOS_CMD_TABLE(AdjustDisplayPll, params)) {
+- /* Convert output pixel clock back 10KHz-->KHz: multiply
+- * original pixel clock in KHz by ratio
+- * [output pxlClk/input pxlClk] */
+- uint64_t pixel_clock_10KHz_out =
+- le16_to_cpu((uint64_t)params.usPixelClock);
+- uint64_t pixel_clock = (uint64_t)bp_params->pixel_clock;
+-
+- bp_params->adjusted_pixel_clock =
+- div_u64(pixel_clock * pixel_clock_10KHz_out,
+- pixel_clock_10KHz_in);
+- result = BP_RESULT_OK;
+- }
+-
+ return result;
+ }
+
+@@ -1586,25 +1497,6 @@ static enum bp_result adjust_display_pll_v3(
+ (uint8_t)bp->cmd_helper->encoder_mode_bp_to_atom(
+ bp_params->signal_type, false);
+
+- if (DISP_PLL_CONFIG_DVO_DDR_MODE_LOW_12BIT ==
+- bp_params->display_pll_config)
+- params.sInput.ucDispPllConfig =
+- DISPPLL_CONFIG_DVO_DDR_SPEED |
+- DISPPLL_CONFIG_DVO_LOW12BIT;
+- else if (DISP_PLL_CONFIG_DVO_DDR_MODE_UPPER_12BIT ==
+- bp_params->display_pll_config)
+- params.sInput.ucDispPllConfig =
+- DISPPLL_CONFIG_DVO_DDR_SPEED |
+- DISPPLL_CONFIG_DVO_UPPER12BIT;
+- else if (DISP_PLL_CONFIG_DVO_DDR_MODE_24BIT ==
+- bp_params->display_pll_config)
+- params.sInput.ucDispPllConfig =
+- DISPPLL_CONFIG_DVO_DDR_SPEED | DISPPLL_CONFIG_DVO_24BIT;
+- else
+- /* this does not mean anything here */
+- params.sInput.ucDispPllConfig =
+- (uint8_t)(bp_params->display_pll_config);
+-
+ if (bp_params->ss_enable == true)
+ params.sInput.ucDispPllConfig |= DISPPLL_CONFIG_SS_ENABLE;
+
+@@ -1873,9 +1765,6 @@ static enum signal_type dac_load_detection_v3(
+ case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
+ params.sDacload.ucDacType = ATOM_DAC_B;
+ break;
+- case ENCODER_ID_EXTERNAL_CH7303:
+- params.sDacload.ucDacType = ATOM_EXT_DAC;
+- break;
+ default:
+ return signal;
+ }
+diff --git a/drivers/gpu/drm/amd/dal/dc/bios/command_table.h b/drivers/gpu/drm/amd/dal/dc/bios/command_table.h
+index e233ea6..3cb0c7f 100644
+--- a/drivers/gpu/drm/amd/dal/dc/bios/command_table.h
++++ b/drivers/gpu/drm/amd/dal/dc/bios/command_table.h
+@@ -39,9 +39,6 @@ struct cmd_tbl {
+ enum bp_result (*encoder_control_dig2)(
+ struct bios_parser *bp,
+ struct bp_encoder_control *control);
+- enum bp_result (*dvo_encoder_control)(
+- struct bios_parser *bp,
+- struct bp_dvo_encoder_control *cntl);
+ enum bp_result (*transmitter_control)(
+ struct bios_parser *bp,
+ struct bp_transmitter_control *control);
+diff --git a/drivers/gpu/drm/amd/dal/dc/bios/command_table_helper.c b/drivers/gpu/drm/amd/dal/dc/bios/command_table_helper.c
+index 83a80d5..36d1240 100644
+--- a/drivers/gpu/drm/amd/dal/dc/bios/command_table_helper.c
++++ b/drivers/gpu/drm/amd/dal/dc/bios/command_table_helper.c
+@@ -245,30 +245,8 @@ uint8_t dal_cmd_table_helper_encoder_id_to_atom(
+ return ENCODER_OBJECT_ID_INTERNAL_DAC1;
+ case ENCODER_ID_INTERNAL_DAC2:
+ return ENCODER_OBJECT_ID_INTERNAL_DAC2;
+- case ENCODER_ID_INTERNAL_SDVOA:
+- return ENCODER_OBJECT_ID_INTERNAL_SDVOA;
+- case ENCODER_ID_INTERNAL_SDVOB:
+- return ENCODER_OBJECT_ID_INTERNAL_SDVOB;
+- case ENCODER_ID_EXTERNAL_SI170B:
+- return ENCODER_OBJECT_ID_SI170B;
+- case ENCODER_ID_EXTERNAL_CH7303:
+- return ENCODER_OBJECT_ID_CH7303;
+- case ENCODER_ID_EXTERNAL_CH7301:
+- return ENCODER_OBJECT_ID_CH7301;
+- case ENCODER_ID_INTERNAL_DVO1:
+- return ENCODER_OBJECT_ID_INTERNAL_DVO1;
+- case ENCODER_ID_EXTERNAL_SDVOA:
+- return ENCODER_OBJECT_ID_EXTERNAL_SDVOA;
+- case ENCODER_ID_EXTERNAL_SDVOB:
+- return ENCODER_OBJECT_ID_EXTERNAL_SDVOB;
+- case ENCODER_ID_EXTERNAL_TITFP513:
+- return ENCODER_OBJECT_ID_TITFP513;
+ case ENCODER_ID_INTERNAL_LVTM1:
+ return ENCODER_OBJECT_ID_INTERNAL_LVTM1;
+- case ENCODER_ID_EXTERNAL_VT1623:
+- return ENCODER_OBJECT_ID_VT1623;
+- case ENCODER_ID_EXTERNAL_SI1930:
+- return ENCODER_OBJECT_ID_HDMI_SI1930;
+ case ENCODER_ID_INTERNAL_HDMI:
+ return ENCODER_OBJECT_ID_HDMI_INTERNAL;
+ case ENCODER_ID_EXTERNAL_TRAVIS:
+@@ -277,26 +255,14 @@ uint8_t dal_cmd_table_helper_encoder_id_to_atom(
+ return ENCODER_OBJECT_ID_NUTMEG;
+ case ENCODER_ID_INTERNAL_KLDSCP_TMDS1:
+ return ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1;
+- case ENCODER_ID_INTERNAL_KLDSCP_DVO1:
+- return ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1;
+ case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
+ return ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1;
+ case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
+ return ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2;
+- case ENCODER_ID_EXTERNAL_SI178:
+- return ENCODER_OBJECT_ID_SI178;
+ case ENCODER_ID_EXTERNAL_MVPU_FPGA:
+ return ENCODER_OBJECT_ID_MVPU_FPGA;
+ case ENCODER_ID_INTERNAL_DDI:
+ return ENCODER_OBJECT_ID_INTERNAL_DDI;
+- case ENCODER_ID_EXTERNAL_VT1625:
+- return ENCODER_OBJECT_ID_VT1625;
+- case ENCODER_ID_EXTERNAL_SI1932:
+- return ENCODER_OBJECT_ID_HDMI_SI1932;
+- case ENCODER_ID_EXTERNAL_AN9801:
+- return ENCODER_OBJECT_ID_DP_AN9801;
+- case ENCODER_ID_EXTERNAL_DP501:
+- return ENCODER_OBJECT_ID_DP_DP501;
+ case ENCODER_ID_INTERNAL_UNIPHY:
+ return ENCODER_OBJECT_ID_INTERNAL_UNIPHY;
+ case ENCODER_ID_INTERNAL_KLDSCP_LVTMA:
+@@ -309,9 +275,6 @@ uint8_t dal_cmd_table_helper_encoder_id_to_atom(
+ return ENCODER_OBJECT_ID_INTERNAL_UNIPHY3;
+ case ENCODER_ID_INTERNAL_WIRELESS:
+ return ENCODER_OBJECT_ID_INTERNAL_VCE;
+- case ENCODER_ID_EXTERNAL_GENERIC_DVO:
+- return ENCODER_OBJECT_ID_GENERAL_EXTERNAL_DVO;
+- case ENCODER_ID_INTERNAL_VIRTUAL:
+ case ENCODER_ID_UNKNOWN:
+ return ENCODER_OBJECT_ID_NONE;
+ default:
+diff --git a/drivers/gpu/drm/amd/dal/dc/bios/dce110/command_table_helper_dce110.c b/drivers/gpu/drm/amd/dal/dc/bios/dce110/command_table_helper_dce110.c
+index e75b51b..0319382 100644
+--- a/drivers/gpu/drm/amd/dal/dc/bios/dce110/command_table_helper_dce110.c
++++ b/drivers/gpu/drm/amd/dal/dc/bios/dce110/command_table_helper_dce110.c
+@@ -270,10 +270,6 @@ static bool engine_bp_to_atom(enum engine_id id, uint32_t *atom_engine_id)
+ *atom_engine_id = ASIC_INT_DIG7_ENCODER_ID;
+ result = true;
+ break;
+- case ENGINE_ID_DVO:
+- *atom_engine_id = ASIC_EXT_DIG_ENCODER_ID;
+- result = true;
+- break;
+ case ENGINE_ID_DACA:
+ *atom_engine_id = ASIC_INT_DAC1_ENCODER_ID;
+ result = true;
+diff --git a/drivers/gpu/drm/amd/dal/dc/dc_bios_types.h b/drivers/gpu/drm/amd/dal/dc/dc_bios_types.h
+index 0f85f63..53f0477 100644
+--- a/drivers/gpu/drm/amd/dal/dc/dc_bios_types.h
++++ b/drivers/gpu/drm/amd/dal/dc/dc_bios_types.h
+@@ -207,9 +207,6 @@ struct dc_vbios_funcs {
+ enum engine_id engine_id,
+ bool enable,
+ uint32_t pixel_clock);
+- enum bp_result (*dvo_encoder_control)(
+- struct dc_bios *bios,
+- struct bp_dvo_encoder_control *cntl);
+ enum bp_result (*enable_crtc)(
+ struct dc_bios *bios,
+ enum controller_id id,
+diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
+index f899565..0eafe16 100644
+--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
+@@ -1090,7 +1090,8 @@ static bool dc_set_clocks_and_clock_state (
+ * that state.
+ *
+ * Update the clock state here (prior to setting Pixel clock,
+- * DVO clock, or Display clock) */
++ * or Display clock)
++ **/
+ if (!dal_display_clock_set_min_clocks_state(
+ disp_clk, context->res_ctx.required_clocks_state)) {
+ BREAK_TO_DEBUGGER();
+diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/Makefile b/drivers/gpu/drm/amd/dal/dc/gpio/Makefile
+index 50a1d34..2507bb5 100644
+--- a/drivers/gpu/drm/amd/dal/dc/gpio/Makefile
++++ b/drivers/gpu/drm/amd/dal/dc/gpio/Makefile
+@@ -2,7 +2,7 @@
+ # Makefile for the 'gpio' sub-component of DAL.
+ # It provides the control and status of HW GPIO pins.
+
+-GPIO = ddc.o dvo.o gpio_base.o gpio_service.o hw_ddc.o hw_dvo.o hw_factory.o \
++GPIO = ddc.o gpio_base.o gpio_service.o hw_ddc.o hw_factory.o \
+ hw_gpio.o hw_gpio_pad.o hw_gpio_pin.o hw_hpd.o hw_translate.o irq.o
+
+ AMD_DAL_GPIO = $(addprefix $(AMDDALPATH)/dc/gpio/,$(GPIO))
+diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_factory_dce110.c b/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_factory_dce110.c
+index 85644c5..55d6986 100644
+--- a/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_factory_dce110.c
++++ b/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_factory_dce110.c
+@@ -46,7 +46,6 @@
+
+ /* fucntion table */
+ static const struct hw_factory_funcs funcs = {
+- .create_dvo = NULL,
+ .create_ddc_data = dal_hw_ddc_dce110_create,
+ .create_ddc_clock = dal_hw_ddc_dce110_create,
+ .create_generic = NULL,
+@@ -68,9 +67,6 @@ static const struct hw_factory_funcs funcs = {
+ void dal_hw_factory_dce110_init(struct hw_factory *factory)
+ {
+ /*TODO check ASIC CAPs*/
+- factory->number_of_pins[GPIO_ID_DVO1] = 24;
+- factory->number_of_pins[GPIO_ID_DVO12] = 2;
+- factory->number_of_pins[GPIO_ID_DVO24] = 1;
+ factory->number_of_pins[GPIO_ID_DDC_DATA] = 8;
+ factory->number_of_pins[GPIO_ID_DDC_CLOCK] = 8;
+ factory->number_of_pins[GPIO_ID_GENERIC] = 7;
+diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_translate_dce110.c b/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_translate_dce110.c
+index 05ac0b2..38512fa 100644
+--- a/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_translate_dce110.c
++++ b/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_translate_dce110.c
+@@ -45,7 +45,6 @@
+ */
+
+ #include "../hw_gpio_pin.h"
+-#include "../hw_dvo.h"
+
+ #include "dce/dce_11_0_d.h"
+ #include "dce/dce_11_0_sh_mask.h"
+@@ -57,26 +56,6 @@ static bool offset_to_id(
+ uint32_t *en)
+ {
+ switch (offset) {
+- /* DVO */
+- case mmDC_GPIO_DVODATA_A:
+- switch (mask) {
+- case BUNDLE_A_MASK:
+- *id = GPIO_ID_DVO12;
+- *en = GPIO_DVO12_A;
+- return true;
+- case BUNDLE_B_MASK:
+- *id = GPIO_ID_DVO12;
+- *en = GPIO_DVO12_B;
+- return true;
+- case DC_GPIO_DVODATA_A__DC_GPIO_DVODATA_A_MASK:
+- *id = GPIO_ID_DVO24;
+- *en = 0;
+- return true;
+- default:
+- ASSERT_CRITICAL(false);
+- return false;
+- }
+- break;
+ /* GENERIC */
+ case mmDC_GPIO_GENERIC_A:
+ *id = GPIO_ID_GENERIC;
+@@ -220,20 +199,6 @@ static bool id_to_offset(
+ bool result = true;
+
+ switch (id) {
+- case GPIO_ID_DVO12:
+- info->offset = mmDC_GPIO_DVODATA_A;
+- switch (en) {
+- case GPIO_DVO12_A:
+- info->mask = BUNDLE_A_MASK;
+- break;
+- case GPIO_DVO12_B:
+- info->mask = BUNDLE_B_MASK;
+- break;
+- default:
+- ASSERT_CRITICAL(false);
+- result = false;
+- }
+- break;
+ case GPIO_ID_DDC_DATA:
+ info->mask = DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A_MASK;
+ switch (en) {
+@@ -394,11 +359,6 @@ static bool id_to_offset(
+ result = false;
+ }
+ break;
+- case GPIO_ID_DVO24:
+- info->offset = mmDC_GPIO_DVODATA_A;
+- info->mask = DC_GPIO_DVODATA_A__DC_GPIO_DVODATA_A_MASK;
+- break;
+- case GPIO_ID_DVO1:
+ case GPIO_ID_VIP_PAD:
+ default:
+ ASSERT_CRITICAL(false);
+diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_factory_diag.c b/drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_factory_diag.c
+index 13b69e2..59503c4 100644
+--- a/drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_factory_diag.c
++++ b/drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_factory_diag.c
+@@ -42,7 +42,6 @@
+
+ /* function table */
+ static const struct hw_factory_funcs funcs = {
+- .create_dvo = NULL,
+ .create_ddc_data = NULL,
+ .create_ddc_clock = NULL,
+ .create_generic = NULL,
+@@ -54,9 +53,6 @@ static const struct hw_factory_funcs funcs = {
+
+ void dal_hw_factory_diag_fpga_init(struct hw_factory *factory)
+ {
+- factory->number_of_pins[GPIO_ID_DVO1] = 24;
+- factory->number_of_pins[GPIO_ID_DVO12] = 2;
+- factory->number_of_pins[GPIO_ID_DVO24] = 1;
+ factory->number_of_pins[GPIO_ID_DDC_DATA] = 8;
+ factory->number_of_pins[GPIO_ID_DDC_CLOCK] = 8;
+ factory->number_of_pins[GPIO_ID_GENERIC] = 7;
+@@ -65,6 +61,5 @@ void dal_hw_factory_diag_fpga_init(struct hw_factory *factory)
+ factory->number_of_pins[GPIO_ID_VIP_PAD] = 0;
+ factory->number_of_pins[GPIO_ID_SYNC] = 2;
+ factory->number_of_pins[GPIO_ID_GSL] = 4;
+-
+ factory->funcs = &funcs;
+ }
+diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/dvo.c b/drivers/gpu/drm/amd/dal/dc/gpio/dvo.c
+deleted file mode 100644
+index a237d25..0000000
+--- a/drivers/gpu/drm/amd/dal/dc/gpio/dvo.c
++++ /dev/null
+@@ -1,138 +0,0 @@
+-/*
+- * Copyright 2012-15 Advanced Micro Devices, Inc.
+- *
+- * Permission is hereby granted, free of charge, to any person obtaining a
+- * copy of this software and associated documentation files (the "Software"),
+- * to deal in the Software without restriction, including without limitation
+- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+- * and/or sell copies of the Software, and to permit persons to whom the
+- * Software is furnished to do so, subject to the following conditions:
+- *
+- * The above copyright notice and this permission notice shall be included in
+- * all copies or substantial portions of the Software.
+- *
+- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+- * OTHER DEALINGS IN THE SOFTWARE.
+- *
+- * Authors: AMD
+- *
+- */
+-
+-#include "dal_services.h"
+-
+-/*
+- * Pre-requisites: headers required by header of this unit
+- */
+-
+-#include "include/gpio_interface.h"
+-#include "include/dvo_interface.h"
+-#include "include/gpio_service_interface.h"
+-#include "hw_gpio_pin.h"
+-#include "hw_translate.h"
+-#include "hw_factory.h"
+-#include "gpio_service.h"
+-#include "gpio.h"
+-
+-/*
+- * Header of this unit
+- */
+-
+-#include "dvo.h"
+-
+-/*
+- * Post-requisites: headers required by this unit
+- */
+-
+-/*
+- * This unit
+- */
+-
+-enum gpio_result dal_dvo_open(
+- struct dvo *dvo,
+- enum gpio_mode mode)
+-{
+- return dal_gpio_open(dvo->pin, mode);
+-}
+-
+-enum gpio_result dal_dvo_get_value(
+- const struct dvo *dvo,
+- uint32_t *value)
+-{
+- return dal_gpio_get_value(dvo->pin, value);
+-}
+-
+-enum gpio_result dal_dvo_set_value(
+- const struct dvo *dvo,
+- uint32_t value)
+-{
+- return dal_gpio_set_value(dvo->pin, value);
+-}
+-
+-void dal_dvo_close(
+- struct dvo *dvo)
+-{
+- dal_gpio_close(dvo->pin);
+-}
+-
+-/*
+- * @brief
+- * Creation and destruction
+- */
+-
+-struct dvo *dal_dvo_create(
+- struct gpio_service *service,
+- enum gpio_id id,
+- uint32_t en)
+-{
+- struct dvo *dvo;
+-
+- switch (id) {
+- case GPIO_ID_DVO12:
+- if ((en < GPIO_DVO12_MIN) || (en > GPIO_DVO12_MAX)) {
+- BREAK_TO_DEBUGGER();
+- return NULL;
+- }
+- break;
+- case GPIO_ID_DVO24:
+- if ((en < GPIO_DVO24_MIN) || (en > GPIO_DVO24_MAX)) {
+- BREAK_TO_DEBUGGER();
+- return NULL;
+- }
+- break;
+- default:
+- BREAK_TO_DEBUGGER();
+- return NULL;
+- }
+-
+- dvo = dc_service_alloc(service->ctx, sizeof(struct dvo));
+-
+- if (!dvo) {
+- BREAK_TO_DEBUGGER();
+- return NULL;
+- }
+-
+- dvo->pin = NULL;
+- dvo->ctx = service->ctx;
+-
+- return dvo;
+-}
+-
+-void dal_dvo_destroy(
+- struct dvo **dvo)
+-{
+- if (!dvo || !*dvo) {
+- BREAK_TO_DEBUGGER();
+- return;
+- }
+-
+- dal_dvo_close(*dvo);
+-
+- dc_service_free((*dvo)->ctx, *dvo);
+-
+- *dvo = NULL;
+-}
+diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/dvo.h b/drivers/gpu/drm/amd/dal/dc/gpio/dvo.h
+deleted file mode 100644
+index 0d98b51..0000000
+--- a/drivers/gpu/drm/amd/dal/dc/gpio/dvo.h
++++ /dev/null
+@@ -1,42 +0,0 @@
+-/*
+- * Copyright 2012-15 Advanced Micro Devices, Inc.
+- *
+- * Permission is hereby granted, free of charge, to any person obtaining a
+- * copy of this software and associated documentation files (the "Software"),
+- * to deal in the Software without restriction, including without limitation
+- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+- * and/or sell copies of the Software, and to permit persons to whom the
+- * Software is furnished to do so, subject to the following conditions:
+- *
+- * The above copyright notice and this permission notice shall be included in
+- * all copies or substantial portions of the Software.
+- *
+- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+- * OTHER DEALINGS IN THE SOFTWARE.
+- *
+- * Authors: AMD
+- *
+- */
+-
+-#ifndef __DAL_DVO_H__
+-#define __DAL_DVO_H__
+-
+-struct dvo {
+- struct gpio *pin;
+- struct dc_context *ctx;
+-};
+-
+-struct dvo *dal_dvo_create(
+- struct gpio_service *service,
+- enum gpio_id id,
+- uint32_t en);
+-
+-void dal_dvo_destroy(
+- struct dvo **dvo);
+-
+-#endif
+diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/gpio_service.c b/drivers/gpu/drm/amd/dal/dc/gpio/gpio_service.c
+index 3a6b5f4..0920545 100644
+--- a/drivers/gpu/drm/amd/dal/dc/gpio/gpio_service.c
++++ b/drivers/gpu/drm/amd/dal/dc/gpio/gpio_service.c
+@@ -30,8 +30,6 @@
+ #include "dal_services.h"
+ #include "include/gpio_interface.h"
+ #include "include/ddc_interface.h"
+-/* TODO remove dvo */
+-#include "include/dvo_interface.h"
+ #include "include/irq_interface.h"
+ #include "include/gpio_service_interface.h"
+ #include "hw_translate.h"
+@@ -49,7 +47,6 @@
+
+ #include "hw_gpio_pin.h"
+ #include "gpio.h"
+-#include "dvo.h"
+ #include "ddc.h"
+ #include "irq.h"
+
+@@ -200,36 +197,6 @@ void dal_gpio_service_destroy_ddc(
+ dal_gpio_destroy_ddc(ddc);
+ }
+
+-struct dvo *dal_gpio_service_create_dvo(
+- struct gpio_service *service,
+- uint32_t offset,
+- uint32_t mask)
+-{
+- enum gpio_id id;
+- uint32_t en;
+-
+- if (!service->translate.funcs->offset_to_id(offset, mask, &id, &en)) {
+- BREAK_TO_DEBUGGER();
+- return NULL;
+- }
+-
+- return dal_dvo_create(service, id, en);
+-}
+-
+-struct dvo *dal_gpio_service_create_dvo_ex(
+- struct gpio_service *service,
+- enum gpio_id id,
+- uint32_t en)
+-{
+- return dal_dvo_create(service, id, en);
+-}
+-
+-void dal_gpio_service_destroy_dvo(
+- struct dvo **dvo)
+-{
+- dal_dvo_destroy(dvo);
+-}
+-
+ struct irq *dal_gpio_service_create_irq(
+ struct gpio_service *service,
+ uint32_t offset,
+@@ -304,29 +271,6 @@ static bool is_pin_busy(
+ return 0 != (*slot & (1 << (en % bits_per_uint)));
+ }
+
+-static bool is_some_pin_busy(
+- const struct gpio_service *service,
+- enum gpio_id id)
+-{
+- const uint32_t bits_per_uint = sizeof(uint32_t) << 3;
+-
+- uint32_t index_of_uint = 0;
+-
+- uint32_t number_of_uints =
+- service->factory.number_of_pins[id];
+-
+- number_of_uints = (number_of_uints + bits_per_uint - 1) / bits_per_uint;
+-
+- while (index_of_uint < number_of_uints) {
+- if (service->busyness[id][index_of_uint])
+- return true;
+-
+- ++index_of_uint;
+- };
+-
+- return false;
+-}
+-
+ static void set_pin_busy(
+ struct gpio_service *service,
+ enum gpio_id id,
+@@ -370,38 +314,6 @@ enum gpio_result dal_gpio_service_open(
+ }
+
+ switch (id) {
+- case GPIO_ID_DVO1:
+- /* [anaumov] not implemented, commented with "to do" */
+- ASSERT_CRITICAL(false);
+- return GPIO_RESULT_NON_SPECIFIC_ERROR;
+- case GPIO_ID_DVO12:
+- if (!service->busyness[GPIO_ID_DVO24]) {
+- ASSERT_CRITICAL(false);
+- return GPIO_RESULT_OPEN_FAILED;
+- }
+-
+- if (is_some_pin_busy(service, GPIO_ID_DVO24)) {
+- ASSERT_CRITICAL(false);
+- return GPIO_RESULT_DEVICE_BUSY;
+- }
+-
+- pin = service->factory.funcs->create_dvo(
+- service->ctx, id, en);
+- break;
+- case GPIO_ID_DVO24:
+- if (!service->busyness[GPIO_ID_DVO12]) {
+- ASSERT_CRITICAL(false);
+- return GPIO_RESULT_OPEN_FAILED;
+- }
+-
+- if (is_some_pin_busy(service, GPIO_ID_DVO12)) {
+- ASSERT_CRITICAL(false);
+- return GPIO_RESULT_DEVICE_BUSY;
+- }
+-
+- pin = service->factory.funcs->create_dvo(
+- service->ctx, id, en);
+- break;
+ case GPIO_ID_DDC_DATA:
+ pin = service->factory.funcs->create_ddc_data(
+ service->ctx, id, en);
+diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/hw_dvo.c b/drivers/gpu/drm/amd/dal/dc/gpio/hw_dvo.c
+deleted file mode 100644
+index a5a07f0..0000000
+--- a/drivers/gpu/drm/amd/dal/dc/gpio/hw_dvo.c
++++ /dev/null
+@@ -1,318 +0,0 @@
+-/*
+- * Copyright 2012-15 Advanced Micro Devices, Inc.
+- *
+- * Permission is hereby granted, free of charge, to any person obtaining a
+- * copy of this software and associated documentation files (the "Software"),
+- * to deal in the Software without restriction, including without limitation
+- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+- * and/or sell copies of the Software, and to permit persons to whom the
+- * Software is furnished to do so, subject to the following conditions:
+- *
+- * The above copyright notice and this permission notice shall be included in
+- * all copies or substantial portions of the Software.
+- *
+- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+- * OTHER DEALINGS IN THE SOFTWARE.
+- *
+- * Authors: AMD
+- *
+- */
+-
+-#include "dal_services.h"
+-
+-/*
+- * Pre-requisites: headers required by header of this unit
+- */
+-
+-#include "include/gpio_types.h"
+-#include "hw_gpio_pin.h"
+-
+-/*
+- * Header of this unit
+- */
+-
+-#include "hw_dvo.h"
+-
+-/*
+- * Post-requisites: headers required by this unit
+- */
+-
+-/*
+- * This unit
+- */
+-
+-#define FROM_HW_GPIO_PIN(ptr) \
+- container_of((ptr), struct hw_dvo, base)
+-
+-static void store_dvo_registers(
+- struct hw_dvo *pin)
+-{
+- pin->store.dvo_mask = dal_read_reg(
+- pin->base.ctx, pin->addr.DC_GPIO_DVODATA_MASK);
+- pin->store.dvo_en = dal_read_reg(
+- pin->base.ctx, pin->addr.DC_GPIO_DVODATA_EN);
+- pin->store.dvo_data_a = dal_read_reg(
+- pin->base.ctx, pin->addr.DC_GPIO_DVODATA_A);
+-}
+-
+-static void restore_dvo_registers(
+- struct hw_dvo *pin)
+-{
+- {
+- const uint32_t addr = pin->addr.DC_GPIO_DVODATA_MASK;
+-
+- uint32_t data = dal_read_reg(pin->base.ctx, addr);
+-
+- data &= ~pin->dvo_mask;
+- data |= pin->store.dvo_mask & pin->dvo_mask;
+-
+- dal_write_reg(pin->base.ctx, addr, data);
+- }
+-
+- {
+- const uint32_t addr = pin->addr.DC_GPIO_DVODATA_EN;
+-
+- uint32_t data = dal_read_reg(pin->base.ctx, addr);
+-
+- data &= ~pin->dvo_mask;
+- data |= pin->store.dvo_en & pin->dvo_mask;
+-
+- dal_write_reg(pin->base.ctx, addr, data);
+- }
+-
+- {
+- const uint32_t addr = pin->addr.DC_GPIO_DVODATA_A;
+-
+- uint32_t data = dal_read_reg(pin->base.ctx, addr);
+-
+- data &= ~pin->dvo_mask;
+- data |= pin->store.dvo_data_a & pin->dvo_mask;
+-
+- dal_write_reg(pin->base.ctx, addr, data);
+- }
+-}
+-
+-static void program_dvo(
+- struct hw_dvo *pin,
+- bool output)
+-{
+- /* Turn on Mask bits for the requested channel,
+- * this will enable the channel for software control. */
+- {
+- const uint32_t addr = pin->addr.DC_GPIO_DVODATA_MASK;
+-
+- uint32_t mask = dal_read_reg(pin->base.ctx, addr);
+-
+- uint32_t data = pin->dvo_mask | mask;
+-
+- dal_write_reg(pin->base.ctx, addr, data);
+- }
+-
+- /* Turn off/on the Enable bits on the requested channel,
+- * this will set it to Input/Output mode. */
+- {
+- const uint32_t addr = pin->addr.DC_GPIO_DVODATA_EN;
+-
+- uint32_t enable = dal_read_reg(pin->base.ctx, addr);
+-
+- uint32_t data = output ?
+- (pin->dvo_mask | enable) :
+- (~pin->dvo_mask & enable);
+-
+- dal_write_reg(pin->base.ctx, addr, data);
+- }
+-}
+-
+-static void program_dvo_strength(
+- struct hw_dvo *pin)
+-{
+- const uint32_t addr = pin->addr.DVO_STRENGTH_CONTROL;
+-
+- uint32_t data = dal_read_reg(pin->base.ctx, addr);
+-
+- data &= ~pin->dvo_strength_mask;
+- data |= pin->dvo_strength & pin->dvo_strength_mask;
+-
+- dal_write_reg(pin->base.ctx, addr, data);
+-}
+-
+-static void disable_on_chip_terminators(
+- struct hw_dvo *pin)
+-{
+- const uint32_t addr = pin->addr.D1CRTC_MVP_CONTROL1;
+-
+- uint32_t data = dal_read_reg(pin->base.ctx, addr);
+-
+- pin->store.mvp_terminator_state = (data & pin->mvp_termination_mask);
+-
+- data &= ~pin->mvp_termination_mask;
+-
+- dal_write_reg(pin->base.ctx, addr, data);
+-}
+-
+-static void restore_on_chip_terminators(
+- struct hw_dvo *pin)
+-{
+- const uint32_t addr = pin->addr.D1CRTC_MVP_CONTROL1;
+-
+- uint32_t data = dal_read_reg(pin->base.ctx, addr);
+-
+- data &= ~pin->mvp_termination_mask;
+-
+- if (pin->store.mvp_terminator_state)
+- data |= pin->mvp_termination_mask;
+-
+- dal_write_reg(pin->base.ctx, addr, data);
+-}
+-
+-bool dal_hw_dvo_open(
+- struct hw_gpio_pin *ptr,
+- enum gpio_mode mode,
+- void *options)
+-{
+- struct hw_dvo *pin = FROM_HW_GPIO_PIN(ptr);
+-
+- store_dvo_registers(pin);
+-
+- ptr->mode = mode;
+-
+- switch (mode) {
+- case GPIO_MODE_INPUT:
+- program_dvo_strength(pin);
+- disable_on_chip_terminators(pin);
+- program_dvo(pin, false);
+-
+- ptr->opened = true;
+- break;
+- case GPIO_MODE_OUTPUT:
+- program_dvo_strength(pin);
+- disable_on_chip_terminators(pin);
+- program_dvo(pin, true);
+-
+- ptr->opened = true;
+- break;
+- default:
+- /* unsupported mode */
+- BREAK_TO_DEBUGGER();
+-
+- ptr->opened = false;
+- }
+-
+- return ptr->opened;
+-}
+-
+-enum gpio_result dal_hw_dvo_get_value(
+- const struct hw_gpio_pin *ptr,
+- uint32_t *value)
+-{
+- const struct hw_dvo *pin = FROM_HW_GPIO_PIN(ptr);
+-
+- if (ptr->mode != GPIO_MODE_INPUT)
+- return GPIO_RESULT_NON_SPECIFIC_ERROR;
+-
+- *value = dal_read_reg(ptr->ctx, pin->addr.DC_GPIO_DVODATA_Y);
+-
+- *value &= pin->dvo_mask;
+- *value >>= pin->dvo_shift;
+-
+- return GPIO_RESULT_OK;
+-}
+-
+-enum gpio_result dal_hw_dvo_set_value(
+- const struct hw_gpio_pin *ptr,
+- uint32_t value)
+-{
+- const struct hw_dvo *pin = FROM_HW_GPIO_PIN(ptr);
+-
+- uint32_t masked_value;
+-
+- if (ptr->mode != GPIO_MODE_OUTPUT) {
+- BREAK_TO_DEBUGGER();
+- return GPIO_RESULT_NON_SPECIFIC_ERROR;
+- }
+-
+- /* Ensure there is no overflow of the value written.
+- * Value cannot be more than 12 bits for a 12-bit channel. */
+-
+- masked_value = value << pin->dvo_shift;
+-
+- if (masked_value != (masked_value & pin->dvo_mask)) {
+- BREAK_TO_DEBUGGER();
+- return GPIO_RESULT_INVALID_DATA;
+- }
+-
+- masked_value &= pin->dvo_mask;
+-
+- /* read the DataA register
+- * mask off the Bundle that we want to write to
+- * or the data into the register */
+- {
+- const uint32_t addr = pin->addr.DC_GPIO_DVODATA_A;
+-
+- uint32_t data = dal_read_reg(ptr->ctx, addr);
+-
+- data &= ~pin->dvo_mask;
+- data |= masked_value;
+-
+- dal_write_reg(ptr->ctx, addr, data);
+- }
+-
+- return GPIO_RESULT_OK;
+-}
+-
+-void dal_hw_dvo_close(
+- struct hw_gpio_pin *ptr)
+-{
+- struct hw_dvo *pin = FROM_HW_GPIO_PIN(ptr);
+-
+- restore_dvo_registers(pin);
+- restore_on_chip_terminators(pin);
+-
+- ptr->mode = GPIO_MODE_UNKNOWN;
+-
+- ptr->opened = false;
+-}
+-
+-bool dal_hw_dvo_construct(
+- struct hw_dvo *pin,
+- enum gpio_id id,
+- uint32_t en,
+- struct dc_context *ctx)
+-{
+- struct hw_gpio_pin *base = &pin->base;
+-
+- if (!dal_hw_gpio_pin_construct(base, id, en, ctx))
+- return false;
+-
+- pin->addr.DC_GPIO_DVODATA_MASK = 0;
+- pin->addr.DC_GPIO_DVODATA_EN = 0;
+- pin->addr.DC_GPIO_DVODATA_A = 0;
+- pin->addr.DC_GPIO_DVODATA_Y = 0;
+- pin->addr.DVO_STRENGTH_CONTROL = 0;
+- pin->addr.D1CRTC_MVP_CONTROL1 = 0;
+-
+- pin->dvo_mask = 0;
+- pin->dvo_shift = 0;
+- pin->dvo_strength_mask = 0;
+- pin->mvp_termination_mask = 0;
+-
+- pin->dvo_strength = 0;
+-
+- pin->store.dvo_mask = 0;
+- pin->store.dvo_en = 0;
+- pin->store.dvo_data_a = 0;
+- pin->store.mvp_terminator_state = false;
+-
+- return true;
+-}
+-
+-void dal_hw_dvo_destruct(
+- struct hw_dvo *pin)
+-{
+- dal_hw_gpio_pin_destruct(&pin->base);
+-}
+diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/hw_dvo.h b/drivers/gpu/drm/amd/dal/dc/gpio/hw_dvo.h
+deleted file mode 100644
+index 5a120c2..0000000
+--- a/drivers/gpu/drm/amd/dal/dc/gpio/hw_dvo.h
++++ /dev/null
+@@ -1,89 +0,0 @@
+-/*
+- * Copyright 2012-15 Advanced Micro Devices, Inc.
+- *
+- * Permission is hereby granted, free of charge, to any person obtaining a
+- * copy of this software and associated documentation files (the "Software"),
+- * to deal in the Software without restriction, including without limitation
+- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+- * and/or sell copies of the Software, and to permit persons to whom the
+- * Software is furnished to do so, subject to the following conditions:
+- *
+- * The above copyright notice and this permission notice shall be included in
+- * all copies or substantial portions of the Software.
+- *
+- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+- * OTHER DEALINGS IN THE SOFTWARE.
+- *
+- * Authors: AMD
+- *
+- */
+-
+-#ifndef __DAL_HW_DVO_H__
+-#define __DAL_HW_DVO_H__
+-
+-#define BUNDLE_A_SHIFT 12L
+-#define BUNDLE_B_SHIFT 0L
+-
+-struct hw_dvo {
+- struct hw_gpio_pin base;
+- /* Register indices are represented by member variables,
+- * are to be filled in by derived classes.
+- * These members permit the use of common code
+- * for programming registers where the sequence is the same
+- * but the register sets are different */
+- struct {
+- uint32_t DC_GPIO_DVODATA_MASK;
+- uint32_t DC_GPIO_DVODATA_EN;
+- uint32_t DC_GPIO_DVODATA_A;
+- uint32_t DC_GPIO_DVODATA_Y;
+- uint32_t DVO_STRENGTH_CONTROL;
+- uint32_t D1CRTC_MVP_CONTROL1;
+- } addr;
+-
+- /* Mask and shift differentiates between Bundle A and Bundle B */
+- uint32_t dvo_mask;
+- uint32_t dvo_shift;
+- uint32_t dvo_strength_mask;
+- uint32_t mvp_termination_mask;
+-
+- uint32_t dvo_strength;
+-
+- struct {
+- uint32_t dvo_mask;
+- uint32_t dvo_en;
+- uint32_t dvo_data_a;
+- bool mvp_terminator_state;
+- } store;
+-};
+-
+-bool dal_hw_dvo_construct(
+- struct hw_dvo *pin,
+- enum gpio_id id,
+- uint32_t en,
+- struct dc_context *ctx);
+-
+-void dal_hw_dvo_destruct(
+- struct hw_dvo *pin);
+-
+-bool dal_hw_dvo_open(
+- struct hw_gpio_pin *ptr,
+- enum gpio_mode mode,
+- void *options);
+-
+-enum gpio_result dal_hw_dvo_get_value(
+- const struct hw_gpio_pin *ptr,
+- uint32_t *value);
+-
+-enum gpio_result dal_hw_dvo_set_value(
+- const struct hw_gpio_pin *ptr,
+- uint32_t value);
+-
+-void dal_hw_dvo_close(
+- struct hw_gpio_pin *ptr);
+-
+-#endif
+diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/hw_factory.h b/drivers/gpu/drm/amd/dal/dc/gpio/hw_factory.h
+index 7fef3fa..1fa8b6d 100644
+--- a/drivers/gpu/drm/amd/dal/dc/gpio/hw_factory.h
++++ b/drivers/gpu/drm/amd/dal/dc/gpio/hw_factory.h
+@@ -32,10 +32,6 @@ struct hw_factory {
+ uint32_t number_of_pins[GPIO_ID_COUNT];
+
+ const struct hw_factory_funcs {
+- struct hw_gpio_pin *(*create_dvo)(
+- struct dc_context *ctx,
+- enum gpio_id id,
+- uint32_t en);
+ struct hw_gpio_pin *(*create_ddc_data)(
+ struct dc_context *ctx,
+ enum gpio_id id,
+diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c
+index a2a615a..6cf3955 100644
+--- a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c
++++ b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c
+@@ -41,17 +41,16 @@
+ container_of(base, struct display_clock_dce110, disp_clk_base)
+
+ static struct state_dependent_clocks max_clks_by_state[] = {
+-/*( dvo not exist in KV)*/
+ /*ClocksStateInvalid - should not be used*/
+-{ .display_clk_khz = 0, .pixel_clk_khz = 0, .dvo_clk_khz = 0 },
++{ .display_clk_khz = 0, .pixel_clk_khz = 0 },
+ /*ClocksStateUltraLow - currently by HW design team not supposed to be used*/
+-{ .display_clk_khz = 352000, .pixel_clk_khz = 330000, .dvo_clk_khz = 0 },
++{ .display_clk_khz = 352000, .pixel_clk_khz = 330000 },
+ /*ClocksStateLow*/
+-{ .display_clk_khz = 352000, .pixel_clk_khz = 330000, .dvo_clk_khz = 0 },
++{ .display_clk_khz = 352000, .pixel_clk_khz = 330000 },
+ /*ClocksStateNominal*/
+-{ .display_clk_khz = 467000, .pixel_clk_khz = 400000, .dvo_clk_khz = 0 },
++{ .display_clk_khz = 467000, .pixel_clk_khz = 400000 },
+ /*ClocksStatePerformance*/
+-{ .display_clk_khz = 643000, .pixel_clk_khz = 400000, .dvo_clk_khz = 0 } };
++{ .display_clk_khz = 643000, .pixel_clk_khz = 400000 } };
+
+
+ /* Starting point for each divider range.*/
+diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/pll_clock_source_dce110.c b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/pll_clock_source_dce110.c
+index cce9b0b..019ea02 100644
+--- a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/pll_clock_source_dce110.c
++++ b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/pll_clock_source_dce110.c
+@@ -279,7 +279,6 @@ static bool program_pix_clk(
+ pll_settings->pix_clk_post_divider;
+ bp_pc_params.encoder_object_id = pix_clk_params->encoder_object_id;
+ bp_pc_params.signal_type = pix_clk_params->signal_type;
+- bp_pc_params.dvo_config = pix_clk_params->dvo_cfg;
+ bp_pc_params.flags.SET_EXTERNAL_REF_DIV_SRC =
+ pll_settings->use_external_clk;
+
+@@ -392,7 +391,8 @@ static uint32_t get_pix_clk_dividers(
+ /* Check if reference clock is external (not pcie/xtalin)
+ * HW Dce80 spec:
+ * 00 - PCIE_REFCLK, 01 - XTALIN, 02 - GENERICA, 03 - GENERICB
+- * 04 - HSYNCA, 05 - GENLK_CLK, 06 - PCIE_REFCLK, 07 - DVOCLK0 */
++ * 04 - HSYNCA, 05 - GENLK_CLK, 06 - PCIE_REFCLK
++ */
+ addr = pll_cs_110->pxpll_cntl;
+ value = dal_read_reg(cs->ctx, addr);
+ field = get_reg_field_value(value, PLL_CNTL, PLL_REF_DIV_SRC);
+diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/ext_clock_source.c b/drivers/gpu/drm/amd/dal/dc/gpu/ext_clock_source.c
+index 3a26312..6cd0b3f 100644
+--- a/drivers/gpu/drm/amd/dal/dc/gpu/ext_clock_source.c
++++ b/drivers/gpu/drm/amd/dal/dc/gpu/ext_clock_source.c
+@@ -70,7 +70,6 @@ bool dal_ext_clock_source_program_pix_clk(
+ pix_clk_params->requested_pix_clk;
+ bp_pix_clk_params.encoder_object_id = pix_clk_params->encoder_object_id;
+ bp_pix_clk_params.signal_type = pix_clk_params->signal_type;
+- bp_pix_clk_params.dvo_config = pix_clk_params->dvo_cfg;
+
+ if (clk_src->bios_parser->funcs->set_pixel_clock(
+ clk_src->bios_parser,
+diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/pll_clock_source.c b/drivers/gpu/drm/amd/dal/dc/gpu/pll_clock_source.c
+index 3049842..aa5a667 100644
+--- a/drivers/gpu/drm/amd/dal/dc/gpu/pll_clock_source.c
++++ b/drivers/gpu/drm/amd/dal/dc/gpu/pll_clock_source.c
+@@ -97,9 +97,6 @@ bool dal_pll_clock_source_adjust_pix_clk(
+ bp_adjust_pixel_clock_params.
+ encoder_object_id = pix_clk_params->encoder_object_id;
+ bp_adjust_pixel_clock_params.signal_type = pix_clk_params->signal_type;
+- bp_adjust_pixel_clock_params.dvo_config = pix_clk_params->dvo_cfg;
+- bp_adjust_pixel_clock_params.
+- display_pll_config = pix_clk_params->disp_pll_cfg;
+ bp_adjust_pixel_clock_params.
+ ss_enable = pix_clk_params->flags.ENABLE_SS;
+ bp_result = pll_clk_src->base.bios_parser->funcs->adjust_pixel_clock(
+diff --git a/drivers/gpu/drm/amd/dal/include/audio_types.h b/drivers/gpu/drm/amd/dal/include/audio_types.h
+index e9c2ab3..204c5d8 100644
+--- a/drivers/gpu/drm/amd/dal/include/audio_types.h
++++ b/drivers/gpu/drm/amd/dal/include/audio_types.h
+@@ -264,7 +264,6 @@ struct audio_feature_support {
+ uint32_t ENGINE_DIGE:1;
+ uint32_t ENGINE_DIGF:1;
+ uint32_t ENGINE_DIGG:1;
+- uint32_t ENGINE_DVO:1;
+ uint32_t MULTISTREAM_AUDIO:1;
+ };
+
+diff --git a/drivers/gpu/drm/amd/dal/include/bios_parser_types.h b/drivers/gpu/drm/amd/dal/include/bios_parser_types.h
+index 7b93997..b4b93c6 100644
+--- a/drivers/gpu/drm/amd/dal/include/bios_parser_types.h
++++ b/drivers/gpu/drm/amd/dal/include/bios_parser_types.h
+@@ -144,24 +144,6 @@ struct bp_transmitter_control {
+ bool single_pll_mode;
+ };
+
+-enum dvo_encoder_memory_rate {
+- DVO_ENCODER_MEMORY_RATE_DDR,
+- DVO_ENCODER_MEMORY_RATE_SDR
+-};
+-
+-enum dvo_encoder_interface_width {
+- DVO_ENCODER_INTERFACE_WIDTH_LOW12BIT,
+- DVO_ENCODER_INTERFACE_WIDTH_HIGH12BIT,
+- DVO_ENCODER_INTERFACE_WIDTH_FULL24BIT
+-};
+-
+-struct bp_dvo_encoder_control {
+- enum bp_encoder_control_action action;
+- enum dvo_encoder_memory_rate memory_rate;
+- enum dvo_encoder_interface_width interface_width;
+- uint32_t pixel_clock; /* in KHz */
+-};
+-
+ struct bp_blank_crtc_parameters {
+ enum controller_id controller_id;
+ uint32_t black_color_rcr;
+@@ -207,22 +189,12 @@ struct bp_hw_crtc_overscan_parameters {
+ struct bp_adjust_pixel_clock_parameters {
+ /* Input: Signal Type - to be converted to Encoder mode */
+ enum signal_type signal_type;
+- /* Input: required by V3, display pll configure parameter defined as
+- * following DISPPLL_CONFIG_XXXX */
+- enum disp_pll_config display_pll_config;
+ /* Input: Encoder object id */
+ struct graphics_object_id encoder_object_id;
+ /* Input: Pixel Clock (requested Pixel clock based on Video timing
+ * standard used) in KHz
+ */
+ uint32_t pixel_clock;
+- union {
+- /* Input: If DVO, need passing link rate and output 12bit low or
+- * 24bit to VBIOS Exec table */
+- uint32_t dvo_config;
+- /* Input: If non DVO, not defined yet */
+- uint32_t non_dvo_undefined;
+- };
+ /* Output: Adjusted Pixel Clock (after VBIOS exec table) in KHz */
+ uint32_t adjusted_pixel_clock;
+ /* Output: If non-zero, this refDiv value should be used to calculate
+@@ -252,9 +224,6 @@ struct bp_pixel_clock_parameters {
+ /* Calculated Pixel Clock Post divider of Display PLL */
+ uint32_t pixel_clock_post_divider;
+ struct graphics_object_id encoder_object_id; /* Encoder object id */
+- /* If DVO, need passing link rate and output 12bit low or
+- * 24bit to VBIOS Exec table */
+- uint32_t dvo_config;
+ /* VBIOS returns a fixed display clock when DFS-bypass feature
+ * is enabled (KHz) */
+ uint32_t dfs_bypass_display_clock;
+diff --git a/drivers/gpu/drm/amd/dal/include/clock_source_types.h b/drivers/gpu/drm/amd/dal/include/clock_source_types.h
+index 3883216..4c323a9 100644
+--- a/drivers/gpu/drm/amd/dal/include/clock_source_types.h
++++ b/drivers/gpu/drm/amd/dal/include/clock_source_types.h
+@@ -86,11 +86,6 @@ struct pixel_clk_params {
+ struct csdp_ref_clk_ds_params de_spread_params;
+ /*> de-spread info, relevant only for on-the-fly tune-up pixel rate*/
+
+- uint32_t dvo_cfg;
+-/*> If DVO, need passing link rate
+- * and output 12bit low or 24bit to VBIOS Exec table*/
+-
+- enum disp_pll_config disp_pll_cfg;
+ struct pixel_clk_flags flags;
+ };
+
+diff --git a/drivers/gpu/drm/amd/dal/include/display_clock_interface.h b/drivers/gpu/drm/amd/dal/include/display_clock_interface.h
+index f3a1cee..009b583 100644
+--- a/drivers/gpu/drm/amd/dal/include/display_clock_interface.h
++++ b/drivers/gpu/drm/amd/dal/include/display_clock_interface.h
+@@ -123,7 +123,6 @@ enum clocks_state {
+ struct state_dependent_clocks {
+ uint32_t display_clk_khz;
+ uint32_t pixel_clk_khz;
+- uint32_t dvo_clk_khz;
+ };
+
+ struct display_clock_state {
+diff --git a/drivers/gpu/drm/amd/dal/include/dvo_interface.h b/drivers/gpu/drm/amd/dal/include/dvo_interface.h
+deleted file mode 100644
+index 58d2c6f..0000000
+--- a/drivers/gpu/drm/amd/dal/include/dvo_interface.h
++++ /dev/null
+@@ -1,48 +0,0 @@
+-/*
+- * Copyright 2012-15 Advanced Micro Devices, Inc.
+- *
+- * Permission is hereby granted, free of charge, to any person obtaining a
+- * copy of this software and associated documentation files (the "Software"),
+- * to deal in the Software without restriction, including without limitation
+- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+- * and/or sell copies of the Software, and to permit persons to whom the
+- * Software is furnished to do so, subject to the following conditions:
+- *
+- * The above copyright notice and this permission notice shall be included in
+- * all copies or substantial portions of the Software.
+- *
+- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+- * OTHER DEALINGS IN THE SOFTWARE.
+- *
+- * Authors: AMD
+- *
+- */
+-
+-#ifndef __DAL_DVO_INTERFACE_H__
+-#define __DAL_DVO_INTERFACE_H__
+-
+-#include "gpio_types.h"
+-
+-struct dvo;
+-
+-enum gpio_result dal_dvo_open(
+- struct dvo *dvo,
+- enum gpio_mode mode);
+-
+-enum gpio_result dal_dvo_get_value(
+- const struct dvo *dvo,
+- uint32_t *value);
+-
+-enum gpio_result dal_dvo_set_value(
+- const struct dvo *dvo,
+- uint32_t value);
+-
+-void dal_dvo_close(
+- struct dvo *dvo);
+-
+-#endif
+diff --git a/drivers/gpu/drm/amd/dal/include/gpio_service_interface.h b/drivers/gpu/drm/amd/dal/include/gpio_service_interface.h
+index b4f30dd..3f1b923 100644
+--- a/drivers/gpu/drm/amd/dal/include/gpio_service_interface.h
++++ b/drivers/gpu/drm/amd/dal/include/gpio_service_interface.h
+@@ -28,7 +28,6 @@
+
+ #include "gpio_types.h"
+ #include "gpio_interface.h"
+-#include "dvo_interface.h"
+ #include "ddc_interface.h"
+ #include "irq_interface.h"
+
+@@ -63,19 +62,6 @@ struct ddc *dal_gpio_service_create_ddc(
+ void dal_gpio_service_destroy_ddc(
+ struct ddc **ddc);
+
+-struct dvo *dal_gpio_service_create_dvo(
+- struct gpio_service *service,
+- uint32_t offset,
+- uint32_t mask);
+-
+-struct dvo *dal_gpio_service_create_dvo_ex(
+- struct gpio_service *service,
+- enum gpio_id id,
+- uint32_t en);
+-
+-void dal_gpio_service_destroy_dvo(
+- struct dvo **ptr);
+-
+ struct irq *dal_gpio_service_create_irq(
+ struct gpio_service *service,
+ uint32_t offset,
+diff --git a/drivers/gpu/drm/amd/dal/include/gpio_types.h b/drivers/gpu/drm/amd/dal/include/gpio_types.h
+index d616d62..6d3214b 100644
+--- a/drivers/gpu/drm/amd/dal/include/gpio_types.h
++++ b/drivers/gpu/drm/amd/dal/include/gpio_types.h
+@@ -57,9 +57,6 @@ enum gpio_result {
+ */
+ enum gpio_id {
+ GPIO_ID_UNKNOWN = (-1),
+- GPIO_ID_DVO1,
+- GPIO_ID_DVO12,
+- GPIO_ID_DVO24,
+ GPIO_ID_DDC_DATA,
+ GPIO_ID_DDC_CLOCK,
+ GPIO_ID_GENERIC,
+@@ -69,7 +66,7 @@ enum gpio_id {
+ GPIO_ID_SYNC,
+ GPIO_ID_GSL, /* global swap lock */
+ GPIO_ID_COUNT,
+- GPIO_ID_MIN = GPIO_ID_DVO1,
++ GPIO_ID_MIN = GPIO_ID_DDC_DATA,
+ GPIO_ID_MAX = GPIO_ID_GSL
+ };
+
+@@ -94,54 +91,6 @@ enum gpio_pin_output_state {
+ GPIO_PIN_OUTPUT_STATE_DEFAULT = GPIO_PIN_OUTPUT_STATE_ACTIVE_LOW
+ };
+
+-enum gpio_dvo1 {
+- GPIO_DVO1_UNKNOWN = (-1),
+- GPIO_DVO1_0,
+- GPIO_DVO1_1,
+- GPIO_DVO1_2,
+- GPIO_DVO1_3,
+- GPIO_DVO1_4,
+- GPIO_DVO1_5,
+- GPIO_DVO1_6,
+- GPIO_DVO1_7,
+- GPIO_DVO1_8,
+- GPIO_DVO1_9,
+- GPIO_DVO1_10,
+- GPIO_DVO1_11,
+- GPIO_DVO1_12,
+- GPIO_DVO1_13,
+- GPIO_DVO1_14,
+- GPIO_DVO1_15,
+- GPIO_DVO1_16,
+- GPIO_DVO1_17,
+- GPIO_DVO1_18,
+- GPIO_DVO1_19,
+- GPIO_DVO1_20,
+- GPIO_DVO1_21,
+- GPIO_DVO1_22,
+- GPIO_DVO1_23,
+- GPIO_DVO1_COUNT,
+- GPIO_DVO1_MIN = GPIO_DVO1_0,
+- GPIO_DVO1_MAX = GPIO_DVO1_23
+-};
+-
+-enum gpio_dvo12 {
+- GPIO_DVO12_UNKNOWN = (-1),
+- GPIO_DVO12_A,
+- GPIO_DVO12_B,
+- GPIO_DVO12_COUNT,
+- GPIO_DVO12_MIN = GPIO_DVO12_A,
+- GPIO_DVO12_MAX = GPIO_DVO12_B
+-};
+-
+-enum gpio_dvo24 {
+- GPIO_DVO24_UNKNOWN = (-1),
+- GPIO_DVO24_A,
+- GPIO_DVO24_COUNT,
+- GPIO_DVO24_MIN = GPIO_DVO24_A,
+- GPIO_DVO24_MAX = GPIO_DVO24_A
+-};
+-
+ enum gpio_generic {
+ GPIO_GENERIC_UNKNOWN = (-1),
+ GPIO_GENERIC_A,
+@@ -303,7 +252,6 @@ enum gpio_signal_source {
+ GPIO_SIGNAL_SOURCE_DACB_HSYNC,
+ GPIO_SIGNAL_SOURCE_DACA_VSYNC,
+ GPIO_SIGNAL_SOURCE_DACB_VSYNC,
+- GPIO_SIGNAL_SOURCE_DVO_STEREO_SYNC
+ };
+
+ enum gpio_stereo_source {
+diff --git a/drivers/gpu/drm/amd/dal/include/grph_object_ctrl_defs.h b/drivers/gpu/drm/amd/dal/include/grph_object_ctrl_defs.h
+index d804109..c6de837 100644
+--- a/drivers/gpu/drm/amd/dal/include/grph_object_ctrl_defs.h
++++ b/drivers/gpu/drm/amd/dal/include/grph_object_ctrl_defs.h
+@@ -86,13 +86,6 @@ enum cv_standard {
+ CV_STANDARD_SD_SECAM_L1 /* SECAM L1 output 4009 */
+ };
+
+-enum disp_pll_config {
+- DISP_PLL_CONFIG_UNKNOWN = 0,
+- DISP_PLL_CONFIG_DVO_DDR_MODE_LOW_12BIT,
+- DISP_PLL_CONFIG_DVO_DDR_MODE_UPPER_12BIT,
+- DISP_PLL_CONFIG_DVO_DDR_MODE_24BIT
+-};
+-
+ enum display_output_bit_depth {
+ PANEL_UNDEFINE = 0,
+ PANEL_6BIT_COLOR = 1,
+diff --git a/drivers/gpu/drm/amd/dal/include/grph_object_id.h b/drivers/gpu/drm/amd/dal/include/grph_object_id.h
+index 2f73797..4938435 100644
+--- a/drivers/gpu/drm/amd/dal/include/grph_object_id.h
++++ b/drivers/gpu/drm/amd/dal/include/grph_object_id.h
+@@ -124,35 +124,18 @@ enum encoder_id {
+ ENCODER_ID_INTERNAL_TMDS2,
+ ENCODER_ID_INTERNAL_DAC1,
+ ENCODER_ID_INTERNAL_DAC2, /* TV/CV DAC */
+- ENCODER_ID_INTERNAL_SDVOA,
+- ENCODER_ID_INTERNAL_SDVOB,
+
+ /* External Third Party Encoders */
+- ENCODER_ID_EXTERNAL_SI170B,
+- ENCODER_ID_EXTERNAL_CH7303,
+- ENCODER_ID_EXTERNAL_CH7301, /* 10 in decimal */
+- ENCODER_ID_INTERNAL_DVO1, /* Belongs to Radeon Display Hardware */
+- ENCODER_ID_EXTERNAL_SDVOA,
+- ENCODER_ID_EXTERNAL_SDVOB,
+- ENCODER_ID_EXTERNAL_TITFP513,
+ ENCODER_ID_INTERNAL_LVTM1, /* not used for Radeon */
+- ENCODER_ID_EXTERNAL_VT1623,
+- ENCODER_ID_EXTERNAL_SI1930, /* HDMI */
+ ENCODER_ID_INTERNAL_HDMI,
+
+ /* Kaledisope (KLDSCP) Class Display Hardware */
+ ENCODER_ID_INTERNAL_KLDSCP_TMDS1,
+- ENCODER_ID_INTERNAL_KLDSCP_DVO1,
+ ENCODER_ID_INTERNAL_KLDSCP_DAC1,
+ ENCODER_ID_INTERNAL_KLDSCP_DAC2, /* Shared with CV/TV and CRT */
+ /* External TMDS (dual link) */
+- ENCODER_ID_EXTERNAL_SI178,
+ ENCODER_ID_EXTERNAL_MVPU_FPGA, /* MVPU FPGA chip */
+ ENCODER_ID_INTERNAL_DDI,
+- ENCODER_ID_EXTERNAL_VT1625,
+- ENCODER_ID_EXTERNAL_SI1932,
+- ENCODER_ID_EXTERNAL_AN9801, /* External Display Port */
+- ENCODER_ID_EXTERNAL_DP501, /* External Display Port */
+ ENCODER_ID_INTERNAL_UNIPHY,
+ ENCODER_ID_INTERNAL_KLDSCP_LVTMA,
+ ENCODER_ID_INTERNAL_UNIPHY1,
+@@ -163,8 +146,6 @@ enum encoder_id {
+ ENCODER_ID_INTERNAL_WIRELESS, /* Internal wireless display encoder */
+ ENCODER_ID_INTERNAL_UNIPHY3,
+ ENCODER_ID_INTERNAL_VIRTUAL,
+-
+- ENCODER_ID_EXTERNAL_GENERIC_DVO = 0xFF
+ };
+
+
+@@ -206,7 +187,6 @@ enum engine_id {
+ ENGINE_ID_DIGE,
+ ENGINE_ID_DIGF,
+ ENGINE_ID_DIGG,
+- ENGINE_ID_DVO,
+ ENGINE_ID_DACA,
+ ENGINE_ID_DACB,
+ ENGINE_ID_VCE, /* wireless display pseudo-encoder */
+@@ -225,7 +205,6 @@ union supported_stream_engines {
+ uint32_t ENGINE_ID_DIGE:1;
+ uint32_t ENGINE_ID_DIGF:1;
+ uint32_t ENGINE_ID_DIGG:1;
+- uint32_t ENGINE_ID_DVO:1;
+ uint32_t ENGINE_ID_DACA:1;
+ uint32_t ENGINE_ID_DACB:1;
+ uint32_t ENGINE_ID_VCE:1;
+--
+2.7.4
+
generated by cgit 1.2.3-korg (git 2.39.0) at 2024-04-20 04:15:33 +0000