diff options
Diffstat (limited to 'common/recipes-kernel/linux/files/0709-drm-amd-dal-Add-PreModeChange-event-to-PPLIB.patch')
| -rw-r--r-- | common/recipes-kernel/linux/files/0709-drm-amd-dal-Add-PreModeChange-event-to-PPLIB.patch | 116 |
1 files changed, 116 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/files/0709-drm-amd-dal-Add-PreModeChange-event-to-PPLIB.patch b/common/recipes-kernel/linux/files/0709-drm-amd-dal-Add-PreModeChange-event-to-PPLIB.patch new file mode 100644 index 00000000..8cbf3b98 --- /dev/null +++ b/common/recipes-kernel/linux/files/0709-drm-amd-dal-Add-PreModeChange-event-to-PPLIB.patch @@ -0,0 +1,116 @@ +From c3eeb9ac6864b945dcb60a84847d1afe9ef59776 Mon Sep 17 00:00:00 2001 +From: Anthony Koo <Anthony.Koo@amd.com> +Date: Thu, 14 Jan 2016 14:49:08 -0500 +Subject: [PATCH 0709/1110] drm/amd/dal: Add PreModeChange event to PPLIB + +[Description] +Before this change, we only send PostModeChange event. +What happens is that PPLIB does not know we are changing +display configuration beforehand. By the time we send Post +event, it is already too late, and this may cause soft hang +waiting on SMU to transition power states. + +This issues was found specifically during S3 resume tests, +when we commit 0 targets while entering S3 state. On +resume, we re-enable the display without first telling PPLIB. + +This change adds a PreModeChange notification at the start +of dc_commit_targets. + +Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> +Acked-by: Harry Wentland <harry.wentland@amd.com> +--- + drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dal_services.c | 16 ++++++++++++++++ + drivers/gpu/drm/amd/dal/dc/core/dc.c | 2 ++ + drivers/gpu/drm/amd/dal/dc/core/dc_resource.c | 6 ++++++ + drivers/gpu/drm/amd/dal/dc/dc_services.h | 3 +++ + drivers/gpu/drm/amd/dal/dc/inc/resource.h | 2 ++ + 5 files changed, 29 insertions(+) + +diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dal_services.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dal_services.c +index 12b9475..b67599d 100644 +--- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dal_services.c ++++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dal_services.c +@@ -157,6 +157,22 @@ bool dc_service_pp_pre_dce_clock_change( + return false; + } + ++bool dc_service_pp_apply_safe_state( ++ const struct dc_context *ctx) ++{ ++#ifdef CONFIG_DRM_AMD_POWERPLAY ++ struct amdgpu_device *adev = ctx->driver_context; ++ ++ if (adev->pm.dpm_enabled) { ++ /* TODO: Does this require PreModeChange event to PPLIB? */ ++ } ++ ++ return true; ++#else ++ return false; ++#endif ++} ++ + bool dc_service_pp_apply_display_requirements( + const struct dc_context *ctx, + const struct dc_pp_display_configuration *pp_display_cfg) +diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c +index e49ec86..b68ecb7 100644 +--- a/drivers/gpu/drm/amd/dal/dc/core/dc.c ++++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c +@@ -549,6 +549,8 @@ bool dc_commit_targets( + goto fail; + } + ++ pplib_apply_safe_state(dc); ++ + if (!dal_adapter_service_is_in_accelerated_mode( + dc->res_pool.adapter_srv)) { + dc->hwss.enable_accelerated_mode(dc); +diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c +index 52fcdc1..7cc4ed2 100644 +--- a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c ++++ b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c +@@ -485,6 +485,12 @@ static void fill_display_configs( + pp_display_cfg->display_count = num_cfgs; + } + ++void pplib_apply_safe_state( ++ const struct dc *dc) ++{ ++ dc_service_pp_apply_safe_state(dc->ctx); ++} ++ + void pplib_apply_display_requirements( + const struct dc *dc, + const struct validate_context *context) +diff --git a/drivers/gpu/drm/amd/dal/dc/dc_services.h b/drivers/gpu/drm/amd/dal/dc/dc_services.h +index 907b415..b8b8b20 100644 +--- a/drivers/gpu/drm/amd/dal/dc/dc_services.h ++++ b/drivers/gpu/drm/amd/dal/dc/dc_services.h +@@ -201,6 +201,9 @@ bool dc_service_pp_get_clock_levels_by_type( + struct dc_pp_clock_levels *clk_level_info); + + ++bool dc_service_pp_apply_safe_state( ++ const struct dc_context *ctx); ++ + /* DAL calls this function to notify PP about completion of Mode Set. + * For PP it means that current DCE clocks are those which were returned + * by dc_service_pp_pre_dce_clock_change(), in the 'output' parameter. +diff --git a/drivers/gpu/drm/amd/dal/dc/inc/resource.h b/drivers/gpu/drm/amd/dal/dc/inc/resource.h +index fac4c8b..ea6be75 100644 +--- a/drivers/gpu/drm/amd/dal/dc/inc/resource.h ++++ b/drivers/gpu/drm/amd/dal/dc/inc/resource.h +@@ -61,6 +61,8 @@ bool logical_attach_surfaces_to_target( + uint8_t surface_count, + struct dc_target *dc_target); + ++void pplib_apply_safe_state(const struct dc *dc); ++ + void pplib_apply_display_requirements( + const struct dc *dc, + const struct validate_context *context); +-- +2.7.4 + |