diff options
Diffstat (limited to 'common/recipes-kernel/linux/files/0698-drm-amdgpu-vce-use-multiple-cache-surface-starting-f.patch')
-rw-r--r-- | common/recipes-kernel/linux/files/0698-drm-amdgpu-vce-use-multiple-cache-surface-starting-f.patch | 59 |
1 files changed, 0 insertions, 59 deletions
diff --git a/common/recipes-kernel/linux/files/0698-drm-amdgpu-vce-use-multiple-cache-surface-starting-f.patch b/common/recipes-kernel/linux/files/0698-drm-amdgpu-vce-use-multiple-cache-surface-starting-f.patch deleted file mode 100644 index a60e8a61..00000000 --- a/common/recipes-kernel/linux/files/0698-drm-amdgpu-vce-use-multiple-cache-surface-starting-f.patch +++ /dev/null @@ -1,59 +0,0 @@ -From 3c0ff9f18f8239f5a8a4e251fef79384af3d935c Mon Sep 17 00:00:00 2001 -From: Leo Liu <leo.liu@amd.com> -Date: Tue, 17 Nov 2015 10:25:31 -0500 -Subject: [PATCH 0698/1565] drm/amdgpu: vce use multiple cache surface starting - from stoney - -Signed-off-by: Leo Liu <leo.liu@amd.com> -Reviewed-by: Alex Deucher <alexander.deucher@amd.com> ---- - drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 19 ++++++++++++++----- - 1 file changed, 14 insertions(+), 5 deletions(-) - -diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c -index 3acff3a..370c6c9 100644 ---- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c -+++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c -@@ -40,6 +40,9 @@ - - #define GRBM_GFX_INDEX__VCE_INSTANCE__SHIFT 0x04 - #define GRBM_GFX_INDEX__VCE_INSTANCE_MASK 0x10 -+#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR0 0x8616 -+#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR1 0x8617 -+#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR2 0x8618 - - #define VCE_V3_0_FW_SIZE (384 * 1024) - #define VCE_V3_0_STACK_SIZE (64 * 1024) -@@ -130,9 +133,11 @@ static int vce_v3_0_start(struct amdgpu_device *adev) - - /* set BUSY flag */ - WREG32_P(mmVCE_STATUS, 1, ~1); -- -- WREG32_P(mmVCE_VCPU_CNTL, VCE_VCPU_CNTL__CLK_EN_MASK, -- ~VCE_VCPU_CNTL__CLK_EN_MASK); -+ if (adev->asic_type >= CHIP_STONEY) -+ WREG32_P(mmVCE_VCPU_CNTL, 1, ~0x200001); -+ else -+ WREG32_P(mmVCE_VCPU_CNTL, VCE_VCPU_CNTL__CLK_EN_MASK, -+ ~VCE_VCPU_CNTL__CLK_EN_MASK); - - WREG32_P(mmVCE_SOFT_RESET, - VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK, -@@ -391,8 +396,12 @@ static void vce_v3_0_mc_resume(struct amdgpu_device *adev, int idx) - WREG32(mmVCE_LMI_SWAP_CNTL, 0); - WREG32(mmVCE_LMI_SWAP_CNTL1, 0); - WREG32(mmVCE_LMI_VM_CTRL, 0); -- -- WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR, (adev->vce.gpu_addr >> 8)); -+ if (adev->asic_type >= CHIP_STONEY) { -+ WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR0, (adev->vce.gpu_addr >> 8)); -+ WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR1, (adev->vce.gpu_addr >> 8)); -+ WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR2, (adev->vce.gpu_addr >> 8)); -+ } else -+ WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR, (adev->vce.gpu_addr >> 8)); - offset = AMDGPU_VCE_FIRMWARE_OFFSET; - size = VCE_V3_0_FW_SIZE; - WREG32(mmVCE_VCPU_CACHE_OFFSET0, offset & 0x7fffffff); --- -1.9.1 - |