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-rw-r--r--common/recipes-kernel/linux/files/0690-drm-amdgpu-Initial-Tonga-Light-up.patch216
1 files changed, 216 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/files/0690-drm-amdgpu-Initial-Tonga-Light-up.patch b/common/recipes-kernel/linux/files/0690-drm-amdgpu-Initial-Tonga-Light-up.patch
new file mode 100644
index 00000000..8cd267ce
--- /dev/null
+++ b/common/recipes-kernel/linux/files/0690-drm-amdgpu-Initial-Tonga-Light-up.patch
@@ -0,0 +1,216 @@
+From 91d210eb79966cddb5d4d4d01d96d6643287be6b Mon Sep 17 00:00:00 2001
+From: Eric Yang <eric.yang2@amd.com>
+Date: Mon, 18 Jan 2016 16:52:24 -0500
+Subject: [PATCH 0690/1110] drm/amdgpu: Initial Tonga Light up
+
+Use DM functions for tonga and fiji when DAL is enabled.
+This change combined with a change in DAL allows tonga light up
+with DAL.
+
+Signed-off-by: Eric Yang <eric.yang2@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 5 +
+ drivers/gpu/drm/amd/amdgpu/vi.c | 156 +++++++++++++++++++++++++++++
+ 2 files changed, 161 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index 7c27e5a..3de29d9 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -1398,6 +1398,11 @@ bool amdgpu_device_has_dal_support(struct amdgpu_device *adev)
+ case CHIP_CARRIZO:
+ return true;
+ #endif
++#if defined(CONFIG_DRM_AMD_DAL) && defined(CONFIG_DRM_AMD_DAL_DCE10_0)
++ case CHIP_TONGA:
++ case CHIP_FIJI:
++ return true;
++#endif
+ default:
+ return false;
+ }
+diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
+index c3b5ed6..fc02cad 100644
+--- a/drivers/gpu/drm/amd/amdgpu/vi.c
++++ b/drivers/gpu/drm/amd/amdgpu/vi.c
+@@ -1066,6 +1066,142 @@ static const struct amdgpu_ip_block_version cz_ip_blocks_dal[] =
+ },
+ #endif
+ };
++
++static const struct amdgpu_ip_block_version tonga_ip_blocks_dal[] =
++{
++ /* ORDER MATTERS! */
++ {
++ .type = AMD_IP_BLOCK_TYPE_COMMON,
++ .major = 2,
++ .minor = 0,
++ .rev = 0,
++ .funcs = &vi_common_ip_funcs,
++ },
++ {
++ .type = AMD_IP_BLOCK_TYPE_GMC,
++ .major = 8,
++ .minor = 0,
++ .rev = 0,
++ .funcs = &gmc_v8_0_ip_funcs,
++ },
++ {
++ .type = AMD_IP_BLOCK_TYPE_IH,
++ .major = 3,
++ .minor = 0,
++ .rev = 0,
++ .funcs = &tonga_ih_ip_funcs,
++ },
++ {
++ .type = AMD_IP_BLOCK_TYPE_SMC,
++ .major = 7,
++ .minor = 1,
++ .rev = 0,
++ .funcs = &amdgpu_pp_ip_funcs,
++ },
++ {
++ .type = AMD_IP_BLOCK_TYPE_DCE,
++ .major = 10,
++ .minor = 0,
++ .rev = 0,
++ .funcs = &amdgpu_dm_funcs,
++ },
++ {
++ .type = AMD_IP_BLOCK_TYPE_GFX,
++ .major = 8,
++ .minor = 0,
++ .rev = 0,
++ .funcs = &gfx_v8_0_ip_funcs,
++ },
++ {
++ .type = AMD_IP_BLOCK_TYPE_SDMA,
++ .major = 3,
++ .minor = 0,
++ .rev = 0,
++ .funcs = &sdma_v3_0_ip_funcs,
++ },
++ {
++ .type = AMD_IP_BLOCK_TYPE_UVD,
++ .major = 5,
++ .minor = 0,
++ .rev = 0,
++ .funcs = &uvd_v5_0_ip_funcs,
++ },
++ {
++ .type = AMD_IP_BLOCK_TYPE_VCE,
++ .major = 3,
++ .minor = 0,
++ .rev = 0,
++ .funcs = &vce_v3_0_ip_funcs,
++ },
++};
++
++static const struct amdgpu_ip_block_version fiji_ip_blocks_dal[] =
++{
++ /* ORDER MATTERS! */
++ {
++ .type = AMD_IP_BLOCK_TYPE_COMMON,
++ .major = 2,
++ .minor = 0,
++ .rev = 0,
++ .funcs = &vi_common_ip_funcs,
++ },
++ {
++ .type = AMD_IP_BLOCK_TYPE_GMC,
++ .major = 8,
++ .minor = 5,
++ .rev = 0,
++ .funcs = &gmc_v8_0_ip_funcs,
++ },
++ {
++ .type = AMD_IP_BLOCK_TYPE_IH,
++ .major = 3,
++ .minor = 0,
++ .rev = 0,
++ .funcs = &tonga_ih_ip_funcs,
++ },
++ {
++ .type = AMD_IP_BLOCK_TYPE_SMC,
++ .major = 7,
++ .minor = 1,
++ .rev = 0,
++ .funcs = &amdgpu_pp_ip_funcs,
++ },
++ {
++ .type = AMD_IP_BLOCK_TYPE_DCE,
++ .major = 10,
++ .minor = 1,
++ .rev = 0,
++ .funcs = &amdgpu_dm_funcs,
++ },
++ {
++ .type = AMD_IP_BLOCK_TYPE_GFX,
++ .major = 8,
++ .minor = 0,
++ .rev = 0,
++ .funcs = &gfx_v8_0_ip_funcs,
++ },
++ {
++ .type = AMD_IP_BLOCK_TYPE_SDMA,
++ .major = 3,
++ .minor = 0,
++ .rev = 0,
++ .funcs = &sdma_v3_0_ip_funcs,
++ },
++ {
++ .type = AMD_IP_BLOCK_TYPE_UVD,
++ .major = 6,
++ .minor = 0,
++ .rev = 0,
++ .funcs = &uvd_v6_0_ip_funcs,
++ },
++ {
++ .type = AMD_IP_BLOCK_TYPE_VCE,
++ .major = 3,
++ .minor = 0,
++ .rev = 0,
++ .funcs = &vce_v3_0_ip_funcs,
++ },
++};
+ #endif
+
+ int vi_set_ip_blocks(struct amdgpu_device *adev)
+@@ -1076,12 +1212,32 @@ int vi_set_ip_blocks(struct amdgpu_device *adev)
+ adev->num_ip_blocks = ARRAY_SIZE(topaz_ip_blocks);
+ break;
+ case CHIP_FIJI:
++#if defined(CONFIG_DRM_AMD_DAL)
++ if (amdgpu_dal && amdgpu_device_has_dal_support(adev)) {
++ adev->ip_blocks = fiji_ip_blocks_dal;
++ adev->num_ip_blocks = ARRAY_SIZE(fiji_ip_blocks_dal);
++ } else {
++ adev->ip_blocks = fiji_ip_blocks;
++ adev->num_ip_blocks = ARRAY_SIZE(fiji_ip_blocks);
++ }
++#else
+ adev->ip_blocks = fiji_ip_blocks;
+ adev->num_ip_blocks = ARRAY_SIZE(fiji_ip_blocks);
++#endif
+ break;
+ case CHIP_TONGA:
++#if defined(CONFIG_DRM_AMD_DAL)
++ if (amdgpu_dal && amdgpu_device_has_dal_support(adev)) {
++ adev->ip_blocks = tonga_ip_blocks_dal;
++ adev->num_ip_blocks = ARRAY_SIZE(tonga_ip_blocks_dal);
++ } else {
++ adev->ip_blocks = tonga_ip_blocks;
++ adev->num_ip_blocks = ARRAY_SIZE(tonga_ip_blocks);
++ }
++#else
+ adev->ip_blocks = tonga_ip_blocks;
+ adev->num_ip_blocks = ARRAY_SIZE(tonga_ip_blocks);
++#endif
+ break;
+ case CHIP_CARRIZO:
+ case CHIP_STONEY:
+--
+2.7.4
+