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-rw-r--r--common/recipes-kernel/linux/files/0663-drm-amd-dal-Fix-and-refactor-DCE8.0-resource.patch171
1 files changed, 171 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/files/0663-drm-amd-dal-Fix-and-refactor-DCE8.0-resource.patch b/common/recipes-kernel/linux/files/0663-drm-amd-dal-Fix-and-refactor-DCE8.0-resource.patch
new file mode 100644
index 00000000..acc6aacc
--- /dev/null
+++ b/common/recipes-kernel/linux/files/0663-drm-amd-dal-Fix-and-refactor-DCE8.0-resource.patch
@@ -0,0 +1,171 @@
+From 3f48989ca1abfcd9a60e29be1b0ea2297d74562c Mon Sep 17 00:00:00 2001
+From: Aric Cyr <aric.cyr@amd.com>
+Date: Tue, 5 Jan 2016 17:24:37 -0500
+Subject: [PATCH 0663/1110] drm/amd/dal: Fix and refactor DCE8.0 resource
+
+Signed-off-by: Aric Cyr <aric.cyr@amd.com>
+Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
+---
+ .../gpu/drm/amd/dal/dc/dce110/dce110_resource.c | 2 +-
+ .../amd/dal/dc/dce110/dce110_timing_generator.c | 46 +++++++---------------
+ .../amd/dal/dc/dce110/dce110_timing_generator.h | 4 +-
+ .../drm/amd/dal/include/timing_generator_types.h | 2 +
+ 4 files changed, 19 insertions(+), 35 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
+index d789853..d7eea0d 100644
+--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
++++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
+@@ -811,7 +811,7 @@ enum dc_status dce110_validate_with_context(
+ result = dce_base_map_resources(dc, context);
+
+ if (result == DC_OK)
+- result = map_clock_resources(dc, context);
++ result = map_clock_resources(dc, context);
+
+ if (result == DC_OK)
+ result = validate_mapped_resource(dc, context);
+diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
+index b47ba61..2c7c27f 100644
+--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
++++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
+@@ -144,6 +144,8 @@ static struct timing_generator_funcs dce110_tg_funcs = {
+ .disable_reset_trigger = dce110_timing_generator_disable_reset_trigger,
+ .tear_down_global_swap_lock =
+ dce110_timing_generator_tear_down_global_swap_lock,
++ .enable_advanced_request =
++ dce110_timing_generator_enable_advanced_request
+ };
+
+ static const struct crtc_black_color black_color_format[] = {
+@@ -186,12 +188,6 @@ static void dce110_timing_generator_apply_front_porch_workaround(
+ }
+ }
+
+-static int32_t dce110_timing_generator_get_vsynch_and_front_porch_size(
+- const struct dc_crtc_timing *timing)
+-{
+- return timing->v_sync_width + timing->v_front_porch;
+-}
+-
+ static void dce110_timing_generator_color_space_to_black_color(
+ enum color_space colorspace,
+ struct crtc_black_color *black_color)
+@@ -521,7 +517,6 @@ bool dce110_timing_generator_program_timing_generator(
+ enum bp_result result;
+ struct bp_hw_crtc_timing_parameters bp_params;
+ struct dc_crtc_timing patched_crtc_timing;
+- uint32_t regval;
+ struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
+
+ uint32_t vsync_offset = dc_crtc_timing->v_border_bottom +
+@@ -581,28 +576,7 @@ bool dce110_timing_generator_program_timing_generator(
+
+ program_horz_count_by_2(tg, &patched_crtc_timing);
+
+- regval = dal_read_reg(tg->ctx,
+- CRTC_REG(mmCRTC_START_LINE_CONTROL));
+-
+- if (dce110_timing_generator_get_vsynch_and_front_porch_size(&patched_crtc_timing) <= 3) {
+- set_reg_field_value(regval, 3,
+- CRTC_START_LINE_CONTROL,
+- CRTC_ADVANCED_START_LINE_POSITION);
+-
+- set_reg_field_value(regval, 0,
+- CRTC_START_LINE_CONTROL,
+- CRTC_PREFETCH_EN);
+- } else {
+- set_reg_field_value(regval, 4,
+- CRTC_START_LINE_CONTROL,
+- CRTC_ADVANCED_START_LINE_POSITION);
+-
+- set_reg_field_value(regval, 1,
+- CRTC_START_LINE_CONTROL,
+- CRTC_PREFETCH_EN);
+- }
+- dal_write_reg(tg->ctx,
+- CRTC_REG(mmCRTC_START_LINE_CONTROL), regval);
++ tg110->base.funcs->enable_advanced_request(tg, true, &patched_crtc_timing);
+
+ /* Enable stereo - only when we need to pack 3D frame. Other types
+ * of stereo handled in explicit call */
+@@ -1342,7 +1316,6 @@ bool dce110_timing_generator_is_counter_moving(struct timing_generator *tg)
+ return true;
+ }
+
+-/*TODO: Figure out if we need this function. */
+ void dce110_timing_generator_enable_advanced_request(
+ struct timing_generator *tg,
+ bool enable,
+@@ -1352,7 +1325,7 @@ void dce110_timing_generator_enable_advanced_request(
+ uint32_t addr = CRTC_REG(mmCRTC_START_LINE_CONTROL);
+ uint32_t value = dal_read_reg(tg->ctx, addr);
+
+- if (enable && DCE110TG_FROM_TG(tg)->advanced_request_enable) {
++ if (enable && !DCE110TG_FROM_TG(tg)->disable_advanced_request) {
+ set_reg_field_value(
+ value,
+ 0,
+@@ -1366,7 +1339,7 @@ void dce110_timing_generator_enable_advanced_request(
+ CRTC_LEGACY_REQUESTOR_EN);
+ }
+
+- if (dce110_timing_generator_get_vsynch_and_front_porch_size(timing) <= 3) {
++ if ((timing->v_sync_width + timing->v_front_porch) <= 3) {
+ set_reg_field_value(
+ value,
+ 3,
+@@ -1624,6 +1597,15 @@ void dce110_timing_generator_disable_vga(
+ case CONTROLLER_ID_D2:
+ addr = mmD3VGA_CONTROL;
+ break;
++ case CONTROLLER_ID_D3:
++ addr = mmD4VGA_CONTROL;
++ break;
++ case CONTROLLER_ID_D4:
++ addr = mmD5VGA_CONTROL;
++ break;
++ case CONTROLLER_ID_D5:
++ addr = mmD6VGA_CONTROL;
++ break;
+ default:
+ break;
+ }
+diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.h
+index 4192972..c787530 100644
+--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.h
++++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.h
+@@ -69,7 +69,7 @@ struct dce110_timing_generator {
+ uint32_t min_h_back_porch;
+
+ enum sync_source cached_gsl_group;
+- bool advanced_request_enable;
++ bool disable_advanced_request;
+ };
+
+ #define DCE110TG_FROM_TG(tg)\
+@@ -79,7 +79,7 @@ bool dce110_timing_generator_construct(
+ struct dce110_timing_generator *tg,
+ struct adapter_service *as,
+ struct dc_context *ctx,
+- enum controller_id id,
++ uint32_t instance,
+ const struct dce110_timing_generator_offsets *offsets);
+
+ /* determine if given timing can be supported by TG */
+diff --git a/drivers/gpu/drm/amd/dal/include/timing_generator_types.h b/drivers/gpu/drm/amd/dal/include/timing_generator_types.h
+index 15773c0..3f5f1ec 100644
+--- a/drivers/gpu/drm/amd/dal/include/timing_generator_types.h
++++ b/drivers/gpu/drm/amd/dal/include/timing_generator_types.h
+@@ -182,6 +182,8 @@ struct timing_generator_funcs {
+ const struct trigger_params *trigger_params);
+ void (*disable_reset_trigger)(struct timing_generator *tg);
+ void (*tear_down_global_swap_lock)(struct timing_generator *tg);
++ void (*enable_advanced_request)(struct timing_generator *tg,
++ bool enable, const struct dc_crtc_timing *timing);
+ };
+
+ #endif
+--
+2.7.4
+