diff options
Diffstat (limited to 'common/recipes-kernel/linux/files/0642-drm-amdgpu-dce10-optimize-pageflip.patch')
| -rw-r--r-- | common/recipes-kernel/linux/files/0642-drm-amdgpu-dce10-optimize-pageflip.patch | 78 |
1 files changed, 0 insertions, 78 deletions
diff --git a/common/recipes-kernel/linux/files/0642-drm-amdgpu-dce10-optimize-pageflip.patch b/common/recipes-kernel/linux/files/0642-drm-amdgpu-dce10-optimize-pageflip.patch deleted file mode 100644 index 6ff93ac7..00000000 --- a/common/recipes-kernel/linux/files/0642-drm-amdgpu-dce10-optimize-pageflip.patch +++ /dev/null @@ -1,78 +0,0 @@ -From 0eaaacab038ec03c010cd820554cfa6d1a93cd78 Mon Sep 17 00:00:00 2001 -From: Alex Deucher <alexander.deucher@amd.com> -Date: Thu, 22 Oct 2015 14:16:57 -0400 -Subject: [PATCH 0642/1565] drm/amdgpu/dce10: optimize pageflip -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Taking the grph update lock is only necessary when -updating the the secondary address (for single pipe stereo). - -Reviewed-by: Christian König <christian.koenig@amd.com> -Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> -Signed-off-by: Alex Deucher <alexander.deucher@amd.com> ---- - drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 36 ++++++---------------------------- - 1 file changed, 6 insertions(+), 30 deletions(-) - -diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c -index a6ea2d8..6132051 100644 ---- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c -+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c -@@ -262,46 +262,22 @@ static u32 dce_v10_0_vblank_get_counter(struct amdgpu_device *adev, int crtc) - * @crtc_id: crtc to cleanup pageflip on - * @crtc_base: new address of the crtc (GPU MC address) - * -- * Does the actual pageflip (evergreen+). -- * During vblank we take the crtc lock and wait for the update_pending -- * bit to go high, when it does, we release the lock, and allow the -- * double buffered update to take place. -- * Returns the current update pending status. -+ * Triggers the actual pageflip by updating the primary -+ * surface base address. - */ - static void dce_v10_0_page_flip(struct amdgpu_device *adev, - int crtc_id, u64 crtc_base) - { - struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; -- u32 tmp = RREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset); -- int i; -- -- /* Lock the graphics update lock */ -- tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 1); -- WREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset, tmp); -- -- /* update the scanout addresses */ -- WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, -- upper_32_bits(crtc_base)); -- WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, -- lower_32_bits(crtc_base)); - -+ /* update the primary scanout address */ - WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, - upper_32_bits(crtc_base)); -+ /* writing to the low address triggers the update */ - WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, - lower_32_bits(crtc_base)); -- -- /* Wait for update_pending to go high. */ -- for (i = 0; i < adev->usec_timeout; i++) { -- if (RREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset) & -- GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK) -- break; -- udelay(1); -- } -- DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n"); -- -- /* Unlock the lock, so double-buffering can take place inside vblank */ -- tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 0); -- WREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset, tmp); -+ /* post the write */ -+ RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset); - } - - static int dce_v10_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, --- -1.9.1 - |