aboutsummaryrefslogtreecommitdiffstats
path: root/common/recipes-kernel/linux/files/0579-drm-amdgpu-split-gfx8-gpu-init-into-sw-and-hw-parts.patch
diff options
context:
space:
mode:
Diffstat (limited to 'common/recipes-kernel/linux/files/0579-drm-amdgpu-split-gfx8-gpu-init-into-sw-and-hw-parts.patch')
-rw-r--r--common/recipes-kernel/linux/files/0579-drm-amdgpu-split-gfx8-gpu-init-into-sw-and-hw-parts.patch455
1 files changed, 0 insertions, 455 deletions
diff --git a/common/recipes-kernel/linux/files/0579-drm-amdgpu-split-gfx8-gpu-init-into-sw-and-hw-parts.patch b/common/recipes-kernel/linux/files/0579-drm-amdgpu-split-gfx8-gpu-init-into-sw-and-hw-parts.patch
deleted file mode 100644
index 49df355f..00000000
--- a/common/recipes-kernel/linux/files/0579-drm-amdgpu-split-gfx8-gpu-init-into-sw-and-hw-parts.patch
+++ /dev/null
@@ -1,455 +0,0 @@
-From 0bde3a95eaa90f130dbb71a846243aa6f0e678cf Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Thu, 3 Sep 2015 17:58:06 -0400
-Subject: [PATCH 0579/1565] drm/amdgpu: split gfx8 gpu init into sw and hw
- parts
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Calculate the driver state in sw_init and program the
-registers in hw init.
-
-Acked-by: Leo Liu <leo.liu@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 387 +++++++++++++++++-----------------
- 1 file changed, 197 insertions(+), 190 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-index cb4f68f..718250a 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-@@ -903,6 +903,191 @@ static int gfx_v8_0_mec_init(struct amdgpu_device *adev)
- return 0;
- }
-
-+static void gfx_v8_0_gpu_early_init(struct amdgpu_device *adev)
-+{
-+ u32 gb_addr_config;
-+ u32 mc_shared_chmap, mc_arb_ramcfg;
-+ u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map;
-+ u32 tmp;
-+
-+ switch (adev->asic_type) {
-+ case CHIP_TOPAZ:
-+ adev->gfx.config.max_shader_engines = 1;
-+ adev->gfx.config.max_tile_pipes = 2;
-+ adev->gfx.config.max_cu_per_sh = 6;
-+ adev->gfx.config.max_sh_per_se = 1;
-+ adev->gfx.config.max_backends_per_se = 2;
-+ adev->gfx.config.max_texture_channel_caches = 2;
-+ adev->gfx.config.max_gprs = 256;
-+ adev->gfx.config.max_gs_threads = 32;
-+ adev->gfx.config.max_hw_contexts = 8;
-+
-+ adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
-+ adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
-+ adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
-+ adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
-+ gb_addr_config = TOPAZ_GB_ADDR_CONFIG_GOLDEN;
-+ break;
-+ case CHIP_FIJI:
-+ adev->gfx.config.max_shader_engines = 4;
-+ adev->gfx.config.max_tile_pipes = 16;
-+ adev->gfx.config.max_cu_per_sh = 16;
-+ adev->gfx.config.max_sh_per_se = 1;
-+ adev->gfx.config.max_backends_per_se = 4;
-+ adev->gfx.config.max_texture_channel_caches = 8;
-+ adev->gfx.config.max_gprs = 256;
-+ adev->gfx.config.max_gs_threads = 32;
-+ adev->gfx.config.max_hw_contexts = 8;
-+
-+ adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
-+ adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
-+ adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
-+ adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
-+ gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
-+ break;
-+ case CHIP_TONGA:
-+ adev->gfx.config.max_shader_engines = 4;
-+ adev->gfx.config.max_tile_pipes = 8;
-+ adev->gfx.config.max_cu_per_sh = 8;
-+ adev->gfx.config.max_sh_per_se = 1;
-+ adev->gfx.config.max_backends_per_se = 2;
-+ adev->gfx.config.max_texture_channel_caches = 8;
-+ adev->gfx.config.max_gprs = 256;
-+ adev->gfx.config.max_gs_threads = 32;
-+ adev->gfx.config.max_hw_contexts = 8;
-+
-+ adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
-+ adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
-+ adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
-+ adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
-+ gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
-+ break;
-+ case CHIP_CARRIZO:
-+ adev->gfx.config.max_shader_engines = 1;
-+ adev->gfx.config.max_tile_pipes = 2;
-+ adev->gfx.config.max_sh_per_se = 1;
-+ adev->gfx.config.max_backends_per_se = 2;
-+
-+ switch (adev->pdev->revision) {
-+ case 0xc4:
-+ case 0x84:
-+ case 0xc8:
-+ case 0xcc:
-+ /* B10 */
-+ adev->gfx.config.max_cu_per_sh = 8;
-+ break;
-+ case 0xc5:
-+ case 0x81:
-+ case 0x85:
-+ case 0xc9:
-+ case 0xcd:
-+ /* B8 */
-+ adev->gfx.config.max_cu_per_sh = 6;
-+ break;
-+ case 0xc6:
-+ case 0xca:
-+ case 0xce:
-+ /* B6 */
-+ adev->gfx.config.max_cu_per_sh = 6;
-+ break;
-+ case 0xc7:
-+ case 0x87:
-+ case 0xcb:
-+ default:
-+ /* B4 */
-+ adev->gfx.config.max_cu_per_sh = 4;
-+ break;
-+ }
-+
-+ adev->gfx.config.max_texture_channel_caches = 2;
-+ adev->gfx.config.max_gprs = 256;
-+ adev->gfx.config.max_gs_threads = 32;
-+ adev->gfx.config.max_hw_contexts = 8;
-+
-+ adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
-+ adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
-+ adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
-+ adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
-+ gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN;
-+ break;
-+ default:
-+ adev->gfx.config.max_shader_engines = 2;
-+ adev->gfx.config.max_tile_pipes = 4;
-+ adev->gfx.config.max_cu_per_sh = 2;
-+ adev->gfx.config.max_sh_per_se = 1;
-+ adev->gfx.config.max_backends_per_se = 2;
-+ adev->gfx.config.max_texture_channel_caches = 4;
-+ adev->gfx.config.max_gprs = 256;
-+ adev->gfx.config.max_gs_threads = 32;
-+ adev->gfx.config.max_hw_contexts = 8;
-+
-+ adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
-+ adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
-+ adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
-+ adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
-+ gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
-+ break;
-+ }
-+
-+ mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);
-+ adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
-+ mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
-+
-+ adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
-+ adev->gfx.config.mem_max_burst_length_bytes = 256;
-+ if (adev->flags & AMD_IS_APU) {
-+ /* Get memory bank mapping mode. */
-+ tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING);
-+ dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
-+ dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
-+
-+ tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING);
-+ dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
-+ dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
-+
-+ /* Validate settings in case only one DIMM installed. */
-+ if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12))
-+ dimm00_addr_map = 0;
-+ if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12))
-+ dimm01_addr_map = 0;
-+ if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12))
-+ dimm10_addr_map = 0;
-+ if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12))
-+ dimm11_addr_map = 0;
-+
-+ /* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */
-+ /* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */
-+ if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11))
-+ adev->gfx.config.mem_row_size_in_kb = 2;
-+ else
-+ adev->gfx.config.mem_row_size_in_kb = 1;
-+ } else {
-+ tmp = REG_GET_FIELD(mc_arb_ramcfg, MC_ARB_RAMCFG, NOOFCOLS);
-+ adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
-+ if (adev->gfx.config.mem_row_size_in_kb > 4)
-+ adev->gfx.config.mem_row_size_in_kb = 4;
-+ }
-+
-+ adev->gfx.config.shader_engine_tile_size = 32;
-+ adev->gfx.config.num_gpus = 1;
-+ adev->gfx.config.multi_gpu_tile_size = 64;
-+
-+ /* fix up row size */
-+ switch (adev->gfx.config.mem_row_size_in_kb) {
-+ case 1:
-+ default:
-+ gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 0);
-+ break;
-+ case 2:
-+ gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 1);
-+ break;
-+ case 4:
-+ gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 2);
-+ break;
-+ }
-+ adev->gfx.config.gb_addr_config = gb_addr_config;
-+}
-+
- static int gfx_v8_0_sw_init(void *handle)
- {
- int i, r;
-@@ -1010,6 +1195,8 @@ static int gfx_v8_0_sw_init(void *handle)
-
- adev->gfx.ce_ram_size = 0x8000;
-
-+ gfx_v8_0_gpu_early_init(adev);
-+
- return 0;
- }
-
-@@ -2043,203 +2230,23 @@ static void gfx_v8_0_init_compute_vmid(struct amdgpu_device *adev)
-
- static void gfx_v8_0_gpu_init(struct amdgpu_device *adev)
- {
-- u32 gb_addr_config;
-- u32 mc_shared_chmap, mc_arb_ramcfg;
-- u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map;
- u32 tmp;
- int i;
-
-- switch (adev->asic_type) {
-- case CHIP_TOPAZ:
-- adev->gfx.config.max_shader_engines = 1;
-- adev->gfx.config.max_tile_pipes = 2;
-- adev->gfx.config.max_cu_per_sh = 6;
-- adev->gfx.config.max_sh_per_se = 1;
-- adev->gfx.config.max_backends_per_se = 2;
-- adev->gfx.config.max_texture_channel_caches = 2;
-- adev->gfx.config.max_gprs = 256;
-- adev->gfx.config.max_gs_threads = 32;
-- adev->gfx.config.max_hw_contexts = 8;
--
-- adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
-- adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
-- adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
-- adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
-- gb_addr_config = TOPAZ_GB_ADDR_CONFIG_GOLDEN;
-- break;
-- case CHIP_FIJI:
-- adev->gfx.config.max_shader_engines = 4;
-- adev->gfx.config.max_tile_pipes = 16;
-- adev->gfx.config.max_cu_per_sh = 16;
-- adev->gfx.config.max_sh_per_se = 1;
-- adev->gfx.config.max_backends_per_se = 4;
-- adev->gfx.config.max_texture_channel_caches = 8;
-- adev->gfx.config.max_gprs = 256;
-- adev->gfx.config.max_gs_threads = 32;
-- adev->gfx.config.max_hw_contexts = 8;
--
-- adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
-- adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
-- adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
-- adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
-- gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
-- break;
-- case CHIP_TONGA:
-- adev->gfx.config.max_shader_engines = 4;
-- adev->gfx.config.max_tile_pipes = 8;
-- adev->gfx.config.max_cu_per_sh = 8;
-- adev->gfx.config.max_sh_per_se = 1;
-- adev->gfx.config.max_backends_per_se = 2;
-- adev->gfx.config.max_texture_channel_caches = 8;
-- adev->gfx.config.max_gprs = 256;
-- adev->gfx.config.max_gs_threads = 32;
-- adev->gfx.config.max_hw_contexts = 8;
--
-- adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
-- adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
-- adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
-- adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
-- gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
-- break;
-- case CHIP_CARRIZO:
-- adev->gfx.config.max_shader_engines = 1;
-- adev->gfx.config.max_tile_pipes = 2;
-- adev->gfx.config.max_sh_per_se = 1;
-- adev->gfx.config.max_backends_per_se = 2;
--
-- switch (adev->pdev->revision) {
-- case 0xc4:
-- case 0x84:
-- case 0xc8:
-- case 0xcc:
-- /* B10 */
-- adev->gfx.config.max_cu_per_sh = 8;
-- break;
-- case 0xc5:
-- case 0x81:
-- case 0x85:
-- case 0xc9:
-- case 0xcd:
-- /* B8 */
-- adev->gfx.config.max_cu_per_sh = 6;
-- break;
-- case 0xc6:
-- case 0xca:
-- case 0xce:
-- /* B6 */
-- adev->gfx.config.max_cu_per_sh = 6;
-- break;
-- case 0xc7:
-- case 0x87:
-- case 0xcb:
-- default:
-- /* B4 */
-- adev->gfx.config.max_cu_per_sh = 4;
-- break;
-- }
--
-- adev->gfx.config.max_texture_channel_caches = 2;
-- adev->gfx.config.max_gprs = 256;
-- adev->gfx.config.max_gs_threads = 32;
-- adev->gfx.config.max_hw_contexts = 8;
--
-- adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
-- adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
-- adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
-- adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
-- gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN;
-- break;
-- default:
-- adev->gfx.config.max_shader_engines = 2;
-- adev->gfx.config.max_tile_pipes = 4;
-- adev->gfx.config.max_cu_per_sh = 2;
-- adev->gfx.config.max_sh_per_se = 1;
-- adev->gfx.config.max_backends_per_se = 2;
-- adev->gfx.config.max_texture_channel_caches = 4;
-- adev->gfx.config.max_gprs = 256;
-- adev->gfx.config.max_gs_threads = 32;
-- adev->gfx.config.max_hw_contexts = 8;
--
-- adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
-- adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
-- adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
-- adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
-- gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
-- break;
-- }
--
- tmp = RREG32(mmGRBM_CNTL);
- tmp = REG_SET_FIELD(tmp, GRBM_CNTL, READ_TIMEOUT, 0xff);
- WREG32(mmGRBM_CNTL, tmp);
-
-- mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);
-- adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
-- mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
--
-- adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
-- adev->gfx.config.mem_max_burst_length_bytes = 256;
-- if (adev->flags & AMD_IS_APU) {
-- /* Get memory bank mapping mode. */
-- tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING);
-- dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
-- dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
--
-- tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING);
-- dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
-- dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
--
-- /* Validate settings in case only one DIMM installed. */
-- if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12))
-- dimm00_addr_map = 0;
-- if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12))
-- dimm01_addr_map = 0;
-- if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12))
-- dimm10_addr_map = 0;
-- if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12))
-- dimm11_addr_map = 0;
--
-- /* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */
-- /* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */
-- if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11))
-- adev->gfx.config.mem_row_size_in_kb = 2;
-- else
-- adev->gfx.config.mem_row_size_in_kb = 1;
-- } else {
-- tmp = REG_GET_FIELD(mc_arb_ramcfg, MC_ARB_RAMCFG, NOOFCOLS);
-- adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
-- if (adev->gfx.config.mem_row_size_in_kb > 4)
-- adev->gfx.config.mem_row_size_in_kb = 4;
-- }
--
-- adev->gfx.config.shader_engine_tile_size = 32;
-- adev->gfx.config.num_gpus = 1;
-- adev->gfx.config.multi_gpu_tile_size = 64;
--
-- /* fix up row size */
-- switch (adev->gfx.config.mem_row_size_in_kb) {
-- case 1:
-- default:
-- gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 0);
-- break;
-- case 2:
-- gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 1);
-- break;
-- case 4:
-- gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 2);
-- break;
-- }
-- adev->gfx.config.gb_addr_config = gb_addr_config;
--
-- WREG32(mmGB_ADDR_CONFIG, gb_addr_config);
-- WREG32(mmHDP_ADDR_CONFIG, gb_addr_config);
-- WREG32(mmDMIF_ADDR_CALC, gb_addr_config);
-+ WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
-+ WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
-+ WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config);
- WREG32(mmSDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET,
-- gb_addr_config & 0x70);
-+ adev->gfx.config.gb_addr_config & 0x70);
- WREG32(mmSDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET,
-- gb_addr_config & 0x70);
-- WREG32(mmUVD_UDEC_ADDR_CONFIG, gb_addr_config);
-- WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
-- WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
-+ adev->gfx.config.gb_addr_config & 0x70);
-+ WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
-+ WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
-+ WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
-
- gfx_v8_0_tiling_mode_table_init(adev);
-
-@@ -2256,13 +2263,13 @@ static void gfx_v8_0_gpu_init(struct amdgpu_device *adev)
- if (i == 0) {
- tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_UC);
- tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_UC);
-- tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
-+ tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
- SH_MEM_ALIGNMENT_MODE_UNALIGNED);
- WREG32(mmSH_MEM_CONFIG, tmp);
- } else {
- tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_NC);
- tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_NC);
-- tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
-+ tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
- SH_MEM_ALIGNMENT_MODE_UNALIGNED);
- WREG32(mmSH_MEM_CONFIG, tmp);
- }
---
-1.9.1
-
generated by cgit 1.2.3-korg (git 2.39.0) at 2024-04-24 09:54:36 +0000