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Diffstat (limited to 'common/recipes-kernel/linux/files/0564-drm-amd-dal-Bool-to-Void-on-Link-Encoder-Programming.patch')
-rw-r--r--common/recipes-kernel/linux/files/0564-drm-amd-dal-Bool-to-Void-on-Link-Encoder-Programming.patch760
1 files changed, 0 insertions, 760 deletions
diff --git a/common/recipes-kernel/linux/files/0564-drm-amd-dal-Bool-to-Void-on-Link-Encoder-Programming.patch b/common/recipes-kernel/linux/files/0564-drm-amd-dal-Bool-to-Void-on-Link-Encoder-Programming.patch
deleted file mode 100644
index fab78caf..00000000
--- a/common/recipes-kernel/linux/files/0564-drm-amd-dal-Bool-to-Void-on-Link-Encoder-Programming.patch
+++ /dev/null
@@ -1,760 +0,0 @@
-From f71d6bcc11dd4cdf0e0ebe7e4d4419174406b2ee Mon Sep 17 00:00:00 2001
-From: Chris Park <Chris.Park@amd.com>
-Date: Wed, 2 Dec 2015 11:48:07 -0500
-Subject: [PATCH 0564/1110] drm/amd/dal: Bool to Void on Link Encoder
- Programming
-
-Signed-off-by: Chris Park <Chris.Park@amd.com>
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc.c | 5 +-
- drivers/gpu/drm/amd/dal/dc/core/dc_link.c | 33 +---
- drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c | 48 ++---
- drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c | 18 +-
- .../drm/amd/dal/dc/dce110/dce110_link_encoder.c | 205 +++++++++------------
- .../drm/amd/dal/dc/dce110/dce110_link_encoder.h | 36 +---
- drivers/gpu/drm/amd/dal/dc/inc/core_types.h | 2 +-
- drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h | 8 +-
- drivers/gpu/drm/amd/dal/dc/inc/link_hwss.h | 4 +-
- 9 files changed, 141 insertions(+), 218 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index b7aa85d..e141e99 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -162,10 +162,7 @@ static void init_hw(struct dc *dc)
- * required signal (which may be different from the
- * default signal on connector). */
- struct core_link *link = dc->links[i];
-- if (!dc->hwss.encoder_power_up(link->link_enc)) {
-- dal_error("Failed link encoder power up!\n");
-- return;
-- }
-+ dc->hwss.encoder_power_up(link->link_enc);
- }
-
- dal_bios_parser_set_scratch_acc_mode_change(bp);
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-index 58eac92..d8bf8e9 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-@@ -884,15 +884,12 @@ static enum dc_status enable_link_dp(struct core_stream *stream)
-
- /* get link settings for video mode timing */
- decide_link_settings(stream, &link_settings);
-- status = dp_enable_link_phy(
-+ dp_enable_link_phy(
- stream->sink->link,
- stream->signal,
- stream->stream_enc->id,
- &link_settings);
-
-- if (status == DC_ERROR_UNEXPECTED)
-- return status;
--
- panel_mode = dp_get_panel_mode(link);
- dpcd_configure_panel_mode(link, panel_mode);
-
-@@ -936,20 +933,15 @@ static enum dc_status enable_link_dp_mst(struct core_stream *stream)
- return enable_link_dp(stream);
- }
-
--static enum dc_status enable_link_hdmi(struct core_stream *stream)
-+static void enable_link_hdmi(struct core_stream *stream)
- {
- struct core_link *link = stream->sink->link;
-
-- /* TODO:Need to add missing use cases, reference
-- * dal_hw_sequencer_enable_link_base*/
-- enum dc_status status = DC_OK;
--
- /* enable video output */
- /* here we need to specify that encoder output settings
- * need to be calculated as for the set mode,
- * it will lead to querying dynamic link capabilities
- * which should be done before enable output */
--
- uint32_t normalized_pix_clk = stream->public.timing.pix_clk_khz;
- switch (stream->public.timing.display_color_depth) {
- case COLOR_DEPTH_888:
-@@ -977,20 +969,17 @@ static enum dc_status enable_link_hdmi(struct core_stream *stream)
- (stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK)
- ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR;
-
-- if (!link->ctx->dc->hwss.encoder_enable_output(
-+ link->ctx->dc->hwss.encoder_enable_output(
- stream->sink->link->link_enc,
- &stream->sink->link->cur_link_settings,
- stream->stream_enc->id,
- dal_clock_source_get_id(stream->clock_source),
- stream->signal,
- stream->public.timing.display_color_depth,
-- stream->public.timing.pix_clk_khz))
-- status = DC_ERROR_UNEXPECTED;
-+ stream->public.timing.pix_clk_khz);
-
- if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
- dal_ddc_service_read_scdc_data(link->ddc);
--
-- return status;
- }
-
- /****************************enable_link***********************************/
-@@ -1009,7 +998,8 @@ enum dc_status core_link_enable(struct core_stream *stream)
- case SIGNAL_TYPE_DVI_SINGLE_LINK:
- case SIGNAL_TYPE_DVI_DUAL_LINK:
- case SIGNAL_TYPE_HDMI_TYPE_A:
-- status = enable_link_hdmi(stream);
-+ enable_link_hdmi(stream);
-+ status = DC_OK;
- break;
-
- default:
-@@ -1030,10 +1020,9 @@ enum dc_status core_link_enable(struct core_stream *stream)
- return status;
- }
-
--enum dc_status core_link_disable(struct core_stream *stream)
-+void core_link_disable(struct core_stream *stream)
- {
- /* TODO dp_set_hw_test_pattern */
-- enum dc_status status = DC_OK;
- struct dc *dc = stream->ctx->dc;
-
- /* here we need to specify that encoder output settings
-@@ -1051,12 +1040,8 @@ enum dc_status core_link_disable(struct core_stream *stream)
- stream->sink->link, stream);
- }
- }
--
-- else if (!dc->hwss.encoder_disable_output(
-- stream->sink->link->link_enc, stream->signal))
-- status = DC_ERROR_UNEXPECTED;
--
-- return status;
-+ dc->hwss.encoder_disable_output(
-+ stream->sink->link->link_enc, stream->signal);
- }
-
- enum dc_status dc_link_validate_mode_timing(
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-index 71e6f8c..2852440 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-@@ -1071,32 +1071,34 @@ bool dp_hbr_verify_link_cap(
- skip_video_pattern = true;
- if (cur->link_rate == LINK_RATE_LOW)
- skip_video_pattern = false;
-- if (dp_enable_link_phy(
-+
-+ dp_enable_link_phy(
- link,
- link->public.connector_signal,
- ENGINE_ID_UNKNOWN,
-- cur)) {
-- if (skip_link_training)
-- success = true;
-- else {
-- uint8_t num_retries = 3;
-- uint8_t j;
-- uint8_t delay_between_retries = 10;
-- for (j = 0; j < num_retries; ++j) {
-- success = perform_link_training(
-- link,
-- cur,
-- skip_video_pattern);
--
-- if (success)
-- break;
--
-- dc_service_sleep_in_milliseconds(
-- link->ctx,
-- delay_between_retries);
--
-- delay_between_retries += 10;
-- }
-+ cur);
-+
-+ if (skip_link_training)
-+ success = true;
-+ else {
-+ uint8_t num_retries = 3;
-+ uint8_t j;
-+ uint8_t delay_between_retries = 10;
-+
-+ for (j = 0; j < num_retries; ++j) {
-+ success = perform_link_training(
-+ link,
-+ cur,
-+ skip_video_pattern);
-+
-+ if (success)
-+ break;
-+
-+ dc_service_sleep_in_milliseconds(
-+ link->ctx,
-+ delay_between_retries);
-+
-+ delay_between_retries += 10;
- }
- }
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-index 054b0a3..2913d5c 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-@@ -46,28 +46,22 @@ void dp_receiver_power_ctrl(struct core_link *link, bool on)
- sizeof(state));
- }
-
--enum dc_status dp_enable_link_phy(
-+void dp_enable_link_phy(
- struct core_link *link,
- enum signal_type signal,
- enum engine_id engine,
- const struct link_settings *link_settings)
- {
-- enum dc_status status = DC_OK;
--
-- if (!link->dc->hwss.encoder_enable_output(
-+ link->dc->hwss.encoder_enable_output(
- link->link_enc,
- link_settings,
- engine,
- CLOCK_SOURCE_ID_EXTERNAL,
- signal,
- COLOR_DEPTH_UNDEFINED,
-- 0))
-- status = DC_ERROR_UNEXPECTED;
--
-- if (status == DC_OK)
-- dp_receiver_power_ctrl(link, true);
-+ 0);
-
-- return status;
-+ dp_receiver_power_ctrl(link, true);
- }
-
- void dp_disable_link_phy(struct core_link *link, enum signal_type signal)
-@@ -133,7 +127,7 @@ bool dp_set_hw_training_pattern(
- }
-
-
--bool dp_set_hw_lane_settings(
-+void dp_set_hw_lane_settings(
- struct core_link *link,
- const struct link_training_settings *link_settings)
- {
-@@ -141,8 +135,6 @@ bool dp_set_hw_lane_settings(
-
- /* call Encoder to set lane settings */
- link->ctx->dc->hwss.encoder_dp_set_lane_settings(encoder, link_settings);
--
-- return true;
- }
-
- enum dp_panel_mode dp_get_panel_mode(struct core_link *link)
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-index 3e2ac27..3d902f3 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-@@ -640,7 +640,7 @@ static bool is_panel_powered_on(struct dce110_link_encoder *enc110)
- * @brief
- * eDP only. Control the power of the eDP panel.
- */
--static bool link_encoder_edp_power_control(
-+static void link_encoder_edp_power_control(
- struct dce110_link_encoder *enc110,
- bool power_up)
- {
-@@ -651,7 +651,7 @@ static bool link_encoder_edp_power_control(
- if (dal_graphics_object_id_get_connector_id(enc110->base.connector) !=
- CONNECTOR_ID_EDP) {
- BREAK_TO_DEBUGGER();
-- return false;
-+ return;
- }
-
- if ((power_up && !is_panel_powered_on(enc110)) ||
-@@ -693,8 +693,6 @@ static bool link_encoder_edp_power_control(
- "%s: Skipping Panel Power action: %s\n",
- __func__, (power_up ? "On":"Off"));
- }
--
-- return true;
- }
-
- /*
-@@ -810,7 +808,7 @@ static bool is_panel_backlight_on(struct dce110_link_encoder *enc110)
- * @brief
- * eDP only. Control the backlight of the eDP panel
- */
--static bool link_encoder_edp_backlight_control(
-+static void link_encoder_edp_backlight_control(
- struct dce110_link_encoder *enc110,
- bool enable)
- {
-@@ -820,7 +818,7 @@ static bool link_encoder_edp_backlight_control(
- if (dal_graphics_object_id_get_connector_id(enc110->base.connector)
- != CONNECTOR_ID_EDP) {
- BREAK_TO_DEBUGGER();
-- return false;
-+ return;
- }
-
- if (enable && is_panel_backlight_on(enc110)) {
-@@ -829,7 +827,7 @@ static bool link_encoder_edp_backlight_control(
- LOG_MINOR_HW_TRACE_RESUME_S3,
- "%s: panel already powered up. Do nothing.\n",
- __func__);
-- return true;
-+ return;
- }
-
- if (!enable && !is_panel_powered_on(enc110)) {
-@@ -838,7 +836,7 @@ static bool link_encoder_edp_backlight_control(
- LOG_MINOR_HW_TRACE_RESUME_S3,
- "%s: panel already powered down. Do nothing.\n",
- __func__);
-- return true;
-+ return;
- }
-
- /* Send VBIOS command to control eDP panel backlight */
-@@ -874,8 +872,6 @@ static bool link_encoder_edp_backlight_control(
- dal_bios_parser_transmitter_control(
- dal_adapter_service_get_bios_parser(
- enc110->base.adapter_service), &cntl);
--
-- return true;
- }
-
- static bool is_dig_enabled(const struct dce110_link_encoder *enc110)
-@@ -1289,13 +1285,12 @@ bool dce110_link_encoder_validate_output_with_stream(
- return is_valid;
- }
-
--bool dce110_link_encoder_power_up(
-+void dce110_link_encoder_power_up(
- struct link_encoder *enc)
- {
- struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
- struct dc_context *ctx = enc110->base.ctx;
- struct bp_transmitter_control cntl = { 0 };
--
- enum bp_result result;
-
- cntl.action = TRANSMITTER_CONTROL_INIT;
-@@ -1318,7 +1313,7 @@ bool dce110_link_encoder_power_up(
- "%s: Failed to execute VBIOS command table!\n",
- __func__);
- BREAK_TO_DEBUGGER();
-- return false;
-+ return;
- }
-
- if (enc110->base.connector.id == CONNECTOR_ID_LVDS) {
-@@ -1345,8 +1340,6 @@ bool dce110_link_encoder_power_up(
- * as DIG_FE id even caller pass DIG_FE id.
- * So this routine must be called first. */
- hpd_initialize(enc110);
--
-- return true;
- }
-
- void dce110_link_encoder_setup(
-@@ -1390,52 +1383,93 @@ void dce110_link_encoder_setup(
- dal_write_reg(ctx, addr, value);
- }
-
--bool dce110_link_encoder_enable_tmds_output(
-+/*
-+ * @brief
-+ * Configure digital transmitter and enable both encoder and transmitter
-+ * Actual output will be available after calling unblank()
-+ */
-+void dce110_link_encoder_enable_output(
- struct link_encoder *enc,
-+ const struct link_settings *link_settings,
-+ enum engine_id engine,
- enum clock_source_id clock_source,
-+ enum signal_type signal,
- enum dc_color_depth color_depth,
- uint32_t pixel_clock)
- {
-- return true;
--}
-+ struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
-+ struct dc_context *ctx = enc110->base.ctx;
-+ struct bp_transmitter_control cntl = { 0 };
-+ enum bp_result result;
-
--bool dce110_link_encoder_enable_dual_link_tmds_output(
-- struct link_encoder *enc,
-- enum clock_source_id clock_source,
-- enum dc_color_depth color_depth,
-- uint32_t pixel_clock)
--{
-- return true;
--}
-+ if (enc110->base.connector.id == CONNECTOR_ID_EDP) {
-+ /* power up eDP panel */
-
--/* enables DP PHY output */
--bool dce110_link_encoder_enable_dp_output(
-- struct link_encoder *enc,
-- const struct link_settings *link_settings,
-- enum clock_source_id clock_source)
--{
-- return true;
--}
-+ link_encoder_edp_power_control(enc110, true);
-
--/* enables DP PHY output in MST mode */
--bool dce110_link_encoder_enable_dp_mst_output(
-- struct link_encoder *enc,
-- const struct link_settings *link_settings,
-- enum clock_source_id clock_source)
--{
-- return true;
-+ link_encoder_edp_wait_for_hpd_ready(enc110, true);
-+
-+ /* have to turn off the backlight
-+ * before power down eDP panel
-+ */
-+ link_encoder_edp_backlight_control(enc110, true);
-+ }
-+
-+ /* Enable the PHY */
-+
-+ /* number_of_lanes is used for pixel clock adjust,
-+ * but it's not passed to asic_control.
-+ * We need to set number of lanes manually.
-+ */
-+ if (dc_is_dp_signal(signal))
-+ configure_encoder(enc110, engine, link_settings);
-+
-+ cntl.action = TRANSMITTER_CONTROL_ENABLE;
-+ cntl.engine_id = engine;
-+ cntl.transmitter = enc110->base.transmitter;
-+ cntl.pll_id = clock_source;
-+ cntl.signal = signal;
-+ cntl.lanes_number = link_settings->lane_count;
-+ cntl.hpd_sel = enc110->base.hpd_source;
-+ if (dc_is_dp_signal(signal))
-+ cntl.pixel_clock = link_settings->link_rate
-+ * LINK_RATE_REF_FREQ_IN_KHZ;
-+ else
-+ cntl.pixel_clock = pixel_clock;
-+ cntl.color_depth = color_depth;
-+
-+ if (DELAY_AFTER_PIXEL_FORMAT_CHANGE)
-+ dc_service_sleep_in_milliseconds(
-+ ctx,
-+ DELAY_AFTER_PIXEL_FORMAT_CHANGE);
-+
-+ result = dal_bios_parser_transmitter_control(
-+ dal_adapter_service_get_bios_parser(
-+ enc110->base.adapter_service),
-+ &cntl);
-+
-+ if (result != BP_RESULT_OK) {
-+ dal_logger_write(ctx->logger,
-+ LOG_MAJOR_ERROR,
-+ LOG_MINOR_COMPONENT_ENCODER,
-+ "%s: Failed to execute VBIOS command table!\n",
-+ __func__);
-+ BREAK_TO_DEBUGGER();
-+ }
- }
-
- /*
- * @brief
- * Disable transmitter and its encoder
- */
--bool dce110_link_encoder_disable_output(
-+void dce110_link_encoder_disable_output(
- struct link_encoder *enc,
- enum signal_type signal)
- {
- struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
-+ struct dc_context *ctx = enc110->base.ctx;
- struct bp_transmitter_control cntl = { 0 };
-+ enum bp_result result;
-
- if (enc110->base.connector.id == CONNECTOR_ID_EDP) {
- /* have to turn off the backlight
-@@ -1448,7 +1482,7 @@ bool dce110_link_encoder_disable_output(
- dal_adapter_service_should_optimize(
- enc110->base.adapter_service,
- OF_SKIP_POWER_DOWN_INACTIVE_ENCODER)) {
-- return true;
-+ return;
- }
- /* Power-down RX and disable GPU PHY should be paired.
- * Disabling PHY without powering down RX may cause
-@@ -1467,10 +1501,20 @@ bool dce110_link_encoder_disable_output(
- cntl.signal = signal;
- cntl.connector_obj_id = enc110->base.connector;
-
-- dal_bios_parser_transmitter_control(
-+ result = dal_bios_parser_transmitter_control(
- dal_adapter_service_get_bios_parser(
- enc110->base.adapter_service), &cntl);
-
-+ if (result != BP_RESULT_OK) {
-+ dal_logger_write(ctx->logger,
-+ LOG_MAJOR_ERROR,
-+ LOG_MINOR_COMPONENT_ENCODER,
-+ "%s: Failed to execute VBIOS command table!\n",
-+ __func__);
-+ BREAK_TO_DEBUGGER();
-+ return;
-+ }
-+
- /* disable encoder */
- if (dc_is_dp_signal(signal))
- link_encoder_disable(enc110);
-@@ -1488,11 +1532,9 @@ bool dce110_link_encoder_disable_output(
- * link_encoder_edp_power_control(
- link_enc, false); */
- }
--
-- return true;
- }
-
--bool dce110_link_encoder_dp_set_lane_settings(
-+void dce110_link_encoder_dp_set_lane_settings(
- struct link_encoder *enc,
- const struct link_training_settings *link_settings)
- {
-@@ -1503,7 +1545,7 @@ bool dce110_link_encoder_dp_set_lane_settings(
-
- if (!link_settings) {
- BREAK_TO_DEBUGGER();
-- return false;
-+ return;
- }
-
- cntl.action = TRANSMITTER_CONTROL_SET_VOLTAGE_AND_PREEMPASIS;
-@@ -1540,8 +1582,6 @@ bool dce110_link_encoder_dp_set_lane_settings(
- dal_adapter_service_get_bios_parser(
- enc110->base.adapter_service), &cntl);
- }
--
-- return true;
- }
-
- /* set DP PHY test and training patterns */
-@@ -1850,71 +1890,6 @@ void dce110_link_encoder_set_lcd_backlight_level(
- }
- }
-
--/*
-- * @brief
-- * Configure digital transmitter and enable both encoder and transmitter
-- * Actual output will be available after calling unblank()
-- */
--bool dce110_link_encoder_enable_output(
-- struct link_encoder *enc,
-- const struct link_settings *link_settings,
-- enum engine_id engine,
-- enum clock_source_id clock_source,
-- enum signal_type signal,
-- enum dc_color_depth color_depth,
-- uint32_t pixel_clock)
--{
-- struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
-- struct dc_context *ctx = enc110->base.ctx;
-- struct bp_transmitter_control cntl = { 0 };
--
-- if (enc110->base.connector.id == CONNECTOR_ID_EDP) {
-- /* power up eDP panel */
--
-- link_encoder_edp_power_control(enc110, true);
--
-- link_encoder_edp_wait_for_hpd_ready(enc110, true);
--
-- /* have to turn off the backlight
-- * before power down eDP panel */
-- link_encoder_edp_backlight_control(enc110, true);
-- }
--
-- /* Enable the PHY */
--
-- /* number_of_lanes is used for pixel clock adjust,
-- * but it's not passed to asic_control.
-- * We need to set number of lanes manually. */
-- if (dc_is_dp_signal(signal))
-- configure_encoder(enc110, engine, link_settings);
--
-- cntl.action = TRANSMITTER_CONTROL_ENABLE;
-- cntl.engine_id = engine;
-- cntl.transmitter = enc110->base.transmitter;
-- cntl.pll_id = clock_source;
-- cntl.signal = signal;
-- cntl.lanes_number = link_settings->lane_count;
-- cntl.hpd_sel = enc110->base.hpd_source;
-- if (dc_is_dp_signal(signal))
-- cntl.pixel_clock = link_settings->link_rate
-- * LINK_RATE_REF_FREQ_IN_KHZ;
-- else
-- cntl.pixel_clock = pixel_clock;
-- cntl.color_depth = color_depth;
--
-- if (DELAY_AFTER_PIXEL_FORMAT_CHANGE)
-- dc_service_sleep_in_milliseconds(
-- ctx,
-- DELAY_AFTER_PIXEL_FORMAT_CHANGE);
--
-- dal_bios_parser_transmitter_control(
-- dal_adapter_service_get_bios_parser(
-- enc110->base.adapter_service),
-- &cntl);
--
-- return true;
--}
--
- void dce110_link_encoder_connect_dig_be_to_fe(
- struct link_encoder *enc,
- enum engine_id engine,
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h
-index 334cc1f..820a7b8 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h
-@@ -53,7 +53,7 @@ bool dce110_link_encoder_validate_output_with_stream(
- /****************** HW programming ************************/
-
- /* initialize HW */ /* why do we initialze aux in here? */
--bool dce110_link_encoder_power_up(struct link_encoder *enc);
-+void dce110_link_encoder_power_up(struct link_encoder *enc);
-
- /* program DIG_MODE in DIG_BE */
- /* TODO can this be combined with enable_output? */
-@@ -61,41 +61,13 @@ void dce110_link_encoder_setup(
- struct link_encoder *enc,
- enum signal_type signal);
-
--/* enables TMDS PHY output */
--/* TODO: still need depth or just pass in adjusted pixel clock? */
--bool dce110_link_encoder_enable_tmds_output(
-- struct link_encoder *enc,
-- enum clock_source_id clock_source,
-- enum dc_color_depth color_depth,
-- uint32_t pixel_clock);
--
--/* enables TMDS PHY output */
--/* TODO: still need this or just pass in adjusted pixel clock? */
--bool dce110_link_encoder_enable_dual_link_tmds_output(
-- struct link_encoder *enc,
-- enum clock_source_id clock_source,
-- enum dc_color_depth color_depth,
-- uint32_t pixel_clock);
--
--/* enables DP PHY output */
--bool dce110_link_encoder_enable_dp_output(
-- struct link_encoder *enc,
-- const struct link_settings *link_settings,
-- enum clock_source_id clock_source);
--
--/* enables DP PHY output in MST mode */
--bool dce110_link_encoder_enable_dp_mst_output(
-- struct link_encoder *enc,
-- const struct link_settings *link_settings,
-- enum clock_source_id clock_source);
--
- /* disable PHY output */
--bool dce110_link_encoder_disable_output(
-+void dce110_link_encoder_disable_output(
- struct link_encoder *enc,
- enum signal_type signal);
-
- /* set DP lane settings */
--bool dce110_link_encoder_dp_set_lane_settings(
-+void dce110_link_encoder_dp_set_lane_settings(
- struct link_encoder *enc,
- const struct link_training_settings *link_settings);
-
-@@ -112,7 +84,7 @@ void dce110_link_encoder_set_lcd_backlight_level(
- struct link_encoder *enc,
- uint32_t level);
-
--bool dce110_link_encoder_enable_output(
-+void dce110_link_encoder_enable_output(
- struct link_encoder *enc,
- const struct link_settings *link_settings,
- enum engine_id engine,
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-index ecc1cdc..bea3c36 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-@@ -235,7 +235,7 @@ struct core_link *link_create(const struct link_init_data *init_params);
- void link_destroy(struct core_link **link);
- enum dc_status core_link_enable(struct core_stream *stream);
-
--enum dc_status core_link_disable(struct core_stream *stream);
-+void core_link_disable(struct core_stream *stream);
-
- enum dc_status dc_link_validate_mode_timing(
- const struct core_sink *sink,
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
-index e414021..3114fbd 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
-@@ -90,10 +90,10 @@ struct hw_sequencer_funcs {
-
- void (*encoder_destroy)(struct link_encoder **enc);
-
-- bool (*encoder_power_up)(
-+ void (*encoder_power_up)(
- struct link_encoder *enc);
-
-- bool (*encoder_enable_output)(
-+ void (*encoder_enable_output)(
- struct link_encoder *enc,
- const struct link_settings *link_settings,
- enum engine_id engine,
-@@ -102,7 +102,7 @@ struct hw_sequencer_funcs {
- enum dc_color_depth color_depth,
- uint32_t pixel_clock);
-
-- bool (*encoder_disable_output)(
-+ void (*encoder_disable_output)(
- struct link_encoder *enc,
- enum signal_type signal);
-
-@@ -110,7 +110,7 @@ struct hw_sequencer_funcs {
- struct link_encoder *enc,
- const struct encoder_set_dp_phy_pattern_param *param);
-
-- bool (*encoder_dp_set_lane_settings)(
-+ void (*encoder_dp_set_lane_settings)(
- struct link_encoder *enc,
- const struct link_training_settings *link_settings);
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/link_hwss.h b/drivers/gpu/drm/amd/dal/dc/inc/link_hwss.h
-index c86c942..28d9d04 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/link_hwss.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/link_hwss.h
-@@ -40,7 +40,7 @@ enum dc_status core_link_write_dpcd(
- const uint8_t *data,
- uint32_t size);
-
--enum dc_status dp_enable_link_phy(
-+void dp_enable_link_phy(
- struct core_link *link,
- enum signal_type signal,
- enum engine_id engine,
-@@ -56,7 +56,7 @@ bool dp_set_hw_training_pattern(
- struct core_link *link,
- enum hw_dp_training_pattern pattern);
-
--bool dp_set_hw_lane_settings(
-+void dp_set_hw_lane_settings(
- struct core_link *link,
- const struct link_training_settings *link_settings);
-
---
-2.7.4
-