diff options
Diffstat (limited to 'common/recipes-kernel/linux/files/0537-drm-amdgpu-execution-barrier-after-fence-v2.patch')
| -rw-r--r-- | common/recipes-kernel/linux/files/0537-drm-amdgpu-execution-barrier-after-fence-v2.patch | 52 |
1 files changed, 0 insertions, 52 deletions
diff --git a/common/recipes-kernel/linux/files/0537-drm-amdgpu-execution-barrier-after-fence-v2.patch b/common/recipes-kernel/linux/files/0537-drm-amdgpu-execution-barrier-after-fence-v2.patch deleted file mode 100644 index 8bb1768d..00000000 --- a/common/recipes-kernel/linux/files/0537-drm-amdgpu-execution-barrier-after-fence-v2.patch +++ /dev/null @@ -1,52 +0,0 @@ -From 22c01cc48301f6974868bd4a7b03e29883da1103 Mon Sep 17 00:00:00 2001 -From: Anatoli Antonovitch <anatoli.antonovitch@amd.com> -Date: Thu, 3 Sep 2015 11:13:31 -0400 -Subject: [PATCH 0537/1050] drm/amdgpu: execution barrier after fence v2 -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Insert wait for reg mem after EOP to fix potential issue with vm context switch - -v2: move wait to vm_flush() use equal instead of greater than. - -Signed-off-by: Anatoli Antonovitch <anatoli.antonovitch@amd.com> -Signed-off-by: Christian König <christian.koenig@amd.com> -Reviewed-by: Alex Deucher <alexander.deucher@amd.com> ---- - drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 12 ++++++++++++ - 1 file changed, 12 insertions(+) - -diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c -index 53f0743..0f979ab 100644 ---- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c -+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c -@@ -3965,6 +3965,7 @@ static void gfx_v8_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr, - DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); - amdgpu_ring_write(ring, lower_32_bits(seq)); - amdgpu_ring_write(ring, upper_32_bits(seq)); -+ - } - - /** -@@ -4044,6 +4045,17 @@ static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring, - unsigned vm_id, uint64_t pd_addr) - { - int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX); -+ uint32_t seq = ring->fence_drv.sync_seq[ring->idx]; -+ uint64_t addr = ring->fence_drv.gpu_addr; -+ -+ amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); -+ amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */ -+ WAIT_REG_MEM_FUNCTION(3))); /* equal */ -+ amdgpu_ring_write(ring, addr & 0xfffffffc); -+ amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); -+ amdgpu_ring_write(ring, seq); -+ amdgpu_ring_write(ring, 0xffffffff); -+ amdgpu_ring_write(ring, 4); /* poll interval */ - - amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); - amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | --- -1.9.1 - |