diff options
Diffstat (limited to 'common/recipes-kernel/linux/files/0527-drm-amd-dal-merged-wm-programming-merged-pixel-durat.patch')
| -rw-r--r-- | common/recipes-kernel/linux/files/0527-drm-amd-dal-merged-wm-programming-merged-pixel-durat.patch | 287 |
1 files changed, 287 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/files/0527-drm-amd-dal-merged-wm-programming-merged-pixel-durat.patch b/common/recipes-kernel/linux/files/0527-drm-amd-dal-merged-wm-programming-merged-pixel-durat.patch new file mode 100644 index 00000000..21ef66e6 --- /dev/null +++ b/common/recipes-kernel/linux/files/0527-drm-amd-dal-merged-wm-programming-merged-pixel-durat.patch @@ -0,0 +1,287 @@ +From 8be7639656718aa9aac85d92bcf5f63ca215e641 Mon Sep 17 00:00:00 2001 +From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> +Date: Thu, 26 Nov 2015 12:09:08 -0500 +Subject: [PATCH 0527/1110] drm/amd/dal: merged wm programming, merged pixel + duration with dmif allocation + +Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> +Signed-off-by: Harry Wentland <harry.wentland@amd.com> +Acked-by: Harry Wentland <harry.wentland@amd.com> +--- + .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c | 14 +--- + .../gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c | 82 +++++++++++----------- + .../gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h | 51 ++++++++++---- + 3 files changed, 83 insertions(+), 64 deletions(-) + +diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c +index e631593..cb2e3d0 100644 +--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c ++++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c +@@ -1271,18 +1271,12 @@ static void set_displaymarks( + for (j = 0; j < target->stream_count; j++) { + struct core_stream *stream = target->streams[j]; + +- dce110_mem_input_program_nbp_watermark( ++ dce110_mem_input_program_display_marks( + stream->mi, + context->bw_results +- .nbp_state_change_watermark[total_streams]); +- +- dce110_mem_input_program_stutter_watermark( +- stream->mi, ++ .nbp_state_change_watermark[total_streams], + context->bw_results +- .stutter_exit_watermark[total_streams]); +- +- dce110_mem_input_program_urgency_watermark( +- stream->mi, ++ .stutter_exit_watermark[total_streams], + context->bw_results + .urgent_watermark[total_streams], + stream->public.timing.h_total, +@@ -1600,8 +1594,6 @@ static bool set_plane_config( + PIPE_LOCK_CONTROL_SURFACE, + true); + +- dce110_mem_input_program_pix_dur(mi, dc_crtc_timing->pix_clk_khz); +- + dce110_timing_generator_program_blanking(tg, dc_crtc_timing); + + enable_fe_clock(ctx, controller_idx, true); +diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c +index e84a1ae..e1d7e27 100644 +--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c ++++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c +@@ -467,8 +467,8 @@ bool dce110_mem_input_program_surface_config( + + enable(mem_input110); + program_tiling(mem_input110, &surface->tiling_info, surface->format); +- program_size_and_rotation(mem_input110, +- surface->rotation, &surface->plane_size); ++ program_size_and_rotation( ++ mem_input110, surface->rotation, &surface->plane_size); + program_pixel_format(mem_input110, surface->format); + + return true; +@@ -533,12 +533,11 @@ static void program_urgency_watermark( + dal_write_reg(ctx, urgency_addr, urgency_cntl); + } + +-void dce110_mem_input_program_stutter_watermark( +- struct mem_input *mi, ++void program_stutter_watermark( ++ const struct dc_context *ctx, ++ const uint32_t offset, + struct bw_watermarks marks) + { +- const struct dc_context *ctx = mi->ctx; +- const uint32_t offset = TO_DCE110_MEM_INPUT(mi)->offsets.dmif; + /* register value */ + uint32_t stutter_cntl = 0; + uint32_t wm_mask_cntl = 0; +@@ -599,12 +598,11 @@ void dce110_mem_input_program_stutter_watermark( + dal_write_reg(ctx, stutter_addr, stutter_cntl); + } + +-void dce110_mem_input_program_nbp_watermark( +- struct mem_input *mi, ++void program_nbp_watermark( ++ const struct dc_context *ctx, ++ const uint32_t offset, + struct bw_watermarks marks) + { +- const struct dc_context *ctx = mi->ctx; +- const uint32_t offset = TO_DCE110_MEM_INPUT(mi)->offsets.dmif; + uint32_t value; + uint32_t addr; + /* Write mask to enable reading/writing of watermark set A */ +@@ -692,27 +690,37 @@ void dce110_mem_input_program_safe_display_marks(struct mem_input *mi) + + program_urgency_watermark( + mi->ctx, bm_dce110->offsets.dmif, max_marks, MAX_WATERMARK); +- dce110_mem_input_program_stutter_watermark(mi, max_marks); +- dce110_mem_input_program_nbp_watermark(mi, nbp_marks); ++ program_stutter_watermark(mi->ctx, bm_dce110->offsets.dmif, max_marks); ++ program_nbp_watermark(mi->ctx, bm_dce110->offsets.dmif, nbp_marks); + + } + +-void dce110_mem_input_program_urgency_watermark( +- struct mem_input *mi, +- struct bw_watermarks marks, ++void dce110_mem_input_program_display_marks( ++ struct mem_input *mem_input, ++ struct bw_watermarks nbp, ++ struct bw_watermarks stutter, ++ struct bw_watermarks urgent, + uint32_t h_total, + uint32_t pixel_clk_in_khz, + uint32_t pstate_blackout_duration_ns) + { +- struct dce110_mem_input *bm_dce110 = TO_DCE110_MEM_INPUT(mi); ++ struct dce110_mem_input *bm_dce110 = TO_DCE110_MEM_INPUT(mem_input); + uint32_t total_dest_line_time_ns = 1000000UL * h_total + / pixel_clk_in_khz + pstate_blackout_duration_ns; + + program_urgency_watermark( +- mi->ctx, ++ mem_input->ctx, + bm_dce110->offsets.dmif, +- marks, ++ urgent, + total_dest_line_time_ns); ++ program_nbp_watermark( ++ mem_input->ctx, ++ bm_dce110->offsets.dmif, ++ nbp); ++ program_stutter_watermark( ++ mem_input->ctx, ++ bm_dce110->offsets.dmif, ++ stutter); + } + + static uint32_t get_dmif_switch_time_us(struct dc_crtc_timing *timing) +@@ -770,6 +778,7 @@ void dce110_mem_input_allocate_dmif_buffer( + uint32_t addr = bm110->offsets.pipe + mmPIPE0_DMIF_BUFFER_CONTROL; + uint32_t value; + uint32_t field; ++ uint32_t pix_dur; + + if (bm110->supported_stutter_mode + & STUTTER_MODE_NO_DMIF_BUFFER_ALLOCATION) +@@ -812,6 +821,21 @@ void dce110_mem_input_allocate_dmif_buffer( + "%s: DMIF allocation failed", + __func__); + ++ ++ if (timing->pix_clk_khz != 0) { ++ addr = mmDPG_PIPE_ARBITRATION_CONTROL1 + bm110->offsets.dmif; ++ value = dal_read_reg(mi->ctx, addr); ++ pix_dur = 1000000000ULL / timing->pix_clk_khz; ++ ++ set_reg_field_value( ++ value, ++ pix_dur, ++ DPG_PIPE_ARBITRATION_CONTROL1, ++ PIXEL_DURATION); ++ ++ dal_write_reg(mi->ctx, addr, value); ++ } ++ + /* + * Stella Wong proposed the following change + * +@@ -897,28 +921,6 @@ void dce110_mem_input_deallocate_dmif_buffer( + dal_write_reg(mi->ctx, mmMC_HUB_RDREQ_DMIF_LIMIT, value); + } + +-void dce110_mem_input_program_pix_dur( +- struct mem_input *mi, uint32_t pix_clk_khz) +-{ +- uint64_t pix_dur; +- uint32_t addr = mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1 +- + TO_DCE110_MEM_INPUT(mi)->offsets.dmif; +- uint32_t value = dal_read_reg(mi->ctx, addr); +- +- if (pix_clk_khz == 0) +- return; +- +- pix_dur = 1000000000 / pix_clk_khz; +- +- set_reg_field_value( +- value, +- pix_dur, +- DPG_PIPE_ARBITRATION_CONTROL1, +- PIXEL_DURATION); +- +- dal_write_reg(mi->ctx, addr, value); +-} +- + /*****************************************/ + /* Constructor, Destructor */ + /*****************************************/ +diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h +index 0d23c81..88697be 100644 +--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h ++++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h +@@ -48,39 +48,64 @@ struct mem_input *dce110_mem_input_create( + + void dce110_mem_input_destroy(struct mem_input **mem_input); + ++/* ++ * dce110_mem_input_program_display_marks ++ * ++ * This function will program nbp stutter and urgency watermarks to maximum ++ * safe values ++ */ + void dce110_mem_input_program_safe_display_marks(struct mem_input *mi); + +-void dce110_mem_input_program_nbp_watermark( +- struct mem_input *mem_input, +- struct bw_watermarks marks); +- +-void dce110_mem_input_program_stutter_watermark( +- struct mem_input *mem_input, +- struct bw_watermarks marks); +- +-void dce110_mem_input_program_urgency_watermark( ++/* ++ * dce110_mem_input_program_display_marks ++ * ++ * This function will program nbp stutter and urgency watermarks to minimum ++ * allowable values ++ */ ++void dce110_mem_input_program_display_marks( + struct mem_input *mem_input, +- struct bw_watermarks marks, ++ struct bw_watermarks nbp, ++ struct bw_watermarks stutter, ++ struct bw_watermarks urgent, + uint32_t h_total, + uint32_t pixel_clk_in_khz, + uint32_t pstate_blackout_duration_ns); + ++/* ++ * dce110_mem_input_allocate_dmif_buffer ++ * ++ * This function will allocate a dmif buffer and program required ++ * pixel duration for pipe ++ */ + void dce110_mem_input_allocate_dmif_buffer( + struct mem_input *mem_input, + struct dc_crtc_timing *timing, + uint32_t paths_num); + ++/* ++ * dce110_mem_input_deallocate_dmif_buffer ++ * ++ * This function will deallocate a dmif buffer from pipe ++ */ + void dce110_mem_input_deallocate_dmif_buffer( + struct mem_input *mem_input, uint32_t paths_num); + +-void dce110_mem_input_program_pix_dur( +- struct mem_input *mem_input, uint32_t pix_clk_khz); +- ++/* ++ * dce110_mem_input_program_surface_flip_and_addr ++ * ++ * This function programs hsync/vsync mode and surface address ++ */ + bool dce110_mem_input_program_surface_flip_and_addr( + struct mem_input *mem_input, + const struct dc_plane_address *address, + bool flip_immediate); + ++/* ++ * dce110_mem_input_program_surface_config ++ * ++ * This function will program surface tiling, size, rotation and pixel format ++ * to corresponding dcp registers. ++ */ + bool dce110_mem_input_program_surface_config( + struct mem_input *mem_input, + const struct dc_surface *surface); +-- +2.7.4 + |