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-rw-r--r--common/recipes-kernel/linux/files/0510-drm-amd-dal-Add-dal-display-driver.patch90113
1 files changed, 0 insertions, 90113 deletions
diff --git a/common/recipes-kernel/linux/files/0510-drm-amd-dal-Add-dal-display-driver.patch b/common/recipes-kernel/linux/files/0510-drm-amd-dal-Add-dal-display-driver.patch
deleted file mode 100644
index 1606a1aa..00000000
--- a/common/recipes-kernel/linux/files/0510-drm-amd-dal-Add-dal-display-driver.patch
+++ /dev/null
@@ -1,90113 +0,0 @@
-From 35eea4f1b20ded08fc0d65891163d03238e3adf6 Mon Sep 17 00:00:00 2001
-From: Harry Wentland <harry.wentland@amd.com>
-Date: Wed, 25 Nov 2015 14:45:50 -0500
-Subject: [PATCH 0510/1110] drm/amd/dal: Add dal display driver
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/Kconfig | 39 +
- drivers/gpu/drm/amd/dal/Makefile | 19 +
- .../gpu/drm/amd/dal/dal_power_interface_types.h | 76 +
- drivers/gpu/drm/amd/dal/dal_services.h | 266 ++
- drivers/gpu/drm/amd/dal/dal_services_types.h | 62 +
- drivers/gpu/drm/amd/dal/dc/Makefile | 24 +
- drivers/gpu/drm/amd/dal/dc/adapter/Makefile | 18 +
- .../gpu/drm/amd/dal/dc/adapter/adapter_service.c | 2037 +++++++++
- .../gpu/drm/amd/dal/dc/adapter/adapter_service.h | 67 +
- .../adapter/dce110/hw_ctx_adapter_service_dce110.c | 303 ++
- .../adapter/dce110/hw_ctx_adapter_service_dce110.h | 40 +
- .../amd/dal/dc/adapter/hw_ctx_adapter_service.c | 164 +
- .../amd/dal/dc/adapter/hw_ctx_adapter_service.h | 86 +
- .../drm/amd/dal/dc/adapter/wireless_data_source.c | 209 +
- .../drm/amd/dal/dc/adapter/wireless_data_source.h | 80 +
- .../gpu/drm/amd/dal/dc/asic_capability/Makefile | 23 +
- .../amd/dal/dc/asic_capability/asic_capability.c | 178 +
- .../dc/asic_capability/carrizo_asic_capability.c | 146 +
- .../dc/asic_capability/carrizo_asic_capability.h | 36 +
- drivers/gpu/drm/amd/dal/dc/audio/Makefile | 22 +
- drivers/gpu/drm/amd/dal/dc/audio/audio.h | 195 +
- drivers/gpu/drm/amd/dal/dc/audio/audio_base.c | 463 ++
- .../gpu/drm/amd/dal/dc/audio/dce110/audio_dce110.c | 452 ++
- .../gpu/drm/amd/dal/dc/audio/dce110/audio_dce110.h | 42 +
- .../amd/dal/dc/audio/dce110/hw_ctx_audio_dce110.c | 1929 ++++++++
- .../amd/dal/dc/audio/dce110/hw_ctx_audio_dce110.h | 47 +
- drivers/gpu/drm/amd/dal/dc/audio/hw_ctx_audio.c | 771 ++++
- drivers/gpu/drm/amd/dal/dc/audio/hw_ctx_audio.h | 285 ++
- drivers/gpu/drm/amd/dal/dc/basics/Makefile | 10 +
- drivers/gpu/drm/amd/dal/dc/basics/conversion.c | 223 +
- drivers/gpu/drm/amd/dal/dc/basics/conversion.h | 49 +
- drivers/gpu/drm/amd/dal/dc/basics/fixpt31_32.c | 692 +++
- drivers/gpu/drm/amd/dal/dc/basics/fixpt32_32.c | 223 +
- drivers/gpu/drm/amd/dal/dc/basics/grph_object_id.c | 135 +
- drivers/gpu/drm/amd/dal/dc/basics/logger.c | 947 ++++
- drivers/gpu/drm/amd/dal/dc/basics/logger.h | 64 +
- .../gpu/drm/amd/dal/dc/basics/register_logger.c | 197 +
- drivers/gpu/drm/amd/dal/dc/basics/signal_types.c | 116 +
- drivers/gpu/drm/amd/dal/dc/basics/vector.c | 309 ++
- drivers/gpu/drm/amd/dal/dc/bios/Makefile | 27 +
- drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c | 4758 ++++++++++++++++++++
- drivers/gpu/drm/amd/dal/dc/bios/bios_parser.h | 78 +
- .../gpu/drm/amd/dal/dc/bios/bios_parser_helper.c | 193 +
- .../gpu/drm/amd/dal/dc/bios/bios_parser_helper.h | 108 +
- drivers/gpu/drm/amd/dal/dc/bios/command_table.c | 2616 +++++++++++
- drivers/gpu/drm/amd/dal/dc/bios/command_table.h | 117 +
- .../gpu/drm/amd/dal/dc/bios/command_table_helper.c | 315 ++
- .../gpu/drm/amd/dal/dc/bios/command_table_helper.h | 87 +
- .../dal/dc/bios/dce110/bios_parser_helper_dce110.c | 484 ++
- .../dal/dc/bios/dce110/bios_parser_helper_dce110.h | 34 +
- .../dc/bios/dce110/command_table_helper_dce110.c | 369 ++
- .../dc/bios/dce110/command_table_helper_dce110.h | 34 +
- drivers/gpu/drm/amd/dal/dc/calcs/Makefile | 10 +
- drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c | 3478 ++++++++++++++
- drivers/gpu/drm/amd/dal/dc/calcs/bw_fixed.c | 278 ++
- drivers/gpu/drm/amd/dal/dc/calcs/scaler_filter.c | 1992 ++++++++
- drivers/gpu/drm/amd/dal/dc/calcs/scaler_filter.h | 74 +
- drivers/gpu/drm/amd/dal/dc/connector/Makefile | 10 +
- drivers/gpu/drm/amd/dal/dc/connector/connector.h | 39 +
- .../gpu/drm/amd/dal/dc/connector/connector_base.c | 421 ++
- .../drm/amd/dal/dc/connector/connector_signals.c | 204 +
- drivers/gpu/drm/amd/dal/dc/core/dc.c | 849 ++++
- drivers/gpu/drm/amd/dal/dc/core/dc_hw_sequencer.c | 49 +
- drivers/gpu/drm/amd/dal/dc/core/dc_link.c | 1081 +++++
- drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c | 1689 +++++++
- drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c | 188 +
- drivers/gpu/drm/amd/dal/dc/core/dc_resource.c | 378 ++
- drivers/gpu/drm/amd/dal/dc/core/dc_sink.c | 118 +
- drivers/gpu/drm/amd/dal/dc/core/dc_stream.c | 172 +
- drivers/gpu/drm/amd/dal/dc/core/dc_surface.c | 124 +
- drivers/gpu/drm/amd/dal/dc/core/dc_target.c | 473 ++
- drivers/gpu/drm/amd/dal/dc/dc.h | 440 ++
- drivers/gpu/drm/amd/dal/dc/dc_helpers.h | 75 +
- drivers/gpu/drm/amd/dal/dc/dc_services.h | 174 +
- drivers/gpu/drm/amd/dal/dc/dc_temp.h | 508 +++
- drivers/gpu/drm/amd/dal/dc/dc_types.h | 677 +++
- drivers/gpu/drm/amd/dal/dc/dce110/Makefile | 33 +
- .../gpu/drm/amd/dal/dc/dce110/dce110_compressor.c | 886 ++++
- .../gpu/drm/amd/dal/dc/dce110/dce110_compressor.h | 84 +
- .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c | 1825 ++++++++
- .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.h | 36 +
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.c | 85 +
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.h | 90 +
- .../gpu/drm/amd/dal/dc/dce110/dce110_ipp_cursor.c | 256 ++
- .../gpu/drm/amd/dal/dc/dce110/dce110_ipp_gamma.c | 877 ++++
- .../drm/amd/dal/dc/dce110/dce110_link_encoder.c | 2049 +++++++++
- .../drm/amd/dal/dc/dce110/dce110_link_encoder.h | 91 +
- .../gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c | 969 ++++
- .../gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h | 88 +
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c | 296 ++
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.h | 140 +
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_csc.c | 904 ++++
- .../drm/amd/dal/dc/dce110/dce110_opp_formatter.c | 610 +++
- .../gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma.c | 2473 ++++++++++
- .../gpu/drm/amd/dal/dc/dce110/dce110_resource.c | 1276 ++++++
- .../gpu/drm/amd/dal/dc/dce110/dce110_resource.h | 55 +
- .../drm/amd/dal/dc/dce110/dce110_stream_encoder.c | 1168 +++++
- .../drm/amd/dal/dc/dce110/dce110_stream_encoder.h | 64 +
- .../amd/dal/dc/dce110/dce110_timing_generator.c | 1878 ++++++++
- .../amd/dal/dc/dce110/dce110_timing_generator.h | 178 +
- .../gpu/drm/amd/dal/dc/dce110/dce110_transform.c | 116 +
- .../gpu/drm/amd/dal/dc/dce110/dce110_transform.h | 91 +
- .../amd/dal/dc/dce110/dce110_transform_bit_depth.c | 840 ++++
- .../amd/dal/dc/dce110/dce110_transform_bit_depth.h | 51 +
- .../drm/amd/dal/dc/dce110/dce110_transform_gamut.c | 297 ++
- .../drm/amd/dal/dc/dce110/dce110_transform_scl.c | 818 ++++
- .../drm/amd/dal/dc/dce110/dce110_transform_sclv.c | 531 +++
- drivers/gpu/drm/amd/dal/dc/dcs/Makefile | 10 +
- drivers/gpu/drm/amd/dal/dc/dcs/ddc_i2caux_helper.c | 159 +
- drivers/gpu/drm/amd/dal/dc/dcs/ddc_i2caux_helper.h | 60 +
- drivers/gpu/drm/amd/dal/dc/dcs/ddc_service.c | 1034 +++++
- drivers/gpu/drm/amd/dal/dc/dcs/ddc_service.h | 38 +
- drivers/gpu/drm/amd/dal/dc/gpio/Makefile | 24 +
- .../gpu/drm/amd/dal/dc/gpio/dce110/hw_ddc_dce110.c | 883 ++++
- .../gpu/drm/amd/dal/dc/gpio/dce110/hw_ddc_dce110.h | 46 +
- .../drm/amd/dal/dc/gpio/dce110/hw_factory_dce110.c | 84 +
- .../drm/amd/dal/dc/gpio/dce110/hw_factory_dce110.h | 32 +
- .../gpu/drm/amd/dal/dc/gpio/dce110/hw_hpd_dce110.c | 367 ++
- .../gpu/drm/amd/dal/dc/gpio/dce110/hw_hpd_dce110.h | 47 +
- .../amd/dal/dc/gpio/dce110/hw_translate_dce110.c | 440 ++
- .../amd/dal/dc/gpio/dce110/hw_translate_dce110.h | 34 +
- drivers/gpu/drm/amd/dal/dc/gpio/ddc.c | 290 ++
- drivers/gpu/drm/amd/dal/dc/gpio/ddc.h | 45 +
- drivers/gpu/drm/amd/dal/dc/gpio/dvo.c | 138 +
- drivers/gpu/drm/amd/dal/dc/gpio/dvo.h | 42 +
- drivers/gpu/drm/amd/dal/dc/gpio/gpio.h | 48 +
- drivers/gpu/drm/amd/dal/dc/gpio/gpio_base.c | 279 ++
- drivers/gpu/drm/amd/dal/dc/gpio/gpio_service.c | 470 ++
- drivers/gpu/drm/amd/dal/dc/gpio/gpio_service.h | 57 +
- drivers/gpu/drm/amd/dal/dc/gpio/hw_ddc.c | 105 +
- drivers/gpu/drm/amd/dal/dc/gpio/hw_ddc.h | 60 +
- drivers/gpu/drm/amd/dal/dc/gpio/hw_dvo.c | 318 ++
- drivers/gpu/drm/amd/dal/dc/gpio/hw_dvo.h | 89 +
- drivers/gpu/drm/amd/dal/dc/gpio/hw_factory.c | 80 +
- drivers/gpu/drm/amd/dal/dc/gpio/hw_factory.h | 74 +
- drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio.c | 408 ++
- drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio.h | 129 +
- drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio_pad.c | 93 +
- drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio_pad.h | 47 +
- drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio_pin.c | 86 +
- drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio_pin.h | 79 +
- drivers/gpu/drm/amd/dal/dc/gpio/hw_hpd.c | 88 +
- drivers/gpu/drm/amd/dal/dc/gpio/hw_hpd.h | 45 +
- drivers/gpu/drm/amd/dal/dc/gpio/hw_translate.c | 67 +
- drivers/gpu/drm/amd/dal/dc/gpio/hw_translate.h | 49 +
- drivers/gpu/drm/amd/dal/dc/gpio/irq.c | 181 +
- drivers/gpu/drm/amd/dal/dc/gpio/irq.h | 42 +
- drivers/gpu/drm/amd/dal/dc/gpu/Makefile | 26 +
- .../gpu/drm/amd/dal/dc/gpu/calc_pll_clock_source.c | 407 ++
- .../gpu/drm/amd/dal/dc/gpu/calc_pll_clock_source.h | 79 +
- drivers/gpu/drm/amd/dal/dc/gpu/clock_source.c | 649 +++
- drivers/gpu/drm/amd/dal/dc/gpu/clock_source.h | 136 +
- .../gpu/drm/amd/dal/dc/gpu/dc_clock_generator.c | 92 +
- .../gpu/drm/amd/dal/dc/gpu/dc_clock_generator.h | 63 +
- .../amd/dal/dc/gpu/dce110/dc_clock_gating_dce110.c | 90 +
- .../amd/dal/dc/gpu/dce110/dc_clock_gating_dce110.h | 33 +
- .../amd/dal/dc/gpu/dce110/display_clock_dce110.c | 958 ++++
- .../amd/dal/dc/gpu/dce110/display_clock_dce110.h | 53 +
- .../dal/dc/gpu/dce110/ext_clock_source_dce110.c | 383 ++
- .../dal/dc/gpu/dce110/ext_clock_source_dce110.h | 38 +
- .../dal/dc/gpu/dce110/pll_clock_source_dce110.c | 718 +++
- .../dal/dc/gpu/dce110/pll_clock_source_dce110.h | 55 +
- .../dal/dc/gpu/dce110/vce_clock_source_dce110.c | 193 +
- .../dal/dc/gpu/dce110/vce_clock_source_dce110.h | 32 +
- drivers/gpu/drm/amd/dal/dc/gpu/display_clock.c | 204 +
- drivers/gpu/drm/amd/dal/dc/gpu/display_clock.h | 82 +
- drivers/gpu/drm/amd/dal/dc/gpu/divider_range.c | 127 +
- drivers/gpu/drm/amd/dal/dc/gpu/divider_range.h | 63 +
- drivers/gpu/drm/amd/dal/dc/gpu/ext_clock_source.c | 119 +
- drivers/gpu/drm/amd/dal/dc/gpu/ext_clock_source.h | 47 +
- drivers/gpu/drm/amd/dal/dc/gpu/pll_clock_source.c | 141 +
- drivers/gpu/drm/amd/dal/dc/gpu/pll_clock_source.h | 52 +
- drivers/gpu/drm/amd/dal/dc/i2caux/Makefile | 23 +
- drivers/gpu/drm/amd/dal/dc/i2caux/aux_engine.c | 568 +++
- drivers/gpu/drm/amd/dal/dc/i2caux/aux_engine.h | 119 +
- .../amd/dal/dc/i2caux/dce110/aux_engine_dce110.c | 789 ++++
- .../amd/dal/dc/i2caux/dce110/aux_engine_dce110.h | 56 +
- .../i2caux/dce110/i2c_generic_hw_engine_dce110.h | 25 +
- .../dal/dc/i2caux/dce110/i2c_hw_engine_dce110.c | 954 ++++
- .../dal/dc/i2caux/dce110/i2c_hw_engine_dce110.h | 58 +
- .../dal/dc/i2caux/dce110/i2c_sw_engine_dce110.c | 172 +
- .../dal/dc/i2caux/dce110/i2c_sw_engine_dce110.h | 43 +
- .../drm/amd/dal/dc/i2caux/dce110/i2caux_dce110.c | 260 ++
- .../drm/amd/dal/dc/i2caux/dce110/i2caux_dce110.h | 39 +
- drivers/gpu/drm/amd/dal/dc/i2caux/engine.h | 129 +
- drivers/gpu/drm/amd/dal/dc/i2caux/engine_base.c | 68 +
- drivers/gpu/drm/amd/dal/dc/i2caux/i2c_engine.c | 122 +
- drivers/gpu/drm/amd/dal/dc/i2caux/i2c_engine.h | 113 +
- .../drm/amd/dal/dc/i2caux/i2c_generic_hw_engine.c | 287 ++
- .../drm/amd/dal/dc/i2caux/i2c_generic_hw_engine.h | 77 +
- drivers/gpu/drm/amd/dal/dc/i2caux/i2c_hw_engine.c | 247 +
- drivers/gpu/drm/amd/dal/dc/i2caux/i2c_hw_engine.h | 80 +
- drivers/gpu/drm/amd/dal/dc/i2caux/i2c_sw_engine.c | 615 +++
- drivers/gpu/drm/amd/dal/dc/i2caux/i2c_sw_engine.h | 81 +
- drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.c | 519 +++
- drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.h | 123 +
- drivers/gpu/drm/amd/dal/dc/inc/bandwidth_calcs.h | 463 ++
- drivers/gpu/drm/amd/dal/dc/inc/bw_fixed.h | 60 +
- drivers/gpu/drm/amd/dal/dc/inc/compressor.h | 140 +
- drivers/gpu/drm/amd/dal/dc/inc/core_dc.h | 39 +
- drivers/gpu/drm/amd/dal/dc/inc/core_status.h | 46 +
- drivers/gpu/drm/amd/dal/dc/inc/core_types.h | 308 ++
- drivers/gpu/drm/amd/dal/dc/inc/dc_link_dp.h | 51 +
- drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h | 170 +
- drivers/gpu/drm/amd/dal/dc/inc/ipp.h | 66 +
- drivers/gpu/drm/amd/dal/dc/inc/link_hwss.h | 67 +
- drivers/gpu/drm/amd/dal/dc/inc/mem_input.h | 55 +
- drivers/gpu/drm/amd/dal/dc/inc/opp.h | 206 +
- drivers/gpu/drm/amd/dal/dc/inc/resource.h | 61 +
- drivers/gpu/drm/amd/dal/dc/inc/transform.h | 81 +
- drivers/gpu/drm/amd/dal/dc/irq/Makefile | 21 +
- .../drm/amd/dal/dc/irq/dce110/irq_service_dce110.c | 389 ++
- .../drm/amd/dal/dc/irq/dce110/irq_service_dce110.h | 34 +
- drivers/gpu/drm/amd/dal/dc/irq/irq_service.c | 173 +
- drivers/gpu/drm/amd/dal/dc/irq/irq_service.h | 85 +
- drivers/gpu/drm/amd/dal/dc/irq_types.h | 199 +
- .../amd/dal/include/adapter_service_interface.h | 628 +++
- .../drm/amd/dal/include/adapter_service_types.h | 70 +
- .../gpu/drm/amd/dal/include/adjustment_interface.h | 230 +
- drivers/gpu/drm/amd/dal/include/adjustment_types.h | 420 ++
- .../amd/dal/include/asic_capability_interface.h | 58 +
- .../drm/amd/dal/include/asic_capability_types.h | 134 +
- drivers/gpu/drm/amd/dal/include/audio_interface.h | 184 +
- drivers/gpu/drm/amd/dal/include/audio_types.h | 275 ++
- .../drm/amd/dal/include/bios_parser_interface.h | 294 ++
- .../gpu/drm/amd/dal/include/bios_parser_types.h | 305 ++
- drivers/gpu/drm/amd/dal/include/bit_set.h | 61 +
- .../drm/amd/dal/include/clock_source_interface.h | 89 +
- .../gpu/drm/amd/dal/include/clock_source_types.h | 118 +
- .../gpu/drm/amd/dal/include/connector_interface.h | 82 +
- drivers/gpu/drm/amd/dal/include/dal_asic_id.h | 106 +
- .../gpu/drm/amd/dal/include/dal_register_logger.h | 43 +
- drivers/gpu/drm/amd/dal/include/dal_types.h | 292 ++
- .../amd/dal/include/dc_clock_generator_interface.h | 77 +
- drivers/gpu/drm/amd/dal/include/dcs_interface.h | 351 ++
- drivers/gpu/drm/amd/dal/include/dcs_types.h | 742 +++
- drivers/gpu/drm/amd/dal/include/ddc_interface.h | 74 +
- .../drm/amd/dal/include/ddc_service_interface.h | 100 +
- .../gpu/drm/amd/dal/include/ddc_service_types.h | 220 +
- .../amd/dal/include/default_mode_list_interface.h | 37 +
- .../drm/amd/dal/include/display_clock_interface.h | 189 +
- .../drm/amd/dal/include/display_path_interface.h | 436 ++
- .../gpu/drm/amd/dal/include/display_path_types.h | 132 +
- .../amd/dal/include/display_service_interface.h | 165 +
- .../drm/amd/dal/include/display_service_types.h | 167 +
- drivers/gpu/drm/amd/dal/include/dmcu_interface.h | 87 +
- drivers/gpu/drm/amd/dal/include/dmcu_types.h | 199 +
- .../dal/include/dpcd_access_service_interface.h | 65 +
- drivers/gpu/drm/amd/dal/include/dpcd_defs.h | 869 ++++
- drivers/gpu/drm/amd/dal/include/dvo_interface.h | 48 +
- .../gpu/drm/amd/dal/include/encoder_interface.h | 278 ++
- drivers/gpu/drm/amd/dal/include/encoder_types.h | 216 +
- drivers/gpu/drm/amd/dal/include/fixed31_32.h | 389 ++
- drivers/gpu/drm/amd/dal/include/fixed32_32.h | 80 +
- drivers/gpu/drm/amd/dal/include/gpio_interface.h | 93 +
- .../drm/amd/dal/include/gpio_service_interface.h | 94 +
- drivers/gpu/drm/amd/dal/include/gpio_types.h | 393 ++
- drivers/gpu/drm/amd/dal/include/gpu_clock_info.h | 43 +
- drivers/gpu/drm/amd/dal/include/gpu_interface.h | 91 +
- drivers/gpu/drm/amd/dal/include/grph_csc_types.h | 98 +
- .../drm/amd/dal/include/grph_object_ctrl_defs.h | 598 +++
- drivers/gpu/drm/amd/dal/include/grph_object_defs.h | 328 ++
- drivers/gpu/drm/amd/dal/include/grph_object_id.h | 285 ++
- .../gpu/drm/amd/dal/include/hw_adjustment_set.h | 50 +
- .../gpu/drm/amd/dal/include/hw_adjustment_types.h | 205 +
- .../amd/dal/include/hw_path_mode_set_interface.h | 48 +
- .../drm/amd/dal/include/hw_sequencer_interface.h | 388 ++
- .../gpu/drm/amd/dal/include/hw_sequencer_types.h | 305 ++
- drivers/gpu/drm/amd/dal/include/i2caux_interface.h | 127 +
- drivers/gpu/drm/amd/dal/include/irq_interface.h | 53 +
- .../drm/amd/dal/include/irq_service_interface.h | 55 +
- drivers/gpu/drm/amd/dal/include/isr_config_types.h | 157 +
- .../gpu/drm/amd/dal/include/link_encoder_types.h | 32 +
- .../drm/amd/dal/include/link_service_interface.h | 202 +
- .../gpu/drm/amd/dal/include/link_service_types.h | 428 ++
- drivers/gpu/drm/amd/dal/include/logger_interface.h | 153 +
- drivers/gpu/drm/amd/dal/include/logger_types.h | 356 ++
- .../gpu/drm/amd/dal/include/mode_manager_types.h | 71 +
- .../gpu/drm/amd/dal/include/mode_query_interface.h | 93 +
- .../amd/dal/include/mode_timing_list_interface.h | 51 +
- .../gpu/drm/amd/dal/include/overlay_interface.h | 137 +
- drivers/gpu/drm/amd/dal/include/overlay_types.h | 164 +
- .../drm/amd/dal/include/path_mode_set_interface.h | 107 +
- drivers/gpu/drm/amd/dal/include/plane_types.h | 309 ++
- drivers/gpu/drm/amd/dal/include/scaler_types.h | 196 +
- .../amd/dal/include/set_mode_params_interface.h | 101 +
- drivers/gpu/drm/amd/dal/include/set_mode_types.h | 285 ++
- drivers/gpu/drm/amd/dal/include/signal_types.h | 58 +
- .../gpu/drm/amd/dal/include/stream_encoder_types.h | 16 +
- .../drm/amd/dal/include/timing_generator_types.h | 150 +
- .../amd/dal/include/timing_list_query_interface.h | 69 +
- drivers/gpu/drm/amd/dal/include/vector.h | 150 +
- drivers/gpu/drm/amd/dal/include/video_csc_types.h | 135 +
- .../gpu/drm/amd/dal/include/video_gamma_types.h | 56 +
- 294 files changed, 87748 insertions(+)
- create mode 100644 drivers/gpu/drm/amd/dal/Kconfig
- create mode 100644 drivers/gpu/drm/amd/dal/Makefile
- create mode 100644 drivers/gpu/drm/amd/dal/dal_power_interface_types.h
- create mode 100644 drivers/gpu/drm/amd/dal/dal_services.h
- create mode 100644 drivers/gpu/drm/amd/dal/dal_services_types.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/Makefile
- create mode 100644 drivers/gpu/drm/amd/dal/dc/adapter/Makefile
- create mode 100644 drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/adapter/dce110/hw_ctx_adapter_service_dce110.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/adapter/dce110/hw_ctx_adapter_service_dce110.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/adapter/hw_ctx_adapter_service.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/adapter/hw_ctx_adapter_service.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/adapter/wireless_data_source.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/adapter/wireless_data_source.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/asic_capability/Makefile
- create mode 100644 drivers/gpu/drm/amd/dal/dc/asic_capability/asic_capability.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/asic_capability/carrizo_asic_capability.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/asic_capability/carrizo_asic_capability.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/audio/Makefile
- create mode 100644 drivers/gpu/drm/amd/dal/dc/audio/audio.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/audio/audio_base.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/audio/dce110/audio_dce110.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/audio/dce110/audio_dce110.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/audio/dce110/hw_ctx_audio_dce110.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/audio/dce110/hw_ctx_audio_dce110.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/audio/hw_ctx_audio.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/audio/hw_ctx_audio.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/basics/Makefile
- create mode 100644 drivers/gpu/drm/amd/dal/dc/basics/conversion.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/basics/conversion.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/basics/fixpt31_32.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/basics/fixpt32_32.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/basics/grph_object_id.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/basics/logger.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/basics/logger.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/basics/register_logger.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/basics/signal_types.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/basics/vector.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/bios/Makefile
- create mode 100644 drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/bios/bios_parser.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/bios/command_table.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/bios/command_table.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/bios/command_table_helper.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/bios/command_table_helper.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/bios/dce110/bios_parser_helper_dce110.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/bios/dce110/bios_parser_helper_dce110.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/bios/dce110/command_table_helper_dce110.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/bios/dce110/command_table_helper_dce110.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/calcs/Makefile
- create mode 100644 drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/calcs/bw_fixed.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/calcs/scaler_filter.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/calcs/scaler_filter.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/connector/Makefile
- create mode 100644 drivers/gpu/drm/amd/dal/dc/connector/connector.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/connector/connector_base.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/connector/connector_signals.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/core/dc.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/core/dc_hw_sequencer.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/core/dc_link.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/core/dc_sink.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/core/dc_stream.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/core/dc_surface.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/core/dc_target.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dc.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dc_helpers.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dc_services.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dc_temp.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dc_types.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/Makefile
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_compressor.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_compressor.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp_cursor.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp_gamma.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_csc.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_formatter.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_bit_depth.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_bit_depth.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_gamut.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_scl.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_sclv.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dcs/Makefile
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dcs/ddc_i2caux_helper.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dcs/ddc_i2caux_helper.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dcs/ddc_service.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dcs/ddc_service.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/Makefile
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_ddc_dce110.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_ddc_dce110.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_factory_dce110.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_factory_dce110.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_hpd_dce110.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_hpd_dce110.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_translate_dce110.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_translate_dce110.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/ddc.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/ddc.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/dvo.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/dvo.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/gpio.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/gpio_base.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/gpio_service.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/gpio_service.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/hw_ddc.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/hw_ddc.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/hw_dvo.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/hw_dvo.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/hw_factory.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/hw_factory.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio_pad.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio_pad.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio_pin.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio_pin.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/hw_hpd.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/hw_hpd.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/hw_translate.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/hw_translate.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/irq.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/irq.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/Makefile
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/calc_pll_clock_source.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/calc_pll_clock_source.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/clock_source.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/clock_source.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/dc_clock_generator.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/dc_clock_generator.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/dce110/dc_clock_gating_dce110.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/dce110/dc_clock_gating_dce110.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/dce110/ext_clock_source_dce110.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/dce110/ext_clock_source_dce110.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/dce110/pll_clock_source_dce110.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/dce110/pll_clock_source_dce110.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/dce110/vce_clock_source_dce110.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/dce110/vce_clock_source_dce110.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/display_clock.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/display_clock.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/divider_range.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/divider_range.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/ext_clock_source.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/ext_clock_source.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/pll_clock_source.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/pll_clock_source.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/Makefile
- create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/aux_engine.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/aux_engine.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/dce110/aux_engine_dce110.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/dce110/aux_engine_dce110.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_generic_hw_engine_dce110.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_hw_engine_dce110.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_hw_engine_dce110.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_sw_engine_dce110.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_sw_engine_dce110.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2caux_dce110.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2caux_dce110.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/engine.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/engine_base.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/i2c_engine.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/i2c_engine.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/i2c_generic_hw_engine.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/i2c_generic_hw_engine.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/i2c_hw_engine.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/i2c_hw_engine.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/i2c_sw_engine.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/i2c_sw_engine.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/inc/bandwidth_calcs.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/inc/bw_fixed.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/inc/compressor.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/inc/core_dc.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/inc/core_status.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/inc/core_types.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/inc/dc_link_dp.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/inc/ipp.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/inc/link_hwss.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/inc/mem_input.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/inc/opp.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/inc/resource.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/inc/transform.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/irq/Makefile
- create mode 100644 drivers/gpu/drm/amd/dal/dc/irq/dce110/irq_service_dce110.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/irq/dce110/irq_service_dce110.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/irq/irq_service.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/irq/irq_service.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/irq_types.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/adapter_service_interface.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/adapter_service_types.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/adjustment_interface.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/adjustment_types.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/asic_capability_interface.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/asic_capability_types.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/audio_interface.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/audio_types.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/bios_parser_interface.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/bios_parser_types.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/bit_set.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/clock_source_interface.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/clock_source_types.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/connector_interface.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/dal_asic_id.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/dal_register_logger.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/dal_types.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/dc_clock_generator_interface.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/dcs_interface.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/dcs_types.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/ddc_interface.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/ddc_service_interface.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/ddc_service_types.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/default_mode_list_interface.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/display_clock_interface.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/display_path_interface.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/display_path_types.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/display_service_interface.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/display_service_types.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/dmcu_interface.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/dmcu_types.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/dpcd_access_service_interface.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/dpcd_defs.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/dvo_interface.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/encoder_interface.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/encoder_types.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/fixed31_32.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/fixed32_32.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/gpio_interface.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/gpio_service_interface.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/gpio_types.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/gpu_clock_info.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/gpu_interface.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/grph_csc_types.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/grph_object_ctrl_defs.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/grph_object_defs.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/grph_object_id.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/hw_adjustment_set.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/hw_adjustment_types.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/hw_path_mode_set_interface.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/hw_sequencer_interface.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/hw_sequencer_types.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/i2caux_interface.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/irq_interface.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/irq_service_interface.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/isr_config_types.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/link_encoder_types.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/link_service_interface.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/link_service_types.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/logger_interface.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/logger_types.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/mode_manager_types.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/mode_query_interface.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/mode_timing_list_interface.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/overlay_interface.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/overlay_types.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/path_mode_set_interface.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/plane_types.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/scaler_types.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/set_mode_params_interface.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/set_mode_types.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/signal_types.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/stream_encoder_types.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/timing_generator_types.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/timing_list_query_interface.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/vector.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/video_csc_types.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/video_gamma_types.h
-
-diff --git a/drivers/gpu/drm/amd/dal/Kconfig b/drivers/gpu/drm/amd/dal/Kconfig
-new file mode 100644
-index 0000000..14df02e
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/Kconfig
-@@ -0,0 +1,39 @@
-+menu "Display Engine Configuration"
-+ depends on DRM && (DRM_AMDSOC || DRM_AMDGPU)
-+
-+config DRM_AMD_DAL
-+ bool "AMD DAL - Enable new display engine (will be deprecated when the development is done)"
-+ help
-+ Choose this option if you want to use the new display engine
-+ support for AMD SOC.
-+
-+ Will be deprecated when the DAL component becomes stable and
-+ AMDSOC will fully switch to it.
-+
-+config DRM_AMD_DAL_VBIOS_PRESENT
-+ bool "Video Bios available on board"
-+ depends on DRM_AMD_DAL
-+ help
-+ This option is needed to allow a full range of feature
-+ support when working on
-+ x86 platforms and there is a VBIOS
-+ present in the system
-+
-+config DRM_AMD_DAL_DCE11_0
-+ bool "Carrizo family"
-+ depends on DRM_AMD_DAL
-+ help
-+ Choose this option
-+ if you want to have
-+ CZ family
-+ for display engine
-+
-+config DEBUG_KERNEL_DAL
-+ bool "Enable kgdb break in DAL"
-+ depends on DRM_AMD_DAL
-+ help
-+ Choose this option
-+ if you want to hit
-+ kdgb_break in assert.
-+
-+endmenu
-diff --git a/drivers/gpu/drm/amd/dal/Makefile b/drivers/gpu/drm/amd/dal/Makefile
-new file mode 100644
-index 0000000..bdf5d18
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/Makefile
-@@ -0,0 +1,19 @@
-+#
-+# Makefile for the DAL (Display Abstract Layer), which is a sub-component
-+# of the AMDGPU drm driver.
-+# It provides the HW control for display related functionalities.
-+
-+AMDDALPATH = $(RELATIVE_AMD_DAL_PATH)
-+
-+subdir-ccflags-y += -I$(AMDDALPATH)/ -I$(AMDDALPATH)/include -DDAL_CZ_BRINGUP
-+
-+subdir-ccflags-y += -I$(FULL_AMD_DAL_PATH)/dc/inc/
-+
-+#TODO: remove when Timing Sync feature is complete
-+subdir-ccflags-y += -DBUILD_FEATURE_TIMING_SYNC=0
-+
-+DAL_LIBS = amdgpu_dm dc
-+
-+AMD_DAL = $(addsuffix /Makefile, $(addprefix $(FULL_AMD_DAL_PATH)/,$(DAL_LIBS)))
-+
-+include $(AMD_DAL)
-diff --git a/drivers/gpu/drm/amd/dal/dal_power_interface_types.h b/drivers/gpu/drm/amd/dal/dal_power_interface_types.h
-new file mode 100644
-index 0000000..82e8ca2
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dal_power_interface_types.h
-@@ -0,0 +1,76 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_POWER_INTERFACE_TYPES_H__
-+#define __DAL_POWER_INTERFACE_TYPES_H__
-+
-+enum dal_to_power_clocks_state {
-+ PP_CLOCKS_STATE_INVALID,
-+ PP_CLOCKS_STATE_ULTRA_LOW,
-+ PP_CLOCKS_STATE_LOW,
-+ PP_CLOCKS_STATE_NOMINAL,
-+ PP_CLOCKS_STATE_PERFORMANCE
-+};
-+
-+/* clocks in khz */
-+struct dal_to_power_info {
-+ enum dal_to_power_clocks_state required_clock;
-+ uint32_t min_sclk;
-+ uint32_t min_mclk;
-+ uint32_t min_deep_sleep_sclk;
-+};
-+
-+/* clocks in khz */
-+struct power_to_dal_info {
-+ uint32_t min_sclk;
-+ uint32_t max_sclk;
-+ uint32_t min_mclk;
-+ uint32_t max_mclk;
-+};
-+
-+/* clocks in khz */
-+struct dal_system_clock_range {
-+ uint32_t min_sclk;
-+ uint32_t max_sclk;
-+
-+ uint32_t min_mclk;
-+ uint32_t max_mclk;
-+
-+ uint32_t min_dclk;
-+ uint32_t max_dclk;
-+
-+ /* Wireless Display */
-+ uint32_t min_eclk;
-+ uint32_t max_eclk;
-+};
-+
-+/* clocks in khz */
-+struct dal_to_power_dclk {
-+ uint32_t optimal; /* input: best optimizes for stutter efficiency */
-+ uint32_t minimal; /* input: the lowest clk that DAL can support */
-+ uint32_t established; /* output: the actually set one */
-+};
-+
-+#endif /* __DAL_POWER_INTERFACE_TYPES_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/dal_services.h b/drivers/gpu/drm/amd/dal/dal_services.h
-new file mode 100644
-index 0000000..398e4e5
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dal_services.h
-@@ -0,0 +1,266 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_SERVICES_H__
-+#define __DAL_SERVICES_H__
-+
-+/* DC headers*/
-+#include "dc/dc_services.h"
-+
-+#include "dal_power_interface_types.h"
-+
-+#include "irq_types.h"
-+#include "include/dal_types.h"
-+
-+/* TODO: investigate if it can be removed. */
-+/* Undefine DEPRECATED because it conflicts with printk.h */
-+#undef DEPRECATED
-+
-+/*
-+ *
-+ * interrupt services to register and unregister handlers
-+ *
-+ */
-+
-+/* the timer "interrupt" current implementation supports only
-+'one-shot' type, and LOW level (asynchronous) context */
-+void dal_register_timer_interrupt(
-+ struct dc_context *ctx,
-+ struct dc_timer_interrupt_params *int_params,
-+ interrupt_handler ih,
-+ void *handler_args);
-+
-+/*
-+ *
-+ * kernel memory manipulation
-+ *
-+ */
-+
-+/* Reallocate memory. The contents will remain unchanged.*/
-+void *dc_service_realloc(struct dc_context *ctx, const void *ptr, uint32_t size);
-+
-+void dc_service_memmove(void *dst, const void *src, uint32_t size);
-+
-+void dc_service_memset(void *p, int32_t c, uint32_t count);
-+
-+int32_t dal_memcmp(const void *p1, const void *p2, uint32_t count);
-+
-+int32_t dal_strncmp(const int8_t *p1, const int8_t *p2, uint32_t count);
-+
-+/*
-+ *
-+ * GPU registers access
-+ *
-+ */
-+static inline uint32_t dal_read_reg(
-+ const struct dc_context *ctx,
-+ uint32_t address)
-+{
-+ uint32_t value = cgs_read_register(ctx->cgs_device, address);
-+
-+#if defined(__DAL_REGISTER_LOGGER__)
-+ if (true == dal_reg_logger_should_dump_register()) {
-+ dal_reg_logger_rw_count_increment();
-+ DRM_INFO("%s 0x%x 0x%x\n", __func__, address, value);
-+ }
-+#endif
-+ return value;
-+}
-+
-+static inline uint32_t get_reg_field_value_ex(
-+ uint32_t reg_value,
-+ uint32_t mask,
-+ uint8_t shift)
-+{
-+ return (mask & reg_value) >> shift;
-+}
-+
-+#define get_reg_field_value(reg_value, reg_name, reg_field)\
-+ get_reg_field_value_ex(\
-+ (reg_value),\
-+ reg_name ## __ ## reg_field ## _MASK,\
-+ reg_name ## __ ## reg_field ## __SHIFT)
-+
-+static inline uint32_t set_reg_field_value_ex(
-+ uint32_t reg_value,
-+ uint32_t value,
-+ uint32_t mask,
-+ uint8_t shift)
-+{
-+ return (reg_value & ~mask) | (mask & (value << shift));
-+}
-+
-+#define set_reg_field_value(reg_value, value, reg_name, reg_field)\
-+ (reg_value) = set_reg_field_value_ex(\
-+ (reg_value),\
-+ (value),\
-+ reg_name ## __ ## reg_field ## _MASK,\
-+ reg_name ## __ ## reg_field ## __SHIFT)
-+
-+static inline void dal_write_reg(
-+ const struct dc_context *ctx,
-+ uint32_t address,
-+ uint32_t value)
-+{
-+#if defined(__DAL_REGISTER_LOGGER__)
-+ if (true == dal_reg_logger_should_dump_register()) {
-+ dal_reg_logger_rw_count_increment();
-+ DRM_INFO("%s 0x%x 0x%x\n", __func__, address, value);
-+ }
-+#endif
-+ cgs_write_register(ctx->cgs_device, address, value);
-+}
-+
-+static inline uint32_t dal_read_index_reg(
-+ const struct dc_context *ctx,
-+ enum cgs_ind_reg addr_space,
-+ uint32_t index)
-+{
-+ return cgs_read_ind_register(ctx->cgs_device,addr_space,index);
-+}
-+
-+static inline void dal_write_index_reg(
-+ const struct dc_context *ctx,
-+ enum cgs_ind_reg addr_space,
-+ uint32_t index,
-+ uint32_t value)
-+{
-+ cgs_write_ind_register(ctx->cgs_device,addr_space,index,value);
-+}
-+
-+enum platform_method {
-+ PM_GET_AVAILABLE_METHODS = 1 << 0,
-+ PM_GET_LID_STATE = 1 << 1,
-+ PM_GET_EXTENDED_BRIGHNESS_CAPS = 1 << 2
-+};
-+
-+struct platform_info_params {
-+ enum platform_method method;
-+ void *data;
-+};
-+
-+struct platform_info_brightness_caps {
-+ uint8_t ac_level_percentage;
-+ uint8_t dc_level_percentage;
-+};
-+
-+struct platform_info_ext_brightness_caps {
-+ struct platform_info_brightness_caps basic_caps;
-+ struct data_point {
-+ uint8_t luminance;
-+ uint8_t signal_level;
-+ } data_points[99];
-+
-+ uint8_t data_points_num;
-+ uint8_t min_input_signal;
-+ uint8_t max_input_signal;
-+};
-+
-+bool dal_get_platform_info(
-+ struct dc_context *ctx,
-+ struct platform_info_params *params);
-+
-+
-+static inline uint32_t dal_bios_cmd_table_para_revision(
-+ struct dc_context *ctx,
-+ uint32_t index)
-+{
-+ uint8_t frev;
-+ uint8_t crev;
-+
-+ if (cgs_atom_get_cmd_table_revs(
-+ ctx->cgs_device,
-+ index,
-+ &frev,
-+ &crev) != 0)
-+ return 0;
-+
-+ return crev;
-+}
-+
-+/* Calls to notification */
-+
-+/* Notify display manager for hotplug event */
-+void dal_notify_hotplug(
-+ struct dc_context *ctx,
-+ uint32_t display_index,
-+ bool is_connected);
-+
-+
-+void dal_notify_setmode_complete(
-+ struct dc_context *ctx,
-+ uint32_t h_total,
-+ uint32_t v_total,
-+ uint32_t h_active,
-+ uint32_t v_active,
-+ uint32_t pix_clk_in_khz);
-+
-+/* End of notification calls */
-+
-+/*
-+ *
-+ * Delay functions.
-+ *
-+ *
-+ */
-+
-+/* Following the guidance:
-+ * https://www.kernel.org/doc/Documentation/timers/timers-howto.txt
-+ *
-+ * This is a busy wait for nano seconds and should be used only for
-+ * extremely short ranges
-+ */
-+void dal_delay_in_nanoseconds(uint32_t nanoseconds);
-+
-+
-+/*
-+ *
-+ * atombios services
-+ *
-+ */
-+
-+bool dal_exec_bios_cmd_table(
-+ struct dc_context *ctx,
-+ uint32_t index,
-+ void *params);
-+
-+/*
-+ *
-+ * print-out services
-+ *
-+ */
-+#define dal_log_to_buffer(buffer, size, fmt, args)\
-+ vsnprintf(buffer, size, fmt, args)
-+
-+long dal_get_pid(void);
-+long dal_get_tgid(void);
-+
-+/*
-+ *
-+ * general debug capabilities
-+ *
-+ */
-+
-+#endif /* __DAL_SERVICES_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/dal_services_types.h b/drivers/gpu/drm/amd/dal/dal_services_types.h
-new file mode 100644
-index 0000000..89c73c6
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dal_services_types.h
-@@ -0,0 +1,62 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_SERVICES_TYPES_H__
-+#define __DAL_SERVICES_TYPES_H__
-+
-+#define INVALID_DISPLAY_INDEX 0xffffffff
-+
-+#if defined __KERNEL__
-+
-+#include <asm/byteorder.h>
-+#include <linux/types.h>
-+#include <drm/drmP.h>
-+
-+#include "cgs_linux.h"
-+
-+#if defined(__BIG_ENDIAN) && !defined(BIGENDIAN_CPU)
-+#define BIGENDIAN_CPU
-+#elif defined(__LITTLE_ENDIAN) && !defined(LITTLEENDIAN_CPU)
-+#define LITTLEENDIAN_CPU
-+#endif
-+
-+#undef READ
-+#undef WRITE
-+#undef FRAME_SIZE
-+
-+#define dal_output_to_console(fmt, ...) DRM_INFO(fmt, ##__VA_ARGS__)
-+
-+#define dal_error(fmt, ...) DRM_ERROR(fmt, ##__VA_ARGS__)
-+
-+#define dal_debug(fmt, ...) DRM_DEBUG_KMS(fmt, ##__VA_ARGS__)
-+
-+#define dal_vlog(fmt, args) vprintk(fmt, args)
-+
-+#define dal_min(x, y) min(x, y)
-+#define dal_max(x, y) max(x, y)
-+
-+#endif
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/Makefile b/drivers/gpu/drm/amd/dal/dc/Makefile
-new file mode 100644
-index 0000000..6926356
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/Makefile
-@@ -0,0 +1,24 @@
-+#
-+# Makefile for Display Core (dc) component.
-+#
-+
-+DC_LIBS = adapter asic_capability audio basics bios calcs connector \
-+dcs gpio gpu i2caux irq
-+
-+ifdef CONFIG_DRM_AMD_DAL_DCE11_0
-+DC_LIBS += dce110
-+endif
-+
-+AMD_DC = $(addsuffix /Makefile, $(addprefix $(FULL_AMD_DAL_PATH)/dc/,$(DC_LIBS)))
-+
-+include $(AMD_DC)
-+
-+DISPLAY_CORE = dc.o dc_link.o dc_resource.o dc_target.o dc_sink.o dc_stream.o \
-+dc_hw_sequencer.o dc_surface.o dc_link_hwss.o dc_link_dp.o
-+
-+AMD_DISPLAY_CORE = $(addprefix $(AMDDALPATH)/dc/core/,$(DISPLAY_CORE))
-+
-+AMD_DAL_FILES += $(AMD_DISPLAY_CORE)
-+
-+
-+
-diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/Makefile b/drivers/gpu/drm/amd/dal/dc/adapter/Makefile
-new file mode 100644
-index 0000000..8ede504
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/adapter/Makefile
-@@ -0,0 +1,18 @@
-+#
-+# Makefile for the 'adapter' sub-component of DAL.
-+# It provides the control and status of HW adapter.
-+
-+ADAPTER = adapter_service.o hw_ctx_adapter_service.o wireless_data_source.o
-+
-+AMD_DAL_ADAPTER = $(addprefix $(AMDDALPATH)/dc/adapter/,$(ADAPTER))
-+
-+AMD_DAL_FILES += $(AMD_DAL_ADAPTER)
-+
-+
-+###############################################################################
-+# DCE 11x
-+###############################################################################
-+
-+ifdef CONFIG_DRM_AMD_DAL_DCE11_0
-+AMD_DAL_FILES += $(AMDDALPATH)/dc/adapter/dce110/hw_ctx_adapter_service_dce110.o
-+endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
-new file mode 100644
-index 0000000..4f9a637
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
-@@ -0,0 +1,2037 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+
-+#include "dal_services.h"
-+
-+#include "include/adapter_service_interface.h"
-+#include "include/i2caux_interface.h"
-+#include "include/asic_capability_types.h"
-+#include "include/bios_parser_interface.h"
-+#include "include/gpio_service_interface.h"
-+#include "include/asic_capability_interface.h"
-+#include "include/logger_interface.h"
-+
-+#include "adapter_service.h"
-+#include "hw_ctx_adapter_service.h"
-+#include "wireless_data_source.h"
-+
-+#include "atom.h"
-+
-+#if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
-+#include "dce110/hw_ctx_adapter_service_dce110.h"
-+#endif
-+
-+/*
-+ * Adapter service feature entry table.
-+ *
-+ * This is an array of features that is used to generate feature set. Each
-+ * entry consists three element:
-+ *
-+ * Feature name, default value, and if this feature is a boolean type. A
-+ * feature can only be a boolean or int type.
-+ *
-+ * Example 1: a boolean type feature
-+ * FEATURE_ENABLE_HW_EDID_POLLING, false, true
-+ *
-+ * First element is feature name: EATURE_ENABLE_HW_EDID_POLLING, it has a
-+ * default value 0, and it is a boolean feature.
-+ *
-+ * Example 2: an int type feature
-+ * FEATURE_DCP_PROGRAMMING_WA, 0x1FF7, false
-+ *
-+ * In this case, the default value is 0x1FF7 and not a boolean type, which
-+ * makes it an int type.
-+ */
-+
-+static
-+#if !defined(DAL_CZ_BRINGUP)
-+const
-+#endif
-+struct feature_source_entry feature_entry_table[] = {
-+ /* Feature name | default value | is boolean type */
-+ {FEATURE_ENABLE_HW_EDID_POLLING, false, true},
-+ {FEATURE_DP_SINK_DETECT_POLL_DATA_PIN, false, true},
-+ {FEATURE_UNDERFLOW_INTERRUPT, false, true},
-+ {FEATURE_ALLOW_WATERMARK_ADJUSTMENT, false, true},
-+ {FEATURE_LIGHT_SLEEP, false, true},
-+ {FEATURE_DCP_DITHER_FRAME_RANDOM_ENABLE, false, true},
-+ {FEATURE_DCP_DITHER_RGB_RANDOM_ENABLE, false, true},
-+ {FEATURE_DCP_DITHER_HIGH_PASS_RANDOM_ENABLE, false, true},
-+ {FEATURE_LINE_BUFFER_ENHANCED_PIXEL_DEPTH, false, true},
-+ {FEATURE_MAXIMIZE_URGENCY_WATERMARKS, false, true},
-+ {FEATURE_MAXIMIZE_STUTTER_MARKS, false, true},
-+ {FEATURE_MAXIMIZE_NBP_MARKS, false, true},
-+ /*
-+ * We meet HW I2C issue when test S3 resume on KB.
-+ * An EPR is created for debug the issue.
-+ * Make Test has already been implemented
-+ * with HW I2C. The work load for revert back to SW I2C in make test
-+ * is big. Below is workaround for this issue.
-+ * Driver uses SW I2C.
-+ * Make Test uses HW I2C.
-+ */
-+#if defined(DAL_CZ_BRINGUP)
-+ {FEATURE_RESTORE_USAGE_I2C_SW_ENGINE, true, true},
-+#else
-+ {FEATURE_RESTORE_USAGE_I2C_SW_ENGINE, false, true},
-+#endif
-+ {FEATURE_USE_MAX_DISPLAY_CLK, false, true},
-+ {FEATURE_ALLOW_EDP_RESOURCE_SHARING, false, true},
-+ {FEATURE_SUPPORT_DP_YUV, false, true},
-+ {FEATURE_SUPPORT_DP_Y_ONLY, false, true},
-+ {FEATURE_DISABLE_DP_GTC_SYNC, true, true},
-+ {FEATURE_MODIFY_TIMINGS_FOR_WIRELESS, false, true},
-+ {FEATURE_DCP_BIT_DEPTH_REDUCTION_MODE, 0, false},
-+ {FEATURE_DCP_DITHER_MODE, 0, false},
-+ {FEATURE_DCP_PROGRAMMING_WA, 0, false},
-+ {FEATURE_NO_HPD_LOW_POLLING_VCC_OFF, false, true},
-+ {FEATURE_ENABLE_DFS_BYPASS, false, true},
-+ {FEATURE_WIRELESS_FULL_TIMING_ADJUSTMENT, false, true},
-+ {FEATURE_MAX_COFUNC_NON_DP_DISPLAYS, 2, false},
-+ {FEATURE_WIRELESS_LIMIT_720P, false, true},
-+ {FEATURE_MODIFY_TIMINGS_FOR_WIRELESS, false, true},
-+ {FEATURE_SUPPORTED_HDMI_CONNECTION_NUM, 0, false},
-+ {FEATURE_DETECT_REQUIRE_HPD_HIGH, false, true},
-+ {FEATURE_NO_HPD_LOW_POLLING_VCC_OFF, false, true},
-+ {FEATURE_LB_HIGH_RESOLUTION, false, true},
-+ {FEATURE_MAX_CONTROLLER_NUM, 0, false},
-+ {FEATURE_DRR_SUPPORT, AS_DRR_SUPPORT_ENABLED, false},
-+ {FEATURE_STUTTER_MODE, 15, false},
-+ {FEATURE_DP_DISPLAY_FORCE_SS_ENABLE, false, true},
-+ {FEATURE_REPORT_CE_MODE_ONLY, false, true},
-+ {FEATURE_ALLOW_OPTIMIZED_MODE_AS_DEFAULT, false, true},
-+ {FEATURE_DDC_READ_FORCE_REPEATED_START, false, true},
-+ {FEATURE_FORCE_TIMING_RESYNC, false, true},
-+ {FEATURE_TMDS_DISABLE_DITHERING, false, true},
-+ {FEATURE_HDMI_DISABLE_DITHERING, false, true},
-+ {FEATURE_DP_DISABLE_DITHERING, false, true},
-+ {FEATURE_EMBEDDED_DISABLE_DITHERING, true, true},
-+ {FEATURE_ALLOW_SELF_REFRESH, false, true},
-+ {FEATURE_ALLOW_DYNAMIC_PIXEL_ENCODING_CHANGE, false, true},
-+ {FEATURE_ALLOW_HSYNC_VSYNC_ADJUSTMENT, false, true},
-+ {FEATURE_FORCE_PSR, false, true},
-+ {FEATURE_PSR_SETUP_TIME_TEST, 0, false},
-+ {FEATURE_POWER_GATING_PIPE_IN_TILE, true, true},
-+ {FEATURE_POWER_GATING_LB_PORTION, true, true},
-+ {FEATURE_PREFER_3D_TIMING, false, true},
-+ {FEATURE_VARI_BRIGHT_ENABLE, true, true},
-+ {FEATURE_PSR_ENABLE, false, true},
-+ {FEATURE_WIRELESS_ENABLE_COMPRESSED_AUDIO, false, true},
-+ {FEATURE_WIRELESS_INCLUDE_UNVERIFIED_TIMINGS, true, true},
-+ {FEATURE_EDID_STRESS_READ, false, true},
-+ {FEATURE_DP_FRAME_PACK_STEREO3D, false, true},
-+ {FEATURE_DISPLAY_PREFERRED_VIEW, 0, false},
-+ {FEATURE_ALLOW_HDMI_WITHOUT_AUDIO, false, true},
-+ {FEATURE_ABM_2_0, false, true},
-+ {FEATURE_SUPPORT_MIRABILIS, false, true},
-+ {FEATURE_OPTIMIZATION, 0xFFFF, false},
-+ {FEATURE_PERF_MEASURE, 0, false},
-+ {FEATURE_MIN_BACKLIGHT_LEVEL, 0, false},
-+ {FEATURE_MAX_BACKLIGHT_LEVEL, 255, false},
-+ {FEATURE_LOAD_DMCU_FIRMWARE, true, true},
-+ {FEATURE_DISABLE_AZ_CLOCK_GATING, false, true},
-+ {FEATURE_ENABLE_GPU_SCALING, false, true},
-+ {FEATURE_DONGLE_SINK_COUNT_CHECK, true, true},
-+ {FEATURE_INSTANT_UP_SCALE_DOWN_SCALE, false, true},
-+ {FEATURE_TILED_DISPLAY, false, true},
-+ {FEATURE_PREFERRED_ABM_CONFIG_SET, 0, false},
-+ {FEATURE_CHANGE_SW_I2C_SPEED, 50, false},
-+ {FEATURE_CHANGE_HW_I2C_SPEED, 50, false},
-+ {FEATURE_CHANGE_I2C_SPEED_CONTROL, false, true},
-+ {FEATURE_DEFAULT_PSR_LEVEL, 0, false},
-+ {FEATURE_MAX_CLOCK_SOURCE_NUM, 0, false},
-+ {FEATURE_REPORT_SINGLE_SELECTED_TIMING, false, true},
-+ {FEATURE_ALLOW_HDMI_HIGH_CLK_DP_DONGLE, true, true},
-+ {FEATURE_SUPPORT_EXTERNAL_PANEL_DRR, false, true},
-+ {FEATURE_LVDS_SAFE_PIXEL_CLOCK_RANGE, 0, false},
-+ {FEATURE_ABM_CONFIG, 0, false},
-+ {FEATURE_WIRELESS_ENABLE, false, true},
-+ {FEATURE_ALLOW_DIRECT_MEMORY_ACCESS_TRIG, false, true},
-+ {FEATURE_FORCE_STATIC_SCREEN_EVENT_TRIGGERS, 0, false},
-+ {FEATURE_USE_PPLIB, true, true},
-+ {FEATURE_DISABLE_LPT_SUPPORT, false, true},
-+ {FEATURE_DUMMY_FBC_BACKEND, false, true},
-+ {FEATURE_DPMS_AUDIO_ENDPOINT_CONTROL, true, true},
-+ {FEATURE_DISABLE_FBC_COMP_CLK_GATE, false, true},
-+ {FEATURE_PIXEL_PERFECT_OUTPUT, false, true},
-+ {FEATURE_8BPP_SUPPORTED, false, true}
-+};
-+
-+
-+/* Stores entire ASIC features by sets */
-+uint32_t adapter_feature_set[FEATURE_MAXIMUM/32];
-+
-+enum {
-+ LEGACY_MAX_NUM_OF_CONTROLLERS = 2,
-+ DEFAULT_NUM_COFUNC_NON_DP_DISPLAYS = 2
-+};
-+
-+/*
-+ * get_feature_entries_num
-+ *
-+ * Get number of feature entries
-+ */
-+static inline uint32_t get_feature_entries_num(void)
-+{
-+ return ARRAY_SIZE(feature_entry_table);
-+}
-+
-+static void get_platform_info_methods(
-+ struct adapter_service *as)
-+{
-+ struct platform_info_params params;
-+ uint32_t mask = 0;
-+
-+ params.data = &mask;
-+ params.method = PM_GET_AVAILABLE_METHODS;
-+
-+ if (dal_get_platform_info(as->ctx, &params))
-+ as->platform_methods_mask = mask;
-+
-+
-+}
-+
-+static void initialize_backlight_caps(
-+ struct adapter_service *as)
-+{
-+ struct firmware_info fw_info;
-+ struct embedded_panel_info panel_info;
-+ struct platform_info_ext_brightness_caps caps;
-+ struct platform_info_params params;
-+ bool custom_curve_present = false;
-+ bool custom_min_max_present = false;
-+
-+ if (!(PM_GET_EXTENDED_BRIGHNESS_CAPS & as->platform_methods_mask)) {
-+ dal_logger_write(as->ctx->logger,
-+ LOG_MAJOR_BACKLIGHT,
-+ LOG_MINOR_BACKLIGHT_BRIGHTESS_CAPS,
-+ "This method is not supported\n");
-+ return;
-+ }
-+
-+ if (dal_bios_parser_get_firmware_info
-+ (as->bios_parser, &fw_info) != BP_RESULT_OK ||
-+ dal_bios_parser_get_embedded_panel_info
-+ (as->bios_parser, &panel_info) != BP_RESULT_OK)
-+ return;
-+
-+ params.data = &caps;
-+ params.method = PM_GET_EXTENDED_BRIGHNESS_CAPS;
-+
-+ if (dal_get_platform_info(as->ctx, &params)) {
-+ as->ac_level_percentage = caps.basic_caps.ac_level_percentage;
-+ as->dc_level_percentage = caps.basic_caps.dc_level_percentage;
-+ custom_curve_present = (caps.data_points_num > 0);
-+ custom_min_max_present = true;
-+ } else
-+ return;
-+ /* Choose minimum backlight level base on priority:
-+ * extended caps,VBIOS,default */
-+ if (custom_min_max_present)
-+ as->backlight_8bit_lut[0] = caps.min_input_signal;
-+
-+ else if (fw_info.min_allowed_bl_level > 0)
-+ as->backlight_8bit_lut[0] = fw_info.min_allowed_bl_level;
-+
-+ else
-+ as->backlight_8bit_lut[0] = DEFAULT_MIN_BACKLIGHT;
-+
-+ /* Choose maximum backlight level base on priority:
-+ * extended caps,default */
-+ if (custom_min_max_present)
-+ as->backlight_8bit_lut[100] = caps.max_input_signal;
-+
-+ else
-+ as->backlight_8bit_lut[100] = DEFAULT_MAX_BACKLIGHT;
-+
-+ if (as->backlight_8bit_lut[100] > ABSOLUTE_BACKLIGHT_MAX)
-+ as->backlight_8bit_lut[100] = ABSOLUTE_BACKLIGHT_MAX;
-+
-+ if (as->backlight_8bit_lut[0] > as->backlight_8bit_lut[100])
-+ as->backlight_8bit_lut[0] = as->backlight_8bit_lut[100];
-+
-+ if (custom_curve_present) {
-+ uint16_t index = 1;
-+ uint16_t i;
-+ uint16_t num_of_data_points = (caps.data_points_num <= 99 ?
-+ caps.data_points_num : 99);
-+ /* Filling translation table from data points -
-+ * between every two provided data points we
-+ * lineary interpolate missing values
-+ */
-+ for (i = 0 ; i < num_of_data_points; i++) {
-+ uint16_t luminance = caps.data_points[i].luminance;
-+ uint16_t signal_level =
-+ caps.data_points[i].signal_level;
-+
-+ if (signal_level < as->backlight_8bit_lut[0])
-+ signal_level = as->backlight_8bit_lut[0];
-+
-+ if (signal_level > as->backlight_8bit_lut[100])
-+ signal_level = as->backlight_8bit_lut[100];
-+
-+ /* Lineary interpolate missing values */
-+ if (index < luminance) {
-+ uint16_t base_value =
-+ as->backlight_8bit_lut[index-1];
-+ uint16_t delta_signal =
-+ signal_level - base_value;
-+ uint16_t delta_luma = luminance - index + 1;
-+ uint16_t step = delta_signal;
-+
-+ for (; index < luminance ; index++) {
-+ as->backlight_8bit_lut[index] =
-+ base_value +
-+ (step / delta_luma);
-+ step += delta_signal;
-+ }
-+ }
-+ /* Now [index == luminance], so we can add
-+ * data point to the translation table */
-+ as->backlight_8bit_lut[index++] = signal_level;
-+ }
-+ /* Complete the final segment of interpolation -
-+ * between last datapoint and maximum value */
-+ if (index < 100) {
-+ uint16_t base_value = as->backlight_8bit_lut[index-1];
-+ uint16_t delta_signal =
-+ as->backlight_8bit_lut[100]-base_value;
-+ uint16_t delta_luma = 100 - index + 1;
-+ uint16_t step = delta_signal;
-+
-+ for (; index < 100 ; index++) {
-+ as->backlight_8bit_lut[index] = base_value +
-+ (step / delta_luma);
-+ step += delta_signal;
-+ }
-+ }
-+ }
-+ /* build backlight translation table based on default curve */
-+ else {
-+ /* Default backlight curve can be defined by
-+ * polinomial F(x) = A(x*x) + Bx + C.
-+ * Backlight curve should always satisfy
-+ * F(0) = min, F(100) = max, so polinomial coefficients are:
-+ * A is 0.0255 - B/100 - min/10000 -
-+ * (255-max)/10000 = (max - min)/10000 - B/100
-+ * B is adjustable factor to modify the curve.
-+ * Bigger B results in less concave curve.
-+ * B range is [0..(max-min)/100]
-+ * C is backlight minimum
-+ */
-+ uint16_t delta = as->backlight_8bit_lut[100] -
-+ as->backlight_8bit_lut[0];
-+ uint16_t coeffc = as->backlight_8bit_lut[0];
-+ uint16_t coeffb = (BACKLIGHT_CURVE_COEFFB < delta ?
-+ BACKLIGHT_CURVE_COEFFB : delta);
-+ uint16_t coeffa = delta - coeffb;
-+ uint16_t i;
-+ uint32_t temp;
-+
-+ for (i = 1; i < 100 ; i++) {
-+ temp = (coeffa * i * i) / BACKLIGHT_CURVE_COEFFA_FACTOR;
-+ as->backlight_8bit_lut[i] = temp + (coeffb * i) /
-+ BACKLIGHT_CURVE_COEFFB_FACTOR + coeffc;
-+ }
-+ }
-+ as->backlight_caps_initialized = true;
-+}
-+
-+static void log_overriden_features(
-+ struct adapter_service *as,
-+ const char *feature_name,
-+ enum adapter_feature_id id,
-+ bool bool_feature,
-+ uint32_t value)
-+{
-+ if (bool_feature)
-+ dal_logger_write(as->ctx->logger,
-+ LOG_MAJOR_FEATURE_OVERRIDE,
-+ LOG_MINOR_FEATURE_OVERRIDE,
-+ "Overridden %s is %s now\n",
-+ feature_name,
-+ (value == 0) ? "disabled" : "enabled");
-+ else
-+ dal_logger_write(as->ctx->logger,
-+ LOG_MAJOR_FEATURE_OVERRIDE,
-+ LOG_MINOR_FEATURE_OVERRIDE,
-+ "Overridden %s new value: %d\n",
-+ feature_name,
-+ value);
-+}
-+
-+/*************************************
-+ * Local static functions definition *
-+ *************************************/
-+
-+#define check_bool_feature(feature) \
-+case FEATURE_ ## feature: \
-+ if (param->bool_param_enable_mask & \
-+ (1 << DAL_PARAM_ ## feature)) { \
-+ *data = param->bool_param_values & \
-+ (1 << DAL_PARAM_ ## feature); \
-+ ret = true; \
-+ feature_name = "FEATURE_" #feature; \
-+ } \
-+ break
-+
-+#define check_int_feature(feature) \
-+case FEATURE_ ## feature: \
-+ if (param->int_param_values[DAL_PARAM_ ## feature] != \
-+ DAL_PARAM_INVALID_INT) { \
-+ *data = param->int_param_values[DAL_PARAM_ ## feature];\
-+ ret = true;\
-+ bool_feature = false;\
-+ feature_name = "FEATURE_" #feature;\
-+ } \
-+ break
-+
-+/*
-+ * override_default_parameters
-+ *
-+ * Override features (from runtime parameter)
-+ * corresponding to Adapter Service Feature ID
-+ */
-+static bool override_default_parameters(
-+ struct adapter_service *as,
-+ const struct dal_override_parameters *param,
-+ const uint32_t idx,
-+ uint32_t *data)
-+{
-+ bool ret = false;
-+ bool bool_feature = true;
-+ char *feature_name;
-+
-+ if (idx >= get_feature_entries_num()) {
-+ ASSERT_CRITICAL(false);
-+ return false;
-+ }
-+
-+ switch (feature_entry_table[idx].feature_id) {
-+ check_int_feature(MAX_COFUNC_NON_DP_DISPLAYS);
-+ check_int_feature(DRR_SUPPORT);
-+ check_bool_feature(LIGHT_SLEEP);
-+ check_bool_feature(MAXIMIZE_STUTTER_MARKS);
-+ check_bool_feature(MAXIMIZE_URGENCY_WATERMARKS);
-+ check_bool_feature(USE_MAX_DISPLAY_CLK);
-+ check_bool_feature(ENABLE_DFS_BYPASS);
-+ check_bool_feature(POWER_GATING_PIPE_IN_TILE);
-+ check_bool_feature(POWER_GATING_LB_PORTION);
-+ check_bool_feature(PSR_ENABLE);
-+ check_bool_feature(VARI_BRIGHT_ENABLE);
-+ check_bool_feature(USE_PPLIB);
-+ check_bool_feature(DISABLE_LPT_SUPPORT);
-+ check_bool_feature(DUMMY_FBC_BACKEND);
-+ check_bool_feature(ENABLE_GPU_SCALING);
-+ default:
-+ return false;
-+ }
-+ if (ret)
-+ log_overriden_features(
-+ as,
-+ feature_name,
-+ feature_entry_table[idx].feature_id,
-+ bool_feature,
-+ *data);
-+
-+ return ret;
-+}
-+
-+/*
-+ * get_feature_value_from_data_sources
-+ *
-+ * For a given feature, determine its value from ASIC cap and wireless
-+ * data source.
-+ * idx : index of feature_entry_table for the feature id.
-+ */
-+static bool get_feature_value_from_data_sources(
-+ const struct adapter_service *as,
-+ const uint32_t idx,
-+ uint32_t *data)
-+{
-+ if (idx >= get_feature_entries_num()) {
-+ ASSERT_CRITICAL(false);
-+ return false;
-+ }
-+
-+ switch (feature_entry_table[idx].feature_id) {
-+ case FEATURE_MAX_COFUNC_NON_DP_DISPLAYS:
-+ *data = as->asic_cap->data[ASIC_DATA_MAX_COFUNC_NONDP_DISPLAYS];
-+ break;
-+
-+ case FEATURE_WIRELESS_LIMIT_720P:
-+ *data = as->asic_cap->caps.WIRELESS_LIMIT_TO_720P;
-+ break;
-+
-+ case FEATURE_WIRELESS_FULL_TIMING_ADJUSTMENT:
-+ *data = as->asic_cap->caps.WIRELESS_FULL_TIMING_ADJUSTMENT;
-+ break;
-+
-+ case FEATURE_MODIFY_TIMINGS_FOR_WIRELESS:
-+ *data = as->asic_cap->caps.WIRELESS_TIMING_ADJUSTMENT;
-+ break;
-+
-+ case FEATURE_SUPPORTED_HDMI_CONNECTION_NUM:
-+ *data =
-+ as->asic_cap->data[ASIC_DATA_SUPPORTED_HDMI_CONNECTION_NUM];
-+ break;
-+
-+ case FEATURE_DETECT_REQUIRE_HPD_HIGH:
-+ *data = as->asic_cap->caps.HPD_CHECK_FOR_EDID;
-+ break;
-+
-+ case FEATURE_NO_HPD_LOW_POLLING_VCC_OFF:
-+ *data = as->asic_cap->caps.NO_VCC_OFF_HPD_POLLING;
-+ break;
-+
-+ case FEATURE_STUTTER_MODE:
-+ *data = as->asic_cap->data[ASIC_DATA_STUTTERMODE];
-+ break;
-+
-+ case FEATURE_WIRELESS_ENABLE:
-+ *data = as->wireless_data.wireless_enable;
-+ break;
-+
-+ case FEATURE_8BPP_SUPPORTED:
-+ *data = as->asic_cap->caps.SUPPORT_8BPP;
-+ break;
-+
-+ default:
-+ return false;
-+ }
-+
-+ return true;
-+}
-+
-+/* get_bool_value
-+ *
-+ * Get the boolean value of a given feature
-+ */
-+static bool get_bool_value(
-+ const uint32_t set,
-+ const uint32_t idx)
-+{
-+ if (idx >= 32) {
-+ ASSERT_CRITICAL(false);
-+ return false;
-+ }
-+
-+ return ((set & (1 << idx)) != 0);
-+}
-+
-+/*
-+ * get_hpd_info
-+ *
-+ * Get HPD information from BIOS
-+ */
-+static bool get_hpd_info(struct adapter_service *as,
-+ struct graphics_object_id id,
-+ struct graphics_object_hpd_info *info)
-+{
-+ return BP_RESULT_OK ==
-+ dal_bios_parser_get_hpd_info(as->bios_parser, id, info);
-+}
-+
-+/*
-+ * lookup_feature_entry
-+ *
-+ * Find the entry index of a given feature in feature table
-+ */
-+static uint32_t lookup_feature_entry(
-+ enum adapter_feature_id feature_id)
-+{
-+ uint32_t entries_num = get_feature_entries_num();
-+ uint32_t i = 0;
-+
-+ while (i != entries_num) {
-+ if (feature_entry_table[i].feature_id == feature_id)
-+ break;
-+
-+ ++i;
-+ }
-+
-+ return i;
-+}
-+
-+/*
-+ * set_bool_value
-+ *
-+ * Set the boolean value of a given feature
-+ */
-+static void set_bool_value(
-+ uint32_t *set,
-+ const uint32_t idx,
-+ bool value)
-+{
-+ if (idx >= 32) {
-+ ASSERT_CRITICAL(false);
-+ return;
-+ }
-+
-+ if (value)
-+ *set |= (1 << idx);
-+ else
-+ *set &= ~(1 << idx);
-+}
-+
-+/*
-+ * generate_feature_set
-+ *
-+ * Generate the internal feature set from multiple data sources
-+ */
-+static bool generate_feature_set(
-+ struct adapter_service *as,
-+ const struct dal_override_parameters *param)
-+{
-+ uint32_t i = 0;
-+ uint32_t value = 0;
-+ uint32_t set_idx = 0;
-+ uint32_t internal_idx = 0;
-+ uint32_t entry_num = 0;
-+ const struct feature_source_entry *entry = NULL;
-+
-+ dc_service_memset(adapter_feature_set, 0, sizeof(adapter_feature_set));
-+ entry_num = get_feature_entries_num();
-+
-+
-+ while (i != entry_num) {
-+ entry = &feature_entry_table[i];
-+
-+ if (entry->feature_id <= FEATURE_UNKNOWN ||
-+ entry->feature_id >= FEATURE_MAXIMUM) {
-+ ASSERT_CRITICAL(false);
-+ return false;
-+ }
-+
-+ set_idx = (uint32_t)((entry->feature_id - 1) / 32);
-+ internal_idx = (uint32_t)((entry->feature_id - 1) % 32);
-+
-+ /* TODO: wireless, runtime parameter, vbios */
-+ if (!override_default_parameters(as, param, i, &value)) {
-+ if (!get_feature_value_from_data_sources(
-+ as, i, &value)) {
-+ /*
-+ * Can't find feature values from
-+ * above data sources
-+ * Assign default value
-+ */
-+ value = entry->default_value;
-+ }
-+ }
-+
-+ if (entry->is_boolean_type)
-+ set_bool_value(&adapter_feature_set[set_idx],
-+ internal_idx,
-+ value != 0);
-+ else
-+ adapter_feature_set[set_idx] = value;
-+
-+ i++;
-+ }
-+
-+ return true;
-+}
-+
-+
-+/*
-+ * create_hw_ctx
-+ *
-+ * Create HW context for adapter service. This is DCE specific.
-+ */
-+static struct hw_ctx_adapter_service *create_hw_ctx(
-+ enum dce_version dce_version,
-+ struct dc_context *ctx)
-+{
-+ switch (dce_version) {
-+#if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
-+ case DCE_VERSION_11_0:
-+ return dal_adapter_service_create_hw_ctx_dce110(ctx);
-+#endif
-+ default:
-+ ASSERT_CRITICAL(false);
-+ return NULL;
-+ }
-+}
-+
-+/*
-+ * adapter_service_destruct
-+ *
-+ * Release memory of objects in adapter service
-+ */
-+static void adapter_service_destruct(
-+ struct adapter_service *as)
-+{
-+ dal_adapter_service_destroy_hw_ctx(&as->hw_ctx);
-+ dal_i2caux_destroy(&as->i2caux);
-+ dal_bios_parser_destroy(&as->bios_parser);
-+ dal_gpio_service_destroy(&as->gpio_service);
-+ dal_asic_capability_destroy(&as->asic_cap);
-+ dal_bios_parser_destroy_integrated_info(as->ctx, &as->integrated_info);
-+}
-+
-+/*
-+ * adapter_service_construct
-+ *
-+ * Construct the derived type of adapter service
-+ */
-+static bool adapter_service_construct(
-+ struct adapter_service *as,
-+ struct as_init_data *init_data)
-+{
-+ if (!init_data)
-+ return false;
-+
-+ /* Create ASIC capability */
-+ as->ctx = init_data->ctx;
-+ as->asic_cap = dal_asic_capability_create(
-+ &init_data->hw_init_data, as->ctx);
-+
-+ if (!as->asic_cap) {
-+ ASSERT_CRITICAL(false);
-+ return false;
-+ }
-+
-+#if defined(DAL_CZ_BRINGUP)
-+ if (dal_adapter_service_get_dce_version(as) == DCE_VERSION_11_0) {
-+ uint32_t i;
-+
-+ for (i = 0; i < ARRAY_SIZE(feature_entry_table); i++) {
-+ enum adapter_feature_id id =
-+ feature_entry_table[i].feature_id;
-+ if (id == FEATURE_MAXIMIZE_URGENCY_WATERMARKS ||
-+ id == FEATURE_MAXIMIZE_STUTTER_MARKS ||
-+ id == FEATURE_MAXIMIZE_NBP_MARKS)
-+ feature_entry_table[i].default_value = true;
-+ }
-+ }
-+#endif
-+
-+ /* Generate feature set table */
-+ if (!generate_feature_set(as, init_data->display_param)) {
-+ ASSERT_CRITICAL(false);
-+ goto failed_to_generate_features;
-+ }
-+
-+ /* Create BIOS parser */
-+ init_data->bp_init_data.ctx = init_data->ctx;
-+ as->bios_parser =
-+ dal_bios_parser_create(&init_data->bp_init_data, as);
-+
-+ if (!as->bios_parser) {
-+ ASSERT_CRITICAL(false);
-+ goto failed_to_create_bios_parser;
-+ }
-+
-+ /* Create GPIO service */
-+ as->gpio_service =
-+ dal_gpio_service_create(
-+ dal_adapter_service_get_dce_version(as),
-+ as->ctx);
-+
-+ if (!as->gpio_service) {
-+ ASSERT_CRITICAL(false);
-+ goto failed_to_create_gpio_service;
-+ }
-+
-+ /* Create I2C AUX */
-+ as->i2caux = dal_i2caux_create(as, as->ctx);
-+
-+ if (!as->i2caux) {
-+ ASSERT_CRITICAL(false);
-+ goto failed_to_create_i2caux;
-+ }
-+
-+ /* Create Adapter Service HW Context*/
-+ as->hw_ctx = create_hw_ctx(
-+ dal_adapter_service_get_dce_version(as),
-+ as->ctx);
-+
-+ if (!as->hw_ctx) {
-+ ASSERT_CRITICAL(false);
-+ goto failed_to_create_hw_ctx;
-+ }
-+
-+ /* Avoid wireless encoder creation in upstream branch. */
-+
-+ /* Integrated info is not provided on discrete ASIC. NULL is allowed */
-+ as->integrated_info = dal_bios_parser_create_integrated_info(
-+ as->bios_parser);
-+
-+ dal_bios_parser_post_init(as->bios_parser);
-+
-+ /* Generate backlight translation table and initializes
-+ other brightness properties */
-+ as->backlight_caps_initialized = false;
-+
-+ get_platform_info_methods(as);
-+
-+ initialize_backlight_caps(as);
-+
-+ return true;
-+
-+failed_to_generate_features:
-+ dal_adapter_service_destroy_hw_ctx(&as->hw_ctx);
-+
-+failed_to_create_hw_ctx:
-+ dal_i2caux_destroy(&as->i2caux);
-+
-+failed_to_create_i2caux:
-+ dal_gpio_service_destroy(&as->gpio_service);
-+
-+failed_to_create_gpio_service:
-+ dal_bios_parser_destroy(&as->bios_parser);
-+
-+failed_to_create_bios_parser:
-+ dal_asic_capability_destroy(&as->asic_cap);
-+
-+ return false;
-+}
-+
-+/*
-+ * Global function definition
-+ */
-+
-+/*
-+ * dal_adapter_service_create
-+ *
-+ * Create adapter service
-+ */
-+struct adapter_service *dal_adapter_service_create(
-+ struct as_init_data *init_data)
-+{
-+ struct adapter_service *as;
-+
-+ as = dc_service_alloc(init_data->ctx, sizeof(struct adapter_service));
-+
-+ if (!as) {
-+ ASSERT_CRITICAL(false);
-+ return NULL;
-+ }
-+
-+ if (adapter_service_construct(as, init_data))
-+ return as;
-+
-+ ASSERT_CRITICAL(false);
-+
-+ dc_service_free(init_data->ctx, as);
-+
-+ return NULL;
-+}
-+
-+/*
-+ * dal_adapter_service_destroy
-+ *
-+ * Destroy adapter service and objects it contains
-+ */
-+void dal_adapter_service_destroy(
-+ struct adapter_service **as)
-+{
-+ if (!as) {
-+ ASSERT_CRITICAL(false);
-+ return;
-+ }
-+
-+ if (!*as) {
-+ ASSERT_CRITICAL(false);
-+ return;
-+ }
-+
-+ adapter_service_destruct(*as);
-+
-+ dc_service_free((*as)->ctx, *as);
-+
-+ *as = NULL;
-+}
-+
-+/*
-+ * dal_adapter_service_get_dce_version
-+ *
-+ * Get the DCE version of current ASIC
-+ */
-+enum dce_version dal_adapter_service_get_dce_version(
-+ const struct adapter_service *as)
-+{
-+ uint32_t version = as->asic_cap->data[ASIC_DATA_DCE_VERSION];
-+
-+ switch (version) {
-+#if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
-+ case 0x110:
-+ return DCE_VERSION_11_0;
-+#endif
-+ default:
-+ ASSERT_CRITICAL(false);
-+ return DCE_VERSION_UNKNOWN;
-+ }
-+}
-+
-+/*
-+ * dal_adapter_service_get_controllers_num
-+ *
-+ * Get number of controllers
-+ */
-+uint8_t dal_adapter_service_get_controllers_num(
-+ struct adapter_service *as)
-+{
-+ uint32_t result = as->asic_cap->data[ASIC_DATA_CONTROLLERS_NUM];
-+
-+ /* Check the "max num of controllers" feature,
-+ * use it for debugging purposes only */
-+ /* TODO implement
-+ * dal_adapter_service_get_feature_value(as, ) */
-+
-+ return result;
-+}
-+
-+
-+/** Get total number of connectors.
-+ *
-+ * \param as Adapter Service
-+ *
-+ * \return Total number of connectors. It is up-to-the caller to decide
-+ * if the number is valid.
-+ */
-+uint8_t dal_adapter_service_get_connectors_num(
-+ struct adapter_service *as)
-+{
-+ uint8_t vbios_connectors_num = 0;
-+ uint8_t wireless_connectors_num = 0;
-+
-+ vbios_connectors_num = dal_bios_parser_get_connectors_number(
-+ as->bios_parser);
-+ wireless_connectors_num = wireless_get_connectors_num(as);
-+
-+ return vbios_connectors_num + wireless_connectors_num;
-+}
-+
-+static bool is_wireless_object(struct graphics_object_id id)
-+{
-+ if ((id.type == OBJECT_TYPE_ENCODER &&
-+ id.id == ENCODER_ID_INTERNAL_WIRELESS) ||
-+ (id.type == OBJECT_TYPE_CONNECTOR && id.id ==
-+ CONNECTOR_ID_WIRELESS) ||
-+ (id.type == OBJECT_TYPE_CONNECTOR && id.id ==
-+ CONNECTOR_ID_MIRACAST))
-+ return true;
-+ return false;
-+}
-+
-+/**
-+ * Get the number of source objects of an object
-+ *
-+ * \param [in] as: Adapter Service
-+ *
-+ * \param [in] id: The graphics object id
-+ *
-+ * \return
-+ * The number of the source objects of an object
-+ */
-+uint32_t dal_adapter_service_get_src_num(
-+ struct adapter_service *as, struct graphics_object_id id)
-+{
-+ if (is_wireless_object(id))
-+ return wireless_get_srcs_num(as, id);
-+ else
-+ return dal_bios_parser_get_src_number(as->bios_parser, id);
-+}
-+
-+/**
-+ * Get the source objects of an object
-+ *
-+ * \param [in] id The graphics object id
-+ * \param [in] index Enumerating index which starts at 0
-+ *
-+ * \return If enumerating successfully, return the VALID source object id,
-+ * otherwise, returns "zeroed out" object id.
-+ * Client should call dal_graphics_object_id_is_valid() to check
-+ * weather the id is valid.
-+ */
-+struct graphics_object_id dal_adapter_service_get_src_obj(
-+ struct adapter_service *as,
-+ struct graphics_object_id id,
-+ uint32_t index)
-+{
-+ struct graphics_object_id src_object_id;
-+
-+ if (is_wireless_object(id))
-+ src_object_id = wireless_get_src_obj_id(as, id, index);
-+ else {
-+ if (BP_RESULT_OK !=
-+ dal_bios_parser_get_src_obj(
-+ as->bios_parser, id, index, &src_object_id))
-+ src_object_id =
-+ dal_graphics_object_id_init(
-+ 0,
-+ ENUM_ID_UNKNOWN,
-+ OBJECT_TYPE_UNKNOWN);
-+ }
-+
-+ return src_object_id;
-+}
-+
-+/** Get connector object id associated with a connector index.
-+ *
-+ * \param as Adapter Service
-+ *
-+ * \param connector_index Index of connector between zero and total number
-+ * returned by dal_adapter_service_get_connectors_num()
-+ *
-+ * \return graphics object id corresponding to the connector_index.
-+ */
-+struct graphics_object_id dal_adapter_service_get_connector_obj_id(
-+ struct adapter_service *as,
-+ uint8_t connector_index)
-+{
-+ uint8_t bios_connectors_num =
-+ dal_bios_parser_get_connectors_number(as->bios_parser);
-+
-+ if (connector_index >= bios_connectors_num)
-+ return wireless_get_connector_id(
-+ as,
-+ connector_index);
-+ else
-+ return dal_bios_parser_get_connector_id(
-+ as->bios_parser,
-+ connector_index);
-+}
-+
-+bool dal_adapter_service_get_device_tag(
-+ struct adapter_service *as,
-+ struct graphics_object_id connector_object_id,
-+ uint32_t device_tag_index,
-+ struct connector_device_tag_info *info)
-+{
-+ if (BP_RESULT_OK == dal_bios_parser_get_device_tag(as->bios_parser,
-+ connector_object_id, device_tag_index, info))
-+ return true;
-+ else
-+ return false;
-+}
-+
-+/* Check if DeviceId is supported by ATOM_OBJECT_HEADER support info */
-+bool dal_adapter_service_is_device_id_supported(struct adapter_service *as,
-+ struct device_id id)
-+{
-+ return dal_bios_parser_is_device_id_supported(as->bios_parser, id);
-+}
-+
-+bool dal_adapter_service_is_meet_underscan_req(struct adapter_service *as)
-+{
-+ struct firmware_info fw_info;
-+ enum bp_result bp_result = dal_adapter_service_get_firmware_info(
-+ as, &fw_info);
-+ uint32_t disp_clk_limit =
-+ as->asic_cap->data[ASIC_DATA_MIN_DISPCLK_FOR_UNDERSCAN];
-+ if (BP_RESULT_OK == bp_result) {
-+ dal_logger_write(as->ctx->logger,
-+ LOG_MAJOR_ERROR,
-+ LOG_MINOR_COMPONENT_ADAPTER_SERVICE,
-+ "Read firmware is NULL");
-+ return false;
-+ }
-+ if (fw_info.default_display_engine_pll_frequency < disp_clk_limit)
-+ return false;
-+ return true;
-+}
-+
-+bool dal_adapter_service_underscan_for_hdmi_only(struct adapter_service *as)
-+{
-+ return as->asic_cap->caps.UNDERSCAN_FOR_HDMI_ONLY;
-+}
-+/*
-+ * dal_adapter_service_get_clock_sources_num
-+ *
-+ * Get number of clock sources
-+ */
-+uint8_t dal_adapter_service_get_clock_sources_num(
-+ struct adapter_service *as)
-+{
-+ struct firmware_info fw_info;
-+ uint32_t max_clk_src = 0;
-+ uint32_t num = as->asic_cap->data[ASIC_DATA_CLOCKSOURCES_NUM];
-+
-+ /*
-+ * Check is system supports the use of the External clock source
-+ * as a clock source for DP
-+ */
-+ enum bp_result bp_result =
-+ dal_bios_parser_get_firmware_info(as->bios_parser,
-+ &fw_info);
-+
-+ if (BP_RESULT_OK == bp_result &&
-+ fw_info.external_clock_source_frequency_for_dp != 0)
-+ ++num;
-+
-+ /*
-+ * Add clock source for wireless if supported
-+ */
-+ num += (uint32_t)wireless_get_clocks_num(as);
-+
-+ /* Check the "max number of clock sources" feature */
-+ if (dal_adapter_service_get_feature_value(
-+ FEATURE_MAX_CLOCK_SOURCE_NUM,
-+ &max_clk_src,
-+ sizeof(uint32_t)))
-+ if ((max_clk_src != 0) && (max_clk_src < num))
-+ num = max_clk_src;
-+
-+ return num;
-+}
-+
-+/*
-+ * dal_adapter_service_get_func_controllers_num
-+ *
-+ * Get number of controllers
-+ */
-+uint8_t dal_adapter_service_get_func_controllers_num(
-+ struct adapter_service *as)
-+{
-+ uint32_t result =
-+ as->asic_cap->data[ASIC_DATA_FUNCTIONAL_CONTROLLERS_NUM];
-+
-+ /* Check the "max num of controllers" feature,
-+ * use it for debugging purposes only */
-+
-+ /* Limit number of controllers by OS */
-+
-+ struct asic_feature_flags flags;
-+
-+ flags.raw = as->asic_cap->data[ASIC_DATA_FEATURE_FLAGS];
-+
-+ if (flags.bits.LEGACY_CLIENT &&
-+ (result > LEGACY_MAX_NUM_OF_CONTROLLERS))
-+ result = LEGACY_MAX_NUM_OF_CONTROLLERS;
-+
-+ return result;
-+}
-+
-+/*
-+ * dal_adapter_service_is_feature_supported
-+ *
-+ * Return if a given feature is supported by the ASIC. The feature has to be
-+ * a boolean type.
-+ */
-+bool dal_adapter_service_is_feature_supported(
-+ enum adapter_feature_id feature_id)
-+{
-+ bool data = 0;
-+
-+ dal_adapter_service_get_feature_value(feature_id, &data, sizeof(bool));
-+
-+ return data;
-+}
-+
-+/**
-+ * Reports maximum number of confunctional non-DP displays.
-+ * Value can be overriden if FEATURE_REPORT_SINGLE_SELECTED_TIMING feature is
-+ * enabled.
-+ *
-+ * \return
-+ * Maximum number of confunctional non-DP displays
-+ */
-+uint32_t dal_adapter_service_get_max_cofunc_non_dp_displays(void)
-+{
-+ uint32_t non_dp_displays = DEFAULT_NUM_COFUNC_NON_DP_DISPLAYS;
-+
-+ if (true == dal_adapter_service_get_feature_value(
-+ FEATURE_MAX_COFUNC_NON_DP_DISPLAYS,
-+ &non_dp_displays,
-+ sizeof(non_dp_displays))) {
-+ /* the cached value exist */
-+ /* TODO: add more logic as per-DAL2 */
-+ }
-+
-+ return non_dp_displays;
-+}
-+
-+uint32_t dal_adapter_service_get_single_selected_timing_signals(void)
-+{
-+ uint32_t signals_bitmap = 0;
-+
-+ if (dal_adapter_service_is_feature_supported(
-+ FEATURE_REPORT_SINGLE_SELECTED_TIMING)) {
-+ /* the cached value exist */
-+ /* TODO: add more logic as per-DAL2 */
-+ signals_bitmap = 0;
-+ }
-+
-+ return signals_bitmap;
-+}
-+
-+/*
-+ * dal_adapter_service_get_i2c_info
-+ *
-+ * Get I2C information from BIOS
-+ */
-+bool dal_adapter_service_get_i2c_info(
-+ struct adapter_service *as,
-+ struct graphics_object_id id,
-+ struct graphics_object_i2c_info *i2c_info)
-+{
-+ if (!i2c_info) {
-+ ASSERT_CRITICAL(false);
-+ return false;
-+ }
-+
-+ return BP_RESULT_OK ==
-+ dal_bios_parser_get_i2c_info(as->bios_parser, id, i2c_info);
-+}
-+
-+/*
-+ * dal_adapter_service_obtain_ddc
-+ *
-+ * Obtain DDC
-+ */
-+struct ddc *dal_adapter_service_obtain_ddc(
-+ struct adapter_service *as,
-+ struct graphics_object_id id)
-+{
-+ struct graphics_object_i2c_info i2c_info;
-+ struct gpio_ddc_hw_info hw_info;
-+
-+
-+ if (!dal_adapter_service_get_i2c_info(as, id, &i2c_info))
-+ return NULL;
-+
-+ hw_info.ddc_channel = i2c_info.i2c_line;
-+ hw_info.hw_supported = i2c_info.i2c_hw_assist;
-+
-+ return dal_gpio_service_create_ddc(
-+ as->gpio_service,
-+ i2c_info.gpio_info.clk_a_register_index,
-+ 1 << i2c_info.gpio_info.clk_a_shift,
-+ &hw_info);
-+}
-+
-+/*
-+ * dal_adapter_service_release_ddc
-+ *
-+ * Release DDC
-+ */
-+void dal_adapter_service_release_ddc(
-+ struct adapter_service *as,
-+ struct ddc *ddc)
-+{
-+ dal_gpio_service_destroy_ddc(&ddc);
-+}
-+
-+/*
-+ * dal_adapter_service_obtain_hpd_irq
-+ *
-+ * Obtain HPD interrupt request
-+ */
-+struct irq *dal_adapter_service_obtain_hpd_irq(
-+ struct adapter_service *as,
-+ struct graphics_object_id id)
-+{
-+ enum bp_result bp_result;
-+
-+ struct graphics_object_hpd_info hpd_info;
-+ struct gpio_pin_info pin_info;
-+
-+ if (!get_hpd_info(as, id, &hpd_info))
-+ return NULL;
-+
-+ bp_result = dal_bios_parser_get_gpio_pin_info(as->bios_parser,
-+ hpd_info.hpd_int_gpio_uid, &pin_info);
-+
-+ if (bp_result != BP_RESULT_OK) {
-+ ASSERT(bp_result == BP_RESULT_NORECORD);
-+ return NULL;
-+ }
-+
-+ return dal_gpio_service_create_irq(
-+ as->gpio_service,
-+ pin_info.offset,
-+ pin_info.mask);
-+}
-+
-+/*
-+ * dal_adapter_service_release_irq
-+ *
-+ * Release interrupt request
-+ */
-+void dal_adapter_service_release_irq(
-+ struct adapter_service *as,
-+ struct irq *irq)
-+{
-+ dal_gpio_service_destroy_irq(&irq);
-+}
-+
-+/*
-+ * dal_adapter_service_get_ss_info_num
-+ *
-+ * Get number of spread spectrum entries from BIOS
-+ */
-+uint32_t dal_adapter_service_get_ss_info_num(
-+ struct adapter_service *as,
-+ enum as_signal_type signal)
-+{
-+ return dal_bios_parser_get_ss_entry_number(as->bios_parser, signal);
-+}
-+
-+/*
-+ * dal_adapter_service_get_ss_info
-+ *
-+ * Get spread spectrum info from BIOS
-+ */
-+bool dal_adapter_service_get_ss_info(
-+ struct adapter_service *as,
-+ enum as_signal_type signal,
-+ uint32_t idx,
-+ struct spread_spectrum_info *info)
-+{
-+ enum bp_result bp_result =
-+ dal_bios_parser_get_spread_spectrum_info(
-+ as->bios_parser, signal, idx, info);
-+
-+ return BP_RESULT_OK == bp_result;
-+}
-+
-+/*
-+ * dal_adapter_service_get_integrated_info
-+ *
-+ * Get integrated information on BIOS
-+ */
-+bool dal_adapter_service_get_integrated_info(
-+ struct adapter_service *as,
-+ struct integrated_info *info)
-+{
-+ if (info == NULL || as->integrated_info == NULL)
-+ return false;
-+
-+ dc_service_memmove(info, as->integrated_info, sizeof(struct integrated_info));
-+
-+ return true;
-+}
-+
-+/*
-+ * dal_adapter_service_is_dfs_bypass_enabled
-+ *
-+ * Check if DFS bypass is enabled
-+ */
-+bool dal_adapter_service_is_dfs_bypass_enabled(
-+ struct adapter_service *as)
-+{
-+ if (as->integrated_info == NULL)
-+ return false;
-+ if ((as->integrated_info->gpu_cap_info & DFS_BYPASS_ENABLE) &&
-+ dal_adapter_service_is_feature_supported(
-+ FEATURE_ENABLE_DFS_BYPASS))
-+ return true;
-+ else
-+ return false;
-+}
-+
-+/*
-+ * dal_adapter_service_get_sw_i2c_speed
-+ *
-+ * Get SW I2C speed
-+ */
-+uint32_t dal_adapter_service_get_sw_i2c_speed(
-+ struct adapter_service *as)
-+{
-+ /* TODO: only from ASIC caps. Feature key is not implemented*/
-+ return as->asic_cap->data[ASIC_DATA_DEFAULT_I2C_SPEED_IN_KHZ];
-+}
-+
-+/*
-+ * dal_adapter_service_get_hw_i2c_speed
-+ *
-+ * Get HW I2C speed
-+ */
-+uint32_t dal_adapter_service_get_hw_i2c_speed(
-+ struct adapter_service *as)
-+{
-+ /* TODO: only from ASIC caps. Feature key is not implemented*/
-+ return as->asic_cap->data[ASIC_DATA_DEFAULT_I2C_SPEED_IN_KHZ];
-+}
-+
-+/*
-+ * dal_adapter_service_get_mc_latency
-+ *
-+ * Get memory controller latency
-+ */
-+uint32_t dal_adapter_service_get_mc_latency(
-+ struct adapter_service *as)
-+{
-+ return as->asic_cap->data[ASIC_DATA_MC_LATENCY];
-+}
-+
-+/*
-+ * dal_adapter_service_get_asic_vram_bit_width
-+ *
-+ * Get the video RAM bit width set on the ASIC
-+ */
-+uint32_t dal_adapter_service_get_asic_vram_bit_width(
-+ struct adapter_service *as)
-+{
-+ return as->asic_cap->data[ASIC_DATA_VRAM_BITWIDTH];
-+}
-+
-+/*
-+ * dal_adapter_service_get_asic_bugs
-+ *
-+ * Get the bug flags set on this ASIC
-+ */
-+struct asic_bugs dal_adapter_service_get_asic_bugs(
-+ struct adapter_service *as)
-+{
-+ return as->asic_cap->bugs;
-+}
-+
-+
-+struct dal_asic_runtime_flags dal_adapter_service_get_asic_runtime_flags(
-+ struct adapter_service *as)
-+{
-+ return as->asic_cap->runtime_flags;
-+}
-+
-+/*
-+ * dal_adapter_service_get_line_buffer_size
-+ *
-+ * Get line buffer size
-+ */
-+uint32_t dal_adapter_service_get_line_buffer_size(
-+ struct adapter_service *as)
-+{
-+ return as->asic_cap->data[ASIC_DATA_LINEBUFFER_SIZE];
-+}
-+
-+/*
-+ * dal_adapter_service_get_bandwidth_tuning_params
-+ *
-+ * Get parameters for bandwidth tuning
-+ */
-+bool dal_adapter_service_get_bandwidth_tuning_params(
-+ struct adapter_service *as,
-+ union bandwidth_tuning_params *params)
-+{
-+ /* TODO: add implementation */
-+ /* note: data comes from runtime parameters */
-+ return false;
-+}
-+
-+/*
-+ * dal_adapter_service_get_feature_flags
-+ *
-+ * Get a copy of ASIC feature flags
-+ */
-+struct asic_feature_flags dal_adapter_service_get_feature_flags(
-+ struct adapter_service *as)
-+{
-+ struct asic_feature_flags result = { { 0 } };
-+
-+ if (!as) {
-+ ASSERT_CRITICAL(false);
-+ return result;
-+ }
-+
-+ result.raw = as->asic_cap->data[ASIC_DATA_FEATURE_FLAGS];
-+
-+ return result;
-+}
-+
-+/*
-+ * dal_adapter_service_get_dram_bandwidth_efficiency
-+ *
-+ * Get efficiency of DRAM
-+ */
-+uint32_t dal_adapter_service_get_dram_bandwidth_efficiency(
-+ struct adapter_service *as)
-+{
-+ return as->asic_cap->data[ASIC_DATA_DRAM_BANDWIDTH_EFFICIENCY];
-+}
-+
-+/*
-+ * dal_adapter_service_obtain_gpio
-+ *
-+ * Obtain GPIO
-+ */
-+struct gpio *dal_adapter_service_obtain_gpio(
-+ struct adapter_service *as,
-+ enum gpio_id id,
-+ uint32_t en)
-+{
-+ return dal_gpio_service_create_gpio_ex(
-+ as->gpio_service, id, en,
-+ GPIO_PIN_OUTPUT_STATE_DEFAULT);
-+}
-+
-+/*
-+ * dal_adapter_service_obtain_stereo_gpio
-+ *
-+ * Obtain GPIO for stereo3D
-+ */
-+struct gpio *dal_adapter_service_obtain_stereo_gpio(
-+ struct adapter_service *as)
-+{
-+ const bool have_param_stereo_gpio = false;
-+
-+ struct asic_feature_flags result;
-+
-+ result.raw = as->asic_cap->data[ASIC_DATA_FEATURE_FLAGS];
-+
-+ /* Case 1 : Workstation stereo */
-+ if (result.bits.WORKSTATION_STEREO)
-+ /* "active low" <--> "default 3d right eye polarity" = false */
-+ return dal_gpio_service_create_gpio_ex(
-+ as->gpio_service, GPIO_ID_GENERIC, GPIO_GENERIC_A,
-+ GPIO_PIN_OUTPUT_STATE_ACTIVE_LOW);
-+ /* Case 2 : runtime parameter override for sideband stereo */
-+ else if (have_param_stereo_gpio) {
-+ /* TODO implement */
-+ return NULL;
-+ /* Case 3 : VBIOS gives us GPIO for sideband stereo */
-+ } else {
-+ const struct graphics_object_id id =
-+ dal_graphics_object_id_init(
-+ GENERIC_ID_STEREO,
-+ ENUM_ID_1,
-+ OBJECT_TYPE_GENERIC);
-+
-+ struct bp_gpio_cntl_info cntl_info;
-+ struct gpio_pin_info pin_info;
-+
-+ /* Get GPIO record for this object.
-+ * Stereo GPIO record should have exactly one entry
-+ * where active state defines stereosync polarity */
-+ if (1 != dal_bios_parser_get_gpio_record(
-+ as->bios_parser, id, &cntl_info, 1)) {
-+ return NULL;
-+ } else if (BP_RESULT_OK != dal_bios_parser_get_gpio_pin_info(
-+ as->bios_parser, cntl_info.id, &pin_info)) {
-+ /*ASSERT_CRITICAL(false);*/
-+ return NULL;
-+ } else
-+ return dal_gpio_service_create_gpio_ex(
-+ as->gpio_service,
-+ pin_info.offset, pin_info.mask,
-+ cntl_info.state);
-+ }
-+}
-+
-+/*
-+ * dal_adapter_service_release_gpio
-+ *
-+ * Release GPIO
-+ */
-+void dal_adapter_service_release_gpio(
-+ struct adapter_service *as,
-+ struct gpio *gpio)
-+{
-+ dal_gpio_service_destroy_gpio(&gpio);
-+}
-+
-+/*
-+ * dal_adapter_service_get_firmware_info
-+ *
-+ * Get firmware information from BIOS
-+ */
-+bool dal_adapter_service_get_firmware_info(
-+ struct adapter_service *as,
-+ struct firmware_info *info)
-+{
-+ return dal_bios_parser_get_firmware_info(as->bios_parser, info) ==
-+ BP_RESULT_OK;
-+}
-+
-+/*
-+ * dal_adapter_service_get_audio_support
-+ *
-+ * Get information on audio support
-+ */
-+union audio_support dal_adapter_service_get_audio_support(
-+ struct adapter_service *as)
-+{
-+ return dal_adapter_service_hw_ctx_get_audio_support(as->hw_ctx);
-+}
-+
-+/*
-+ * dal_adapter_service_get_stream_engines_num
-+ *
-+ * Get number of stream engines
-+ */
-+uint8_t dal_adapter_service_get_stream_engines_num(
-+ struct adapter_service *as)
-+{
-+ return as->asic_cap->data[ASIC_DATA_DIGFE_NUM];
-+}
-+
-+/*
-+ * dal_adapter_service_get_feature_value
-+ *
-+ * Get the cached value of a given feature. This value can be a boolean, int,
-+ * or characters.
-+ */
-+bool dal_adapter_service_get_feature_value(
-+ const enum adapter_feature_id feature_id,
-+ void *data,
-+ uint32_t size)
-+{
-+ uint32_t entry_idx = 0;
-+ uint32_t set_idx = 0;
-+ uint32_t set_internal_idx = 0;
-+
-+ if (feature_id >= FEATURE_MAXIMUM || feature_id <= FEATURE_UNKNOWN) {
-+ ASSERT_CRITICAL(false);
-+ return false;
-+ }
-+
-+ if (data == NULL) {
-+ ASSERT_CRITICAL(false);
-+ return false;
-+ }
-+
-+ entry_idx = lookup_feature_entry(feature_id);
-+ set_idx = (uint32_t)((feature_id - 1)/32);
-+ set_internal_idx = (uint32_t)((feature_id - 1) % 32);
-+
-+ if (entry_idx >= get_feature_entries_num()) {
-+ /* Cannot find this entry */
-+ ASSERT_CRITICAL(false);
-+ return false;
-+ }
-+
-+ if (feature_entry_table[entry_idx].is_boolean_type) {
-+ if (size != sizeof(bool)) {
-+ ASSERT_CRITICAL(false);
-+ return false;
-+ }
-+
-+ *(bool *)data = get_bool_value(adapter_feature_set[set_idx],
-+ set_internal_idx);
-+ } else {
-+ if (size != sizeof(uint32_t)) {
-+ ASSERT_CRITICAL(false);
-+ return false;
-+ }
-+
-+ *(uint32_t *)data = adapter_feature_set[set_idx];
-+ }
-+
-+ return true;
-+}
-+
-+/*
-+ * dal_adapter_service_get_memory_type_multiplier
-+ *
-+ * Get multiplier for the memory type
-+ */
-+uint32_t dal_adapter_service_get_memory_type_multiplier(
-+ struct adapter_service *as)
-+{
-+ return as->asic_cap->data[ASIC_DATA_MEMORYTYPE_MULTIPLIER];
-+}
-+
-+/*
-+ * dal_adapter_service_get_bios_parser
-+ *
-+ * Get BIOS parser handler
-+ */
-+struct bios_parser *dal_adapter_service_get_bios_parser(
-+ struct adapter_service *as)
-+{
-+ return as->bios_parser;
-+}
-+
-+/*
-+ * dal_adapter_service_get_i2caux
-+ *
-+ * Get i2c aux handler
-+ */
-+struct i2caux *dal_adapter_service_get_i2caux(
-+ struct adapter_service *as)
-+{
-+ return as->i2caux;
-+}
-+
-+bool dal_adapter_service_initialize_hw_data(
-+ struct adapter_service *as)
-+{
-+ return as->hw_ctx->funcs->power_up(as->hw_ctx);
-+}
-+
-+struct graphics_object_id dal_adapter_service_enum_fake_path_resource(
-+ struct adapter_service *as,
-+ uint32_t index)
-+{
-+ return as->hw_ctx->funcs->enum_fake_path_resource(as->hw_ctx, index);
-+}
-+
-+struct graphics_object_id dal_adapter_service_enum_stereo_sync_object(
-+ struct adapter_service *as,
-+ uint32_t index)
-+{
-+ return as->hw_ctx->funcs->enum_stereo_sync_object(as->hw_ctx, index);
-+}
-+
-+struct graphics_object_id dal_adapter_service_enum_sync_output_object(
-+ struct adapter_service *as,
-+ uint32_t index)
-+{
-+ return as->hw_ctx->funcs->enum_sync_output_object(as->hw_ctx, index);
-+}
-+
-+struct graphics_object_id dal_adapter_service_enum_audio_object(
-+ struct adapter_service *as,
-+ uint32_t index)
-+{
-+ return as->hw_ctx->funcs->enum_audio_object(as->hw_ctx, index);
-+}
-+
-+
-+void dal_adapter_service_update_audio_connectivity(
-+ struct adapter_service *as,
-+ uint32_t number_of_audio_capable_display_path)
-+{
-+ as->hw_ctx->funcs->update_audio_connectivity(
-+ as->hw_ctx,
-+ number_of_audio_capable_display_path,
-+ dal_adapter_service_get_controllers_num(as));
-+}
-+
-+bool dal_adapter_service_has_embedded_display_connector(
-+ struct adapter_service *as)
-+{
-+ uint8_t index;
-+ uint8_t num_connectors = dal_adapter_service_get_connectors_num(as);
-+
-+ if (num_connectors == 0 || num_connectors > ENUM_ID_COUNT)
-+ return false;
-+
-+ for (index = 0; index < num_connectors; index++) {
-+ struct graphics_object_id obj_id =
-+ dal_adapter_service_get_connector_obj_id(as, index);
-+ enum connector_id connector_id =
-+ dal_graphics_object_id_get_connector_id(obj_id);
-+
-+ if ((connector_id == CONNECTOR_ID_LVDS) ||
-+ (connector_id == CONNECTOR_ID_EDP))
-+ return true;
-+ }
-+
-+ return false;
-+}
-+
-+bool dal_adapter_service_get_embedded_panel_info(
-+ struct adapter_service *as,
-+ struct embedded_panel_info *info)
-+{
-+ enum bp_result result;
-+
-+ if (info == NULL)
-+ /*TODO: add DALASSERT_MSG here*/
-+ return false;
-+
-+ result = dal_bios_parser_get_embedded_panel_info(
-+ as->bios_parser, info);
-+
-+ return result == BP_RESULT_OK;
-+}
-+
-+bool dal_adapter_service_enum_embedded_panel_patch_mode(
-+ struct adapter_service *as,
-+ uint32_t index,
-+ struct embedded_panel_patch_mode *mode)
-+{
-+ enum bp_result result;
-+
-+ if (mode == NULL)
-+ /*TODO: add DALASSERT_MSG here*/
-+ return false;
-+
-+ result = dal_bios_parser_enum_embedded_panel_patch_mode(
-+ as->bios_parser, index, mode);
-+
-+ return result == BP_RESULT_OK;
-+}
-+
-+bool dal_adapter_service_get_faked_edid_len(
-+ struct adapter_service *as,
-+ uint32_t *len)
-+{
-+ enum bp_result result;
-+
-+ result = dal_bios_parser_get_faked_edid_len(
-+ as->bios_parser,
-+ len);
-+ return result == BP_RESULT_OK;
-+}
-+
-+bool dal_adapter_service_get_faked_edid_buf(
-+ struct adapter_service *as,
-+ uint8_t *buf,
-+ uint32_t len)
-+{
-+ enum bp_result result;
-+
-+ result = dal_bios_parser_get_faked_edid_buf(
-+ as->bios_parser,
-+ buf,
-+ len);
-+ return result == BP_RESULT_OK;
-+
-+}
-+
-+/*
-+ * dal_adapter_service_is_fusion
-+ *
-+ * Is this Fusion ASIC
-+ */
-+bool dal_adapter_service_is_fusion(struct adapter_service *as)
-+{
-+ return as->asic_cap->caps.IS_FUSION;
-+}
-+
-+/*
-+ * dal_adapter_service_is_dfsbyass_dynamic
-+ *
-+ *
-+ **/
-+bool dal_adapter_service_is_dfsbyass_dynamic(struct adapter_service *as)
-+{
-+ return as->asic_cap->caps.DFSBYPASS_DYNAMIC_SUPPORT;
-+}
-+
-+/*
-+ * dal_adapter_service_should_optimize
-+ *
-+ * @brief Reports whether driver settings allow requested optimization
-+ *
-+ * @param
-+ * as: adapter service handler
-+ * feature: for which optimization is validated
-+ *
-+ * @return
-+ * true if requested feature can be optimized
-+ */
-+bool dal_adapter_service_should_optimize(
-+ struct adapter_service *as, enum optimization_feature feature)
-+{
-+ uint32_t supported_optimization = 0;
-+ struct dal_asic_runtime_flags flags;
-+
-+ if (!dal_adapter_service_get_feature_value(FEATURE_OPTIMIZATION,
-+ &supported_optimization, sizeof(uint32_t)))
-+ return false;
-+
-+ /* Retrieve ASIC runtime flags */
-+ flags = dal_adapter_service_get_asic_runtime_flags(as);
-+
-+ /* Check runtime flags against different optimization features */
-+ switch (feature) {
-+ case OF_SKIP_HW_PROGRAMMING_ON_ENABLED_EMBEDDED_DISPLAY:
-+ if (!flags.flags.bits.OPTIMIZED_DISPLAY_PROGRAMMING_ON_BOOT)
-+ return false;
-+ break;
-+
-+ case OF_SKIP_RESET_OF_ALL_HW_ON_S3RESUME:
-+ if (as->integrated_info == NULL ||
-+ !flags.flags.bits.SKIP_POWER_DOWN_ON_RESUME)
-+ return false;
-+ break;
-+ case OF_SKIP_POWER_DOWN_INACTIVE_ENCODER:
-+ if (!dal_adapter_service_get_asic_runtime_flags(as).flags.bits.
-+ SKIP_POWER_DOWN_ON_RESUME)
-+ return false;
-+ break;
-+ default:
-+ break;
-+ }
-+
-+ return (supported_optimization & feature) != 0;
-+}
-+
-+/*
-+ * dal_adapter_service_is_in_accelerated_mode
-+ *
-+ * @brief Determine if driver is in accelerated mode
-+ *
-+ * @param
-+ * as: Adapter Service handler
-+ *
-+ * @out
-+ * True if driver is in accelerated mode, false otherwise.
-+ */
-+bool dal_adapter_service_is_in_accelerated_mode(struct adapter_service *as)
-+{
-+ return dal_bios_parser_is_accelerated_mode(as->bios_parser);
-+}
-+
-+struct ddc *dal_adapter_service_obtain_ddc_from_i2c_info(
-+ struct adapter_service *as,
-+ struct graphics_object_i2c_info *info)
-+{
-+ struct gpio_ddc_hw_info hw_info = {
-+ info->i2c_hw_assist,
-+ info->i2c_line };
-+ return dal_gpio_service_create_ddc(as->gpio_service,
-+ info->gpio_info.clk_a_register_index,
-+ (1 << info->gpio_info.clk_a_shift), &hw_info);
-+}
-+
-+struct bdf_info dal_adapter_service_get_adapter_info(struct adapter_service *as)
-+{
-+ return as->bdf_info;
-+}
-+
-+/*
-+ * dal_adapter_service_should_psr_skip_wait_for_pll_lock
-+ *
-+ * @brief Determine if this ASIC needs to wait on PLL lock bit
-+ *
-+ * @param
-+ * as: Adapter Service handle
-+ *
-+ * @out
-+ * True if ASIC does not need to wait for PLL lock bit, i.e. skip the wait.
-+ */
-+bool dal_adapter_service_should_psr_skip_wait_for_pll_lock(
-+ struct adapter_service *as)
-+{
-+ return as->asic_cap->caps.SKIP_PSR_WAIT_FOR_PLL_LOCK_BIT;
-+}
-+
-+bool dal_adapter_service_is_lid_open(struct adapter_service *as)
-+{
-+ bool is_lid_open = false;
-+ struct platform_info_params params;
-+
-+ params.data = &is_lid_open;
-+ params.method = PM_GET_LID_STATE;
-+
-+ if ((PM_GET_LID_STATE & as->platform_methods_mask) &&
-+ dal_get_platform_info(as->ctx, &params))
-+ return is_lid_open;
-+
-+#if defined(CONFIG_DRM_AMD_DAL_VBIOS_PRESENT)
-+ return dal_bios_parser_is_lid_open(as->bios_parser);
-+#else
-+ return false;
-+#endif
-+}
-+
-+bool dal_adapter_service_get_panel_backlight_default_levels(
-+ struct adapter_service *as,
-+ struct panel_backlight_levels *levels)
-+{
-+ if (!as->backlight_caps_initialized)
-+ return false;
-+
-+ levels->ac_level_percentage = as->ac_level_percentage;
-+ levels->dc_level_percentage = as->dc_level_percentage;
-+ return true;
-+}
-+
-+bool dal_adapter_service_get_panel_backlight_boundaries(
-+ struct adapter_service *as,
-+ struct panel_backlight_boundaries *boundaries)
-+{
-+ if (!as->backlight_caps_initialized)
-+ return false;
-+ if (boundaries != NULL) {
-+ boundaries->min_signal_level = as->backlight_8bit_lut[0];
-+ boundaries->max_signal_level =
-+ as->backlight_8bit_lut[SIZEOF_BACKLIGHT_LUT - 1];
-+ return true;
-+ }
-+ return false;
-+}
-+
-+
-+uint32_t dal_adapter_service_get_view_port_pixel_granularity(
-+ struct adapter_service *as)
-+{
-+ return as->asic_cap->data[ASIC_DATA_VIEWPORT_PIXEL_GRANULARITY];
-+}
-+
-+/**
-+ * Get number of paths per DP 1.2 connector from the runtime parameter if it
-+ * exists.
-+ * A check to see if MST is supported for the generation of ASIC is done
-+ *
-+ * \return
-+ * Number of paths per DP 1.2 connector is exists in runtime parameters
-+ * or ASIC cap
-+ */
-+uint32_t dal_adapter_service_get_num_of_path_per_dp_mst_connector(
-+ struct adapter_service *as)
-+{
-+ if (as->asic_cap->caps.DP_MST_SUPPORTED == 0) {
-+ /* ASIC doesn't support DP MST at all */
-+ return 0;
-+ }
-+
-+ return as->asic_cap->data[ASIC_DATA_PATH_NUM_PER_DPMST_CONNECTOR];
-+}
-+
-+uint32_t dal_adapter_service_get_num_of_underlays(
-+ struct adapter_service *as)
-+{
-+ return as->asic_cap->data[ASIC_DATA_NUM_OF_VIDEO_PLANES];
-+}
-+
-+bool dal_adapter_service_get_encoder_cap_info(
-+ struct adapter_service *as,
-+ struct graphics_object_id id,
-+ struct graphics_object_encoder_cap_info *info)
-+{
-+ struct bp_encoder_cap_info bp_cap_info = {0};
-+ enum bp_result result;
-+
-+ if (NULL == info) {
-+ ASSERT_CRITICAL(false);
-+ return false;
-+ }
-+
-+ /*
-+ * Retrieve Encoder Capability Information from VBIOS and store the
-+ * call result (success or fail)
-+ * Info from VBIOS about HBR2 has two fields:
-+ *
-+ * - dpHbr2Cap: indicates supported/not supported by HW Encoder
-+ * - dpHbr2En : indicates DP spec compliant/not compliant
-+ */
-+ result = dal_bios_parser_get_encoder_cap_info(
-+ as->bios_parser,
-+ id,
-+ &bp_cap_info);
-+
-+ /* Set dp_hbr2_validated flag (it's equal to Enable) */
-+ info->dp_hbr2_validated = bp_cap_info.DP_HBR2_EN;
-+
-+ if (result == BP_RESULT_OK) {
-+ info->dp_hbr2_cap = bp_cap_info.DP_HBR2_CAP;
-+ return true;
-+ }
-+
-+ return false;
-+}
-+
-+bool dal_adapter_service_is_mc_tuning_req(struct adapter_service *as)
-+{
-+ return as->asic_cap->caps.NEED_MC_TUNING ? true : false;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.h b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.h
-new file mode 100644
-index 0000000..25ac648
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.h
-@@ -0,0 +1,67 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_ADAPTER_SERVICE_H__
-+#define __DAL_ADAPTER_SERVICE_H__
-+
-+/* Include */
-+#include "include/adapter_service_interface.h"
-+#include "wireless_data_source.h"
-+
-+/*
-+ * Forward declaration
-+ */
-+struct gpio_service;
-+struct asic_cap;
-+
-+/* Adapter service */
-+struct adapter_service {
-+ struct dc_context *ctx;
-+ struct asic_capability *asic_cap;
-+ struct bios_parser *bios_parser;
-+ struct gpio_service *gpio_service;
-+ struct i2caux *i2caux;
-+ struct wireless_data wireless_data;
-+ struct hw_ctx_adapter_service *hw_ctx;
-+ struct integrated_info *integrated_info;
-+ struct bdf_info bdf_info;
-+ uint32_t platform_methods_mask;
-+ uint32_t ac_level_percentage;
-+ uint32_t dc_level_percentage;
-+ uint32_t backlight_caps_initialized;
-+ uint32_t backlight_8bit_lut[SIZEOF_BACKLIGHT_LUT];
-+};
-+
-+/* Type of feature with its runtime parameter and default value */
-+struct feature_source_entry {
-+ enum adapter_feature_id feature_id;
-+ uint32_t default_value;
-+ bool is_boolean_type;
-+};
-+
-+/* Stores entire ASIC features by sets */
-+extern uint32_t adapter_feature_set[];
-+
-+#endif /* __DAL_ADAPTER_SERVICE_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/dce110/hw_ctx_adapter_service_dce110.c b/drivers/gpu/drm/amd/dal/dc/adapter/dce110/hw_ctx_adapter_service_dce110.c
-new file mode 100644
-index 0000000..31c2aab
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/adapter/dce110/hw_ctx_adapter_service_dce110.c
-@@ -0,0 +1,303 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+#include "../hw_ctx_adapter_service.h"
-+
-+#include "hw_ctx_adapter_service_dce110.h"
-+
-+#include "include/logger_interface.h"
-+#include "include/grph_object_id.h"
-+
-+#include "dce/dce_11_0_d.h"
-+#include "dce/dce_11_0_sh_mask.h"
-+
-+#ifndef mmCC_DC_HDMI_STRAPS
-+#define mmCC_DC_HDMI_STRAPS 0x4819
-+#define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40
-+#define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6
-+#define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700
-+#define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8
-+#endif
-+
-+static const struct graphics_object_id invalid_go = {
-+ 0, ENUM_ID_UNKNOWN, OBJECT_TYPE_UNKNOWN, 0
-+};
-+
-+/* Macro */
-+#define AUDIO_STRAPS_HDMI_ENABLE 0x2
-+
-+#define FROM_HW_CTX(ptr) \
-+ container_of((ptr), struct hw_ctx_adapter_service_dce110, base)
-+
-+static const uint32_t audio_index_reg_offset[] = {
-+ /*CZ has 3 DIGs but 4 audio endpoints*/
-+ mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX,
-+ mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX,
-+ mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX,
-+ mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX
-+};
-+
-+static const uint32_t audio_data_reg_offset[] = {
-+ mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA,
-+ mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA,
-+ mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA,
-+ mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA,
-+};
-+
-+enum {
-+ MAX_NUMBER_OF_AUDIO_PINS = 4
-+};
-+
-+static void destruct(
-+ struct hw_ctx_adapter_service_dce110 *hw_ctx)
-+{
-+ /* There is nothing to destruct at the moment */
-+ dal_adapter_service_destruct_hw_ctx(&hw_ctx->base);
-+}
-+
-+static void destroy(
-+ struct hw_ctx_adapter_service *ptr)
-+{
-+ struct hw_ctx_adapter_service_dce110 *hw_ctx =
-+ FROM_HW_CTX(ptr);
-+
-+ destruct(hw_ctx);
-+
-+ dc_service_free(ptr->ctx, hw_ctx);
-+}
-+
-+/*
-+ * enum_audio_object
-+ *
-+ * @brief enumerate audio object
-+ *
-+ * @param
-+ * const struct hw_ctx_adapter_service *hw_ctx - [in] provides num of endpoints
-+ * uint32_t index - [in] audio index
-+ *
-+ * @return
-+ * grphic object id
-+ */
-+static struct graphics_object_id enum_audio_object(
-+ const struct hw_ctx_adapter_service *hw_ctx,
-+ uint32_t index)
-+{
-+ uint32_t number_of_connected_audio_endpoints =
-+ FROM_HW_CTX(hw_ctx)->number_of_connected_audio_endpoints;
-+
-+ if (index >= number_of_connected_audio_endpoints ||
-+ number_of_connected_audio_endpoints == 0)
-+ return invalid_go;
-+ else
-+ return dal_graphics_object_id_init(
-+ AUDIO_ID_INTERNAL_AZALIA,
-+ (enum object_enum_id)(index + 1),
-+ OBJECT_TYPE_AUDIO);
-+}
-+
-+static uint32_t get_number_of_connected_audio_endpoints_multistream(
-+ struct dc_context *ctx)
-+{
-+ uint32_t num_connected_audio_endpoints = 0;
-+ uint32_t i;
-+ uint32_t default_config =
-+ ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT;
-+
-+ /* find the total number of streams available via the
-+ * AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
-+ * registers (one for each pin) starting from pin 1
-+ * up to the max number of audio pins.
-+ * We stop on the first pin where
-+ * PORT_CONNECTIVITY == 1 (as instructed by HW team).
-+ */
-+ for (i = 0; i < MAX_NUMBER_OF_AUDIO_PINS; i++) {
-+ uint32_t value = 0;
-+
-+ set_reg_field_value(value,
-+ default_config,
-+ AZALIA_F0_CODEC_ENDPOINT_INDEX,
-+ AZALIA_ENDPOINT_REG_INDEX);
-+
-+ dal_write_reg(ctx, audio_index_reg_offset[i], value);
-+
-+ value = 0;
-+ value = dal_read_reg(ctx, audio_data_reg_offset[i]);
-+
-+ /* 1 means not supported*/
-+ if (get_reg_field_value(value,
-+ AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT,
-+ PORT_CONNECTIVITY) == 1)
-+ break;
-+
-+ num_connected_audio_endpoints++;
-+ }
-+
-+ return num_connected_audio_endpoints;
-+
-+}
-+
-+/*
-+ * get_number_of_connected_audio_endpoints
-+ */
-+static uint32_t get_number_of_connected_audio_endpoints(
-+ struct hw_ctx_adapter_service *hw_ctx)
-+{
-+ uint32_t addr = mmCC_DC_HDMI_STRAPS;
-+ uint32_t value = 0;
-+ uint32_t field = 0;
-+
-+ if (hw_ctx->cached_audio_straps == AUDIO_STRAPS_NOT_ALLOWED)
-+ /* audio straps indicate no audio supported */
-+ return 0;
-+
-+ value = dal_read_reg(hw_ctx->ctx, addr);
-+
-+ field = get_reg_field_value(
-+ value, CC_DC_HDMI_STRAPS, AUDIO_STREAM_NUMBER);
-+ if (field == 1)
-+ /* multi streams not supported */
-+ return 1;
-+ else if (field == 0)
-+ /* multi streams supported */
-+ return get_number_of_connected_audio_endpoints_multistream(
-+ hw_ctx->ctx);
-+
-+ /* unexpected value */
-+ ASSERT_CRITICAL(false);
-+ return field;
-+}
-+
-+
-+/*
-+ * power_up
-+ *
-+ * @brief
-+ * Determine and cache audio support from register.
-+ *
-+ * @param
-+ * struct hw_ctx_adapter_service *hw_ctx - [in] adapter service hw context
-+ *
-+ * @return
-+ * true if succeed, false otherwise
-+ */
-+static bool power_up(
-+ struct hw_ctx_adapter_service *hw_ctx)
-+{
-+ struct hw_ctx_adapter_service_dce110 *hw_ctx_dce11 =
-+ FROM_HW_CTX(hw_ctx);
-+ /* Allow DP audio all the time
-+ * without additional pinstrap check on Fusion */
-+
-+
-+ {
-+ uint32_t value = 0;
-+ uint32_t field = 0;
-+
-+ value = dal_read_reg(hw_ctx->ctx, mmCC_DC_HDMI_STRAPS);
-+ field = get_reg_field_value(
-+ value, CC_DC_HDMI_STRAPS, HDMI_DISABLE);
-+
-+ if (field == 0) {
-+ hw_ctx->cached_audio_straps = AUDIO_STRAPS_DP_HDMI_AUDIO;
-+ } else {
-+ value = dal_read_reg(
-+ hw_ctx->ctx, mmDC_PINSTRAPS);
-+ field = get_reg_field_value(
-+ value,
-+ DC_PINSTRAPS,
-+ DC_PINSTRAPS_AUDIO);
-+
-+ if (field & AUDIO_STRAPS_HDMI_ENABLE)
-+ hw_ctx->cached_audio_straps =
-+ AUDIO_STRAPS_DP_HDMI_AUDIO_ON_DONGLE;
-+ else
-+ hw_ctx->cached_audio_straps =
-+ AUDIO_STRAPS_DP_AUDIO_ALLOWED;
-+ }
-+
-+ }
-+
-+ /* get the number of connected audio endpoints */
-+ hw_ctx_dce11->number_of_connected_audio_endpoints =
-+ get_number_of_connected_audio_endpoints(hw_ctx);
-+
-+ return true;
-+}
-+
-+static void update_audio_connectivity(
-+ struct hw_ctx_adapter_service *hw_ctx,
-+ uint32_t number_of_audio_capable_display_path,
-+ uint32_t number_of_controllers)
-+{
-+ /* this one should be empty on DCE110 */
-+}
-+
-+static const struct hw_ctx_adapter_service_funcs funcs = {
-+ .destroy = destroy,
-+ .power_up = power_up,
-+ .enum_fake_path_resource = NULL,
-+ .enum_stereo_sync_object = NULL,
-+ .enum_sync_output_object = NULL,
-+ .enum_audio_object = enum_audio_object,
-+ .update_audio_connectivity = update_audio_connectivity
-+};
-+
-+static bool construct(
-+ struct hw_ctx_adapter_service_dce110 *hw_ctx,
-+ struct dc_context *ctx)
-+{
-+ if (!dal_adapter_service_construct_hw_ctx(&hw_ctx->base, ctx)) {
-+ ASSERT_CRITICAL(false);
-+ return false;
-+ }
-+
-+ hw_ctx->base.funcs = &funcs;
-+ hw_ctx->number_of_connected_audio_endpoints = 0;
-+
-+ return true;
-+}
-+
-+struct hw_ctx_adapter_service *
-+ dal_adapter_service_create_hw_ctx_dce110(
-+ struct dc_context *ctx)
-+{
-+ struct hw_ctx_adapter_service_dce110 *hw_ctx =
-+ dc_service_alloc(ctx, sizeof(struct hw_ctx_adapter_service_dce110));
-+
-+ if (!hw_ctx) {
-+ ASSERT_CRITICAL(false);
-+ return NULL;
-+ }
-+
-+ if (construct(hw_ctx, ctx))
-+ return &hw_ctx->base;
-+
-+ ASSERT_CRITICAL(false);
-+
-+ dc_service_free(ctx, hw_ctx);
-+
-+ return NULL;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/dce110/hw_ctx_adapter_service_dce110.h b/drivers/gpu/drm/amd/dal/dc/adapter/dce110/hw_ctx_adapter_service_dce110.h
-new file mode 100644
-index 0000000..092b671
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/adapter/dce110/hw_ctx_adapter_service_dce110.h
-@@ -0,0 +1,40 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_HW_CTX_ADAPTER_SERVICE_DCE110_H__
-+#define __DAL_HW_CTX_ADAPTER_SERVICE_DCE110_H__
-+
-+struct hw_ctx_adapter_service_dce110 {
-+ struct hw_ctx_adapter_service base;
-+ uint32_t number_of_connected_audio_endpoints;
-+};
-+
-+struct hw_ctx_adapter_service *
-+ dal_adapter_service_create_hw_ctx_dce110(
-+ struct dc_context *ctx);
-+
-+#endif /* __DAL_HW_CTX_ADAPTER_SERVICE_DCE110_H__ */
-+
-+
-diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/hw_ctx_adapter_service.c b/drivers/gpu/drm/amd/dal/dc/adapter/hw_ctx_adapter_service.c
-new file mode 100644
-index 0000000..5fa886f
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/adapter/hw_ctx_adapter_service.c
-@@ -0,0 +1,164 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+#include "include/adapter_service_types.h"
-+#include "include/grph_object_id.h"
-+#include "hw_ctx_adapter_service.h"
-+
-+static const struct graphics_object_id invalid_go = {
-+ 0, ENUM_ID_UNKNOWN, OBJECT_TYPE_UNKNOWN
-+};
-+
-+static void destroy(
-+ struct hw_ctx_adapter_service *hw_ctx)
-+{
-+ /* Attention!
-+ * You must override impl method in derived class */
-+ BREAK_TO_DEBUGGER();
-+}
-+
-+static bool power_up(
-+ struct hw_ctx_adapter_service *hw_ctx)
-+{
-+ /* Attention!
-+ * You must override impl method in derived class */
-+ BREAK_TO_DEBUGGER();
-+
-+ return false;
-+}
-+
-+static struct graphics_object_id enum_fake_path_resource(
-+ const struct hw_ctx_adapter_service *hw_ctx,
-+ uint32_t index)
-+{
-+ return invalid_go;
-+}
-+
-+static struct graphics_object_id enum_stereo_sync_object(
-+ const struct hw_ctx_adapter_service *hw_ctx,
-+ uint32_t index)
-+{
-+ return invalid_go;
-+}
-+
-+static struct graphics_object_id enum_sync_output_object(
-+ const struct hw_ctx_adapter_service *hw_ctx,
-+ uint32_t index)
-+{
-+ return invalid_go;
-+}
-+
-+static struct graphics_object_id enum_audio_object(
-+ const struct hw_ctx_adapter_service *hw_ctx,
-+ uint32_t index)
-+{
-+ /* by default, we only allow one audio */
-+
-+ if (index > 0)
-+ return invalid_go;
-+ else if (hw_ctx->cached_audio_straps == AUDIO_STRAPS_NOT_ALLOWED)
-+ return invalid_go;
-+ else
-+ return dal_graphics_object_id_init(
-+ AUDIO_ID_INTERNAL_AZALIA,
-+ ENUM_ID_1,
-+ OBJECT_TYPE_AUDIO);
-+}
-+
-+static void update_audio_connectivity(
-+ struct hw_ctx_adapter_service *hw_ctx,
-+ uint32_t number_of_audio_capable_display_path,
-+ uint32_t number_of_controllers)
-+{
-+ /* Attention!
-+ * You must override impl method in derived class */
-+ BREAK_TO_DEBUGGER();
-+}
-+
-+static const struct hw_ctx_adapter_service_funcs funcs = {
-+ destroy,
-+ power_up,
-+ enum_fake_path_resource,
-+ enum_stereo_sync_object,
-+ enum_sync_output_object,
-+ enum_audio_object,
-+ update_audio_connectivity
-+};
-+
-+bool dal_adapter_service_construct_hw_ctx(
-+ struct hw_ctx_adapter_service *hw_ctx,
-+ struct dc_context *ctx)
-+{
-+
-+ hw_ctx->ctx = ctx;
-+ hw_ctx->funcs = &funcs;
-+ hw_ctx->cached_audio_straps = AUDIO_STRAPS_NOT_ALLOWED;
-+
-+ return true;
-+}
-+
-+union audio_support dal_adapter_service_hw_ctx_get_audio_support(
-+ const struct hw_ctx_adapter_service *hw_ctx)
-+{
-+ union audio_support result;
-+
-+ result.raw = 0;
-+
-+ switch (hw_ctx->cached_audio_straps) {
-+ case AUDIO_STRAPS_DP_HDMI_AUDIO:
-+ result.bits.HDMI_AUDIO_NATIVE = true;
-+ /* do not break ! */
-+ case AUDIO_STRAPS_DP_HDMI_AUDIO_ON_DONGLE:
-+ result.bits.HDMI_AUDIO_ON_DONGLE = true;
-+ /* do not break ! */
-+ case AUDIO_STRAPS_DP_AUDIO_ALLOWED:
-+ result.bits.DP_AUDIO = true;
-+ break;
-+ default:
-+ break;
-+ }
-+
-+ return result;
-+}
-+
-+void dal_adapter_service_destruct_hw_ctx(
-+ struct hw_ctx_adapter_service *hw_ctx)
-+{
-+ /* There is nothing to destruct at the moment */
-+}
-+
-+void dal_adapter_service_destroy_hw_ctx(
-+ struct hw_ctx_adapter_service **ptr)
-+{
-+ if (!ptr || !*ptr) {
-+ BREAK_TO_DEBUGGER();
-+ return;
-+ }
-+
-+ (*ptr)->funcs->destroy(*ptr);
-+
-+ *ptr = NULL;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/hw_ctx_adapter_service.h b/drivers/gpu/drm/amd/dal/dc/adapter/hw_ctx_adapter_service.h
-new file mode 100644
-index 0000000..f98c2d4
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/adapter/hw_ctx_adapter_service.h
-@@ -0,0 +1,86 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_HW_CTX_ADAPTER_SERVICE_H__
-+#define __DAL_HW_CTX_ADAPTER_SERVICE_H__
-+
-+enum audio_straps {
-+ AUDIO_STRAPS_NOT_ALLOWED = 0,
-+ AUDIO_STRAPS_DP_AUDIO_ALLOWED,
-+ AUDIO_STRAPS_DP_HDMI_AUDIO_ON_DONGLE,
-+ AUDIO_STRAPS_DP_HDMI_AUDIO
-+};
-+
-+struct hw_ctx_adapter_service;
-+
-+struct hw_ctx_adapter_service_funcs {
-+ void (*destroy)(
-+ struct hw_ctx_adapter_service *hw_ctx);
-+ /* Initializes relevant HW registers
-+ * and caches relevant data from HW registers */
-+ bool (*power_up)(
-+ struct hw_ctx_adapter_service *hw_ctx);
-+ /* Enumerate fake path resources */
-+ struct graphics_object_id (*enum_fake_path_resource)(
-+ const struct hw_ctx_adapter_service *hw_ctx,
-+ uint32_t index);
-+ /* Enumerate stereo sync objects */
-+ struct graphics_object_id (*enum_stereo_sync_object)(
-+ const struct hw_ctx_adapter_service *hw_ctx,
-+ uint32_t index);
-+ /* Enumerate (H/V) sync output objects */
-+ struct graphics_object_id (*enum_sync_output_object)(
-+ const struct hw_ctx_adapter_service *hw_ctx,
-+ uint32_t index);
-+ /* Enumerate audio objects */
-+ struct graphics_object_id (*enum_audio_object)(
-+ const struct hw_ctx_adapter_service *hw_ctx,
-+ uint32_t index);
-+ void (*update_audio_connectivity)(
-+ struct hw_ctx_adapter_service *hw_ctx,
-+ uint32_t number_of_audio_capable_display_path,
-+ uint32_t number_of_controllers);
-+};
-+
-+struct hw_ctx_adapter_service {
-+ struct dc_context *ctx;
-+ const struct hw_ctx_adapter_service_funcs *funcs;
-+ enum audio_straps cached_audio_straps;
-+};
-+
-+bool dal_adapter_service_construct_hw_ctx(
-+ struct hw_ctx_adapter_service *hw_ctx,
-+ struct dc_context *ctx);
-+
-+union audio_support dal_adapter_service_hw_ctx_get_audio_support(
-+ const struct hw_ctx_adapter_service *hw_ctx);
-+
-+void dal_adapter_service_destruct_hw_ctx(
-+ struct hw_ctx_adapter_service *hw_ctx);
-+
-+void dal_adapter_service_destroy_hw_ctx(
-+ struct hw_ctx_adapter_service **ptr);
-+
-+#endif /* __DAL_HW_CTX_ADAPTER_SERVICE_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/wireless_data_source.c b/drivers/gpu/drm/amd/dal/dc/adapter/wireless_data_source.c
-new file mode 100644
-index 0000000..dcb885d
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/adapter/wireless_data_source.c
-@@ -0,0 +1,209 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+
-+#include "dal_services.h"
-+#include "adapter_service.h"
-+#include "wireless_data_source.h"
-+
-+#include "atom.h"
-+
-+/*construct wireless data*/
-+bool wireless_data_init(struct wireless_data *data,
-+ struct bios_parser *bp,
-+ struct wireless_init_data *init_data)
-+{
-+ struct firmware_info info;
-+
-+ if (data == NULL || bp == NULL || init_data == NULL) {
-+ ASSERT_CRITICAL(false);
-+ return false;
-+ }
-+
-+ data->miracast_connector_enable = false;
-+ data->wireless_disp_path_enable = false;
-+ data->wireless_enable = false;
-+
-+ /* Wireless it not supported if VCE is not supported */
-+ if (!init_data->vce_supported)
-+ return true;
-+
-+ if (init_data->miracast_target_required)
-+ data->miracast_connector_enable = true;
-+
-+ /*
-+ * If override is in place for platform support, we will both
-+ * enable wireless display as a feature (i.e. CCC aspect) and
-+ * enable the wireless display path without any further checks.
-+ */
-+ if (init_data->platform_override) {
-+ data->wireless_enable = true;
-+ data->wireless_disp_path_enable = true;
-+ } else {
-+ /*
-+ * Check if SBIOS sets remote display enable, exposed
-+ * through VBIOS. This is only valid for APU, not dGPU
-+ */
-+ dal_bios_parser_get_firmware_info(bp, &info);
-+
-+ if ((REMOTE_DISPLAY_ENABLE ==
-+ info.remote_display_config) &&
-+ init_data->fusion) {
-+ data->wireless_enable = true;
-+ data->wireless_disp_path_enable = true;
-+ }
-+ }
-+
-+ /*
-+ * If remote display path override is enabled, we enable just the
-+ * remote display path. This is mainly used for testing purposes
-+ */
-+ if (init_data->remote_disp_path_override)
-+ data->wireless_disp_path_enable = true;
-+
-+ return true;
-+}
-+
-+uint8_t wireless_get_clocks_num(
-+ struct adapter_service *as)
-+{
-+ if (as->wireless_data.wireless_enable ||
-+ as->wireless_data.wireless_disp_path_enable)
-+ return 1;
-+ else
-+ return 0;
-+}
-+
-+static uint8_t wireless_get_encoders_num(
-+ struct adapter_service *as)
-+{
-+ if (as->wireless_data.wireless_enable ||
-+ as->wireless_data.wireless_disp_path_enable)
-+ return 1;
-+ else
-+ return 0;
-+}
-+
-+uint8_t wireless_get_connectors_num(
-+ struct adapter_service *as)
-+{
-+ uint8_t wireless_connectors_num = 0;
-+
-+ if (as->wireless_data.wireless_enable &&
-+ as->wireless_data.miracast_connector_enable)
-+ wireless_connectors_num++;
-+
-+ if (as->wireless_data.wireless_disp_path_enable)
-+ wireless_connectors_num++;
-+
-+ return wireless_connectors_num;
-+}
-+
-+struct graphics_object_id wireless_get_connector_id(
-+ struct adapter_service *as,
-+ uint8_t index)
-+{
-+ struct graphics_object_id unknown_object_id =
-+ dal_graphics_object_id_init(
-+ 0,
-+ ENUM_ID_UNKNOWN,
-+ OBJECT_TYPE_UNKNOWN);
-+
-+ if (!as->wireless_data.wireless_enable &&
-+ !as->wireless_data.wireless_disp_path_enable)
-+ return unknown_object_id;
-+
-+ else if (!as->wireless_data.miracast_connector_enable)
-+ return dal_graphics_object_id_init(
-+ CONNECTOR_ID_WIRELESS,
-+ ENUM_ID_1,
-+ OBJECT_TYPE_CONNECTOR);
-+
-+ switch (index) {
-+ case 0:
-+ return dal_graphics_object_id_init(
-+ CONNECTOR_ID_WIRELESS,
-+ ENUM_ID_1,
-+ OBJECT_TYPE_CONNECTOR);
-+ break;
-+ case 1:
-+ return dal_graphics_object_id_init(
-+ CONNECTOR_ID_MIRACAST,
-+ ENUM_ID_1,
-+ OBJECT_TYPE_CONNECTOR);
-+ break;
-+ default:
-+ return unknown_object_id;
-+ }
-+}
-+
-+uint8_t wireless_get_srcs_num(
-+ struct adapter_service *as,
-+ struct graphics_object_id id)
-+{
-+ switch (id.type) {
-+ case OBJECT_TYPE_CONNECTOR:
-+ return wireless_get_encoders_num(as);
-+ case OBJECT_TYPE_ENCODER:
-+ return 1;
-+
-+ default:
-+ ASSERT_CRITICAL(false);
-+ break;
-+ }
-+
-+ return 0;
-+}
-+
-+struct graphics_object_id wireless_get_src_obj_id(
-+ struct adapter_service *as,
-+ struct graphics_object_id id,
-+ uint8_t index)
-+{
-+ if (index < wireless_get_srcs_num(as, id)) {
-+ switch (id.type) {
-+ case OBJECT_TYPE_CONNECTOR:
-+ return dal_graphics_object_id_init(
-+ ENCODER_ID_INTERNAL_WIRELESS,
-+ ENUM_ID_1,
-+ OBJECT_TYPE_ENCODER);
-+ break;
-+ case OBJECT_TYPE_ENCODER:
-+ return dal_graphics_object_id_init(
-+ 0,
-+ ENUM_ID_1,
-+ OBJECT_TYPE_GPU);
-+ break;
-+ default:
-+ ASSERT_CRITICAL(false);
-+ break;
-+ }
-+ }
-+
-+ return dal_graphics_object_id_init(
-+ 0,
-+ ENUM_ID_UNKNOWN,
-+ OBJECT_TYPE_UNKNOWN);
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/wireless_data_source.h b/drivers/gpu/drm/amd/dal/dc/adapter/wireless_data_source.h
-new file mode 100644
-index 0000000..54b140a
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/adapter/wireless_data_source.h
-@@ -0,0 +1,80 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_WIRELESS_DATA_SOURCE_H__
-+#define __DAL_WIRELESS_DATA_SOURCE_H__
-+
-+/* Include */
-+#include "include/grph_object_id.h"
-+
-+/*
-+ * Forward declaration
-+ */
-+struct adapter_service;
-+struct bios_parser;
-+
-+/* Wireless data init structure */
-+struct wireless_init_data {
-+ bool fusion; /* Fusion flag */
-+ bool platform_override; /* Override for platform BIOS option */
-+ bool remote_disp_path_override; /* Override enabling wireless path */
-+ bool vce_supported; /* Existence of VCE block on this DCE */
-+ bool miracast_target_required; /* OS requires Miracast target */
-+};
-+
-+/* Wireless data */
-+struct wireless_data {
-+ bool wireless_enable;
-+ bool wireless_disp_path_enable;
-+ bool miracast_connector_enable;
-+};
-+
-+
-+/*construct wireless data*/
-+bool wireless_data_init(
-+ struct wireless_data *data,
-+ struct bios_parser *bp,
-+ struct wireless_init_data *init_data);
-+
-+uint8_t wireless_get_clocks_num(
-+ struct adapter_service *as);
-+
-+uint8_t wireless_get_connectors_num(
-+ struct adapter_service *as);
-+
-+struct graphics_object_id wireless_get_connector_id(
-+ struct adapter_service *as,
-+ uint8_t connector_index);
-+
-+uint8_t wireless_get_srcs_num(
-+ struct adapter_service *as,
-+ struct graphics_object_id id);
-+
-+struct graphics_object_id wireless_get_src_obj_id(
-+ struct adapter_service *as,
-+ struct graphics_object_id id,
-+ uint8_t index);
-+
-+#endif /* __DAL_WIRELESS_DATA_SOURCE_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/asic_capability/Makefile b/drivers/gpu/drm/amd/dal/dc/asic_capability/Makefile
-new file mode 100644
-index 0000000..5e01a86
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/asic_capability/Makefile
-@@ -0,0 +1,23 @@
-+#
-+# Makefile for the 'asic_capability' sub-component of DAL.
-+#
-+
-+ASIC_CAPABILITY = asic_capability.o
-+
-+AMD_DAL_ASIC_CAPABILITY = \
-+ $(addprefix $(AMDDALPATH)/dc/asic_capability/,$(ASIC_CAPABILITY))
-+
-+AMD_DAL_FILES += $(AMD_DAL_ASIC_CAPABILITY)
-+
-+
-+###############################################################################
-+# DCE 11x
-+###############################################################################
-+ifdef CONFIG_DRM_AMD_DAL_DCE11_0
-+ASIC_CAPABILITY_DCE11 = carrizo_asic_capability.o
-+
-+AMD_DAL_ASIC_CAPABILITY_DCE11 = \
-+ $(addprefix $(AMDDALPATH)/dc/asic_capability/,$(ASIC_CAPABILITY_DCE11))
-+
-+AMD_DAL_FILES += $(AMD_DAL_ASIC_CAPABILITY_DCE11)
-+endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/asic_capability/asic_capability.c b/drivers/gpu/drm/amd/dal/dc/asic_capability/asic_capability.c
-new file mode 100644
-index 0000000..a532e2f
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/asic_capability/asic_capability.c
-@@ -0,0 +1,178 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+
-+#include "include/logger_interface.h"
-+
-+#include "include/asic_capability_interface.h"
-+#include "include/asic_capability_types.h"
-+#include "include/dal_types.h"
-+#include "include/dal_asic_id.h"
-+
-+
-+#if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
-+#include "carrizo_asic_capability.h"
-+#endif
-+
-+/*
-+ * Initializes asic_capability instance.
-+ */
-+static bool construct(
-+ struct asic_capability *cap,
-+ struct hw_asic_id *init,
-+ struct dc_context *ctx)
-+{
-+ bool asic_supported = false;
-+
-+ cap->ctx = ctx;
-+ dc_service_memset(cap->data, 0, sizeof(cap->data));
-+
-+ /* ASIC data */
-+ cap->data[ASIC_DATA_VRAM_TYPE] = init->vram_type;
-+ cap->data[ASIC_DATA_VRAM_BITWIDTH] = init->vram_width;
-+ cap->data[ASIC_DATA_FEATURE_FLAGS] = init->feature_flags;
-+ cap->runtime_flags = init->runtime_flags;
-+ cap->data[ASIC_DATA_REVISION_ID] = init->hw_internal_rev;
-+ cap->data[ASIC_DATA_MAX_UNDERSCAN_PERCENTAGE] = 10;
-+ cap->data[ASIC_DATA_VIEWPORT_PIXEL_GRANULARITY] = 4;
-+ cap->data[ASIC_DATA_SUPPORTED_HDMI_CONNECTION_NUM] = 1;
-+ cap->data[ASIC_DATA_NUM_OF_VIDEO_PLANES] = 0;
-+ cap->data[ASIC_DATA_DEFAULT_I2C_SPEED_IN_KHZ] = 25;
-+
-+ /* ASIC basic capability */
-+ cap->caps.UNDERSCAN_FOR_HDMI_ONLY = true;
-+ cap->caps.SUPPORT_CEA861E_FINAL = true;
-+ cap->caps.MIRABILIS_SUPPORTED = false;
-+ cap->caps.MIRABILIS_ENABLED_BY_DEFAULT = false;
-+ cap->caps.WIRELESS_LIMIT_TO_720P = false;
-+ cap->caps.WIRELESS_FULL_TIMING_ADJUSTMENT = false;
-+ cap->caps.WIRELESS_TIMING_ADJUSTMENT = true;
-+ cap->caps.WIRELESS_COMPRESSED_AUDIO = false;
-+ cap->caps.VCE_SUPPORTED = false;
-+ cap->caps.HPD_CHECK_FOR_EDID = false;
-+ cap->caps.NO_VCC_OFF_HPD_POLLING = false;
-+ cap->caps.NEED_MC_TUNING = false;
-+ cap->caps.SUPPORT_8BPP = true;
-+
-+ /* ASIC stereo 3D capability */
-+ cap->stereo_3d_caps.SUPPORTED = true;
-+
-+ switch (init->chip_family) {
-+ case FAMILY_CI:
-+ break;
-+
-+ case FAMILY_KV:
-+ if (ASIC_REV_IS_KALINDI(init->hw_internal_rev) ||
-+ ASIC_REV_IS_BHAVANI(init->hw_internal_rev)) {
-+ } else {
-+ }
-+ break;
-+
-+ case FAMILY_CZ:
-+#if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
-+ carrizo_asic_capability_create(cap, init);
-+ asic_supported = true;
-+#endif
-+ break;
-+
-+ default:
-+ /* unsupported "chip_family" */
-+ break;
-+ }
-+
-+ if (false == asic_supported) {
-+ dal_logger_write(ctx->logger,
-+ LOG_MAJOR_ERROR,
-+ LOG_MINOR_MASK_ALL,
-+ "%s: ASIC not supported!\n", __func__);
-+ }
-+
-+ return asic_supported;
-+}
-+
-+static void destruct(
-+ struct asic_capability *cap)
-+{
-+ /* nothing to do (yet?) */
-+}
-+
-+/*
-+ * dal_asic_capability_create
-+ *
-+ * Creates asic capability based on DCE version.
-+ */
-+struct asic_capability *dal_asic_capability_create(
-+ struct hw_asic_id *init,
-+ struct dc_context *ctx)
-+{
-+ struct asic_capability *cap;
-+
-+ if (!init) {
-+ BREAK_TO_DEBUGGER();
-+ return NULL;
-+ }
-+
-+ cap = dc_service_alloc(ctx, sizeof(struct asic_capability));
-+
-+ if (!cap) {
-+ BREAK_TO_DEBUGGER();
-+ return NULL;
-+ }
-+
-+ if (construct(cap, init, ctx))
-+ return cap;
-+
-+ BREAK_TO_DEBUGGER();
-+
-+ dc_service_free(ctx, cap);
-+
-+ return NULL;
-+}
-+
-+/*
-+ * dal_asic_capability_destroy
-+ *
-+ * Destroy allocated memory.
-+ */
-+void dal_asic_capability_destroy(
-+ struct asic_capability **cap)
-+{
-+ if (!cap) {
-+ BREAK_TO_DEBUGGER();
-+ return;
-+ }
-+
-+ if (!*cap) {
-+ BREAK_TO_DEBUGGER();
-+ return;
-+ }
-+
-+ destruct(*cap);
-+
-+ dc_service_free((*cap)->ctx, *cap);
-+
-+ *cap = NULL;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/asic_capability/carrizo_asic_capability.c b/drivers/gpu/drm/amd/dal/dc/asic_capability/carrizo_asic_capability.c
-new file mode 100644
-index 0000000..f57d3f7
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/asic_capability/carrizo_asic_capability.c
-@@ -0,0 +1,146 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+
-+#include "include/asic_capability_interface.h"
-+#include "include/asic_capability_types.h"
-+
-+#include "carrizo_asic_capability.h"
-+
-+#include "atom.h"
-+#include "dce/dce_11_0_d.h"
-+#include "smu/smu_8_0_d.h"
-+#include "dce/dce_11_0_sh_mask.h"
-+#include "dal_asic_id.h"
-+
-+#define ixVCE_HARVEST_FUSE_MACRO__ADDRESS 0xC0014074
-+
-+/*
-+ * carrizo_asic_capability_create
-+ *
-+ * Create and initiate Carrizo capability.
-+ */
-+void carrizo_asic_capability_create(struct asic_capability *cap,
-+ struct hw_asic_id *init)
-+{
-+ uint32_t e_fuse_setting;
-+ /* ASIC data */
-+ cap->data[ASIC_DATA_CONTROLLERS_NUM] = 3;
-+ cap->data[ASIC_DATA_FUNCTIONAL_CONTROLLERS_NUM] = 3;
-+ cap->data[ASIC_DATA_LINEBUFFER_NUM] = 3;
-+ cap->data[ASIC_DATA_PATH_NUM_PER_DPMST_CONNECTOR] = 4;
-+ cap->data[ASIC_DATA_DCE_VERSION] = 0x110; /* DCE 11 */
-+ cap->data[ASIC_DATA_LINEBUFFER_SIZE] = 1712 * 144;
-+ cap->data[ASIC_DATA_DRAM_BANDWIDTH_EFFICIENCY] = 45;
-+ cap->data[ASIC_DATA_CLOCKSOURCES_NUM] = 2;
-+ cap->data[ASIC_DATA_MC_LATENCY] = 5000;
-+ cap->data[ASIC_DATA_STUTTERMODE] = 0x200A;
-+ cap->data[ASIC_DATA_VIEWPORT_PIXEL_GRANULARITY] = 2;
-+ cap->data[ASIC_DATA_MAX_COFUNC_NONDP_DISPLAYS] = 2;
-+ cap->data[ASIC_DATA_MEMORYTYPE_MULTIPLIER] = 2;
-+ cap->data[ASIC_DATA_DEFAULT_I2C_SPEED_IN_KHZ] = 100;
-+ cap->data[ASIC_DATA_NUM_OF_VIDEO_PLANES] = 1;
-+ cap->data[ASIC_DATA_SUPPORTED_HDMI_CONNECTION_NUM] = 3;
-+
-+ /* ASIC basic capability */
-+ cap->caps.IS_FUSION = true;
-+ cap->caps.DP_MST_SUPPORTED = true;
-+ cap->caps.PANEL_SELF_REFRESH_SUPPORTED = true;
-+ cap->caps.MIRABILIS_SUPPORTED = true;
-+ cap->caps.NO_VCC_OFF_HPD_POLLING = true;
-+ cap->caps.VCE_SUPPORTED = true;
-+ cap->caps.HPD_CHECK_FOR_EDID = true;
-+ cap->caps.DFSBYPASS_DYNAMIC_SUPPORT = true;
-+ cap->caps.SUPPORT_8BPP = false;
-+
-+ /* ASIC stereo 3d capability */
-+ cap->stereo_3d_caps.DISPLAY_BASED_ON_WS = true;
-+ cap->stereo_3d_caps.HDMI_FRAME_PACK = true;
-+ cap->stereo_3d_caps.INTERLACE_FRAME_PACK = true;
-+ cap->stereo_3d_caps.DISPLAYPORT_FRAME_PACK = true;
-+ cap->stereo_3d_caps.DISPLAYPORT_FRAME_ALT = true;
-+ cap->stereo_3d_caps.INTERLEAVE = true;
-+
-+ e_fuse_setting = dal_read_index_reg(cap->ctx,CGS_IND_REG__SMC,ixVCE_HARVEST_FUSE_MACRO__ADDRESS);
-+
-+ /* Bits [28:27]*/
-+ switch ((e_fuse_setting >> 27) & 0x3) {
-+ case 0:
-+ /*both VCE engine are working*/
-+ cap->caps.VCE_SUPPORTED = true;
-+ cap->caps.WIRELESS_TIMING_ADJUSTMENT = false;
-+ /*TODO:
-+ cap->caps.wirelessLowVCEPerformance = false;
-+ m_AsicCaps.vceInstance0Enabled = true;
-+ m_AsicCaps.vceInstance1Enabled = true;*/
-+ cap->caps.NEED_MC_TUNING = true;
-+ break;
-+
-+ case 1:
-+ cap->caps.VCE_SUPPORTED = true;
-+ cap->caps.WIRELESS_TIMING_ADJUSTMENT = true;
-+ /*TODO:
-+ m_AsicCaps.wirelessLowVCEPerformance = false;
-+ m_AsicCaps.vceInstance1Enabled = true;*/
-+ cap->caps.NEED_MC_TUNING = true;
-+ break;
-+
-+ case 2:
-+ cap->caps.VCE_SUPPORTED = true;
-+ cap->caps.WIRELESS_TIMING_ADJUSTMENT = true;
-+ /*TODO:
-+ m_AsicCaps.wirelessLowVCEPerformance = false;
-+ m_AsicCaps.vceInstance0Enabled = true;*/
-+ cap->caps.NEED_MC_TUNING = true;
-+ break;
-+
-+ case 3:
-+ /* VCE_DISABLE = 0x3 - both VCE
-+ * instances are in harvesting,
-+ * no VCE supported any more.
-+ */
-+ cap->caps.VCE_SUPPORTED = false;
-+ break;
-+
-+ default:
-+ break;
-+ }
-+
-+ if (ASIC_REV_IS_STONEY(init->hw_internal_rev))
-+ {
-+ /* Stoney is the same DCE11, but only two pipes, three digs.
-+ * and HW added 64bit back for non SG */
-+ cap->data[ASIC_DATA_CONTROLLERS_NUM] = 2;
-+ cap->data[ASIC_DATA_FUNCTIONAL_CONTROLLERS_NUM] = 2;
-+ cap->data[ASIC_DATA_LINEBUFFER_NUM] = 2;
-+ /*3 DP MST per connector, limited by number of pipe and number
-+ * of Dig.*/
-+ cap->data[ASIC_DATA_PATH_NUM_PER_DPMST_CONNECTOR] = 2;
-+
-+ }
-+
-+
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/asic_capability/carrizo_asic_capability.h b/drivers/gpu/drm/amd/dal/dc/asic_capability/carrizo_asic_capability.h
-new file mode 100644
-index 0000000..d1e9b83
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/asic_capability/carrizo_asic_capability.h
-@@ -0,0 +1,36 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_CARRIZO_ASIC_CAPABILITY_H__
-+#define __DAL_CARRIZO_ASIC_CAPABILITY_H__
-+
-+/* Forward declaration */
-+struct asic_capability;
-+
-+/* Create and initialize Carrizo data */
-+void carrizo_asic_capability_create(struct asic_capability *cap,
-+ struct hw_asic_id *init);
-+
-+#endif /* __DAL_CARRIZO_ASIC_CAPABILITY_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/audio/Makefile b/drivers/gpu/drm/amd/dal/dc/audio/Makefile
-new file mode 100644
-index 0000000..0999372
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/audio/Makefile
-@@ -0,0 +1,22 @@
-+#
-+# Makefile for the 'audio' sub-component of DAL.
-+# It provides the control and status of HW adapter resources,
-+# that are global for the ASIC and sharable between pipes.
-+
-+AUDIO = audio_base.o hw_ctx_audio.o
-+
-+AMD_DAL_AUDIO = $(addprefix $(AMDDALPATH)/dc/audio/,$(AUDIO))
-+
-+AMD_DAL_FILES += $(AMD_DAL_AUDIO)
-+
-+
-+###############################################################################
-+# DCE 11x
-+###############################################################################
-+ifdef CONFIG_DRM_AMD_DAL_DCE11_0
-+AUDIO_DCE11 = audio_dce110.o hw_ctx_audio_dce110.o
-+
-+AMD_DAL_AUDIO_DCE11 = $(addprefix $(AMDDALPATH)/dc/audio/dce110/,$(AUDIO_DCE11))
-+
-+AMD_DAL_FILES += $(AMD_DAL_AUDIO_DCE11)
-+endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/audio/audio.h b/drivers/gpu/drm/amd/dal/dc/audio/audio.h
-new file mode 100644
-index 0000000..ad2dc18
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/audio/audio.h
-@@ -0,0 +1,195 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_AUDIO_H__
-+#define __DAL_AUDIO_H__
-+
-+#include "include/audio_interface.h"
-+#include "hw_ctx_audio.h"
-+#include "include/link_service_types.h"
-+
-+/***** only for hook functions *****/
-+/**
-+ *which will be overwritten by derived audio object.
-+ *audio hw context object is independent object
-+ */
-+
-+struct audio;
-+
-+struct audio_funcs {
-+ /*
-+ *get_object_id
-+ *get_object_type
-+ *enumerate_input_signals
-+ *enumerate_output_signals
-+ *is_input_signal_supported
-+ *is_output_signal_supported
-+ *set_object_properties
-+ *get_object_properties
-+ */
-+
-+ void (*destroy)(struct audio **audio);
-+ /*power_up
-+ *power_down
-+ *release_hw_base
-+ */
-+
-+ /* setup audio */
-+ enum audio_result (*setup)(
-+ struct audio *audio,
-+ struct audio_output *output,
-+ struct audio_info *info);
-+
-+ enum audio_result (*enable_output)(
-+ struct audio *audio,
-+ enum engine_id engine_id,
-+ enum signal_type signal);
-+
-+ enum audio_result (*disable_output)(
-+ struct audio *audio,
-+ enum engine_id engine_id,
-+ enum signal_type signal);
-+
-+ /*enable_azalia_audio_jack_presence
-+ * disable_azalia_audio_jack_presence
-+ */
-+
-+ enum audio_result (*unmute)(
-+ struct audio *audio,
-+ enum engine_id engine_id,
-+ enum signal_type signal);
-+
-+ enum audio_result (*mute)(
-+ struct audio *audio,
-+ enum engine_id engine_id,
-+ enum signal_type signal);
-+
-+ /* SW initialization that cannot be done in constructor. This will
-+ * be done is audio_power_up but is not in audio_interface. It is only
-+ * called by power_up
-+ */
-+ enum audio_result (*initialize)(
-+ struct audio *audio);
-+
-+ /* enable channel splitting mapping */
-+ void (*enable_channel_splitting_mapping)(
-+ struct audio *audio,
-+ enum engine_id engine_id,
-+ enum signal_type signal,
-+ const struct audio_channel_associate_info *audio_mapping,
-+ bool enable);
-+
-+ /* get current multi channel split. */
-+ enum audio_result (*get_channel_splitting_mapping)(
-+ struct audio *audio,
-+ enum engine_id engine_id,
-+ struct audio_channel_associate_info *audio_mapping);
-+
-+ /* set payload value for the unsolicited response */
-+ void (*set_unsolicited_response_payload)(
-+ struct audio *audio,
-+ enum audio_payload payload);
-+
-+ /* Update audio wall clock source */
-+ void (*setup_audio_wall_dto)(
-+ struct audio *audio,
-+ enum signal_type signal,
-+ const struct audio_crtc_info *crtc_info,
-+ const struct audio_pll_info *pll_info);
-+
-+ /* options and features supported by Audio */
-+ struct audio_feature_support (*get_supported_features)(
-+ struct audio *audio);
-+
-+ /*
-+ *check_audio_bandwidth
-+ *write_reg
-+ *read_reg
-+ *enable_gtc_embedding_with_group
-+ *disable_gtc_embedding
-+ *register_interrupt
-+ *unregister_interrupt
-+ *process_interrupt
-+ *create_hw_ctx
-+ *getHwCtx
-+ *setHwCtx
-+ *handle_interrupt
-+ */
-+};
-+
-+struct audio {
-+ /* hook functions. they will be overwritten by specific ASIC */
-+ const struct audio_funcs *funcs;
-+ /* TODO: static struct audio_funcs funcs;*/
-+
-+ /*external structures - get service from external*/
-+ struct graphics_object_id id;
-+ struct adapter_service *adapter_service;
-+ /* audio HW context */
-+ struct hw_ctx_audio *hw_ctx;
-+ struct dc_context *ctx;
-+ /* audio supports input and output signals */
-+ uint32_t input_signals;
-+ uint32_t output_signals;
-+};
-+
-+/* - functions defined by audio.h will be used by audio component only.
-+ * but audio.c also implements some function defined by dal\include
-+ */
-+
-+/* graphics_object_base implemention
-+ * 1.input_signals and output_signals are moved
-+ * into audio object.
-+ *
-+ * 2.Get the Graphics Object ID
-+ *
-+ * Outside audio:
-+ * use dal_graphics_object_id_get_audio_id
-+ * Within audio:
-+ * use audio->go_base.id
-+ *
-+ * 3. Get the Graphics Object Type
-+ *
-+ * use object_id.type
-+ * not function implemented.
-+ * 4. Common Graphics Object Properties
-+ * use object id ->go_properties.multi_path
-+ * not function implemented.
-+ */
-+
-+bool dal_audio_construct_base(
-+ struct audio *audio,
-+ const struct audio_init_data *init_data);
-+
-+void dal_audio_destruct_base(
-+ struct audio *audio);
-+
-+void dal_audio_release_hw_base(
-+ struct audio *audio);
-+
-+#endif /* __DAL_AUDIO__ */
-+
-+
-+
-diff --git a/drivers/gpu/drm/amd/dal/dc/audio/audio_base.c b/drivers/gpu/drm/amd/dal/dc/audio/audio_base.c
-new file mode 100644
-index 0000000..6bac3ed
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/audio/audio_base.c
-@@ -0,0 +1,463 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+
-+#include "include/logger_interface.h"
-+
-+#include "audio.h"
-+#include "hw_ctx_audio.h"
-+
-+#include "dce110/audio_dce110.h"
-+
-+/***** static function : only used within audio.c *****/
-+
-+/* stub for hook functions */
-+static void destroy(
-+ struct audio **audio)
-+{
-+ /*DCE specific, must be implemented in derived*/
-+ BREAK_TO_DEBUGGER();
-+}
-+
-+static enum audio_result setup(
-+ struct audio *audio,
-+ struct audio_output *output,
-+ struct audio_info *info)
-+{
-+ /*DCE specific, must be implemented in derived*/
-+ BREAK_TO_DEBUGGER();
-+ return AUDIO_RESULT_OK;
-+}
-+
-+static enum audio_result enable_output(
-+ struct audio *audio,
-+ enum engine_id engine_id,
-+ enum signal_type signal)
-+{
-+ /*DCE specific, must be implemented in derived*/
-+ BREAK_TO_DEBUGGER();
-+ return AUDIO_RESULT_OK;
-+}
-+
-+static enum audio_result disable_output(
-+ struct audio *audio,
-+ enum engine_id engine_id,
-+ enum signal_type signal)
-+{
-+ /*DCE specific, must be implemented in derived*/
-+ BREAK_TO_DEBUGGER();
-+ return AUDIO_RESULT_OK;
-+}
-+
-+static enum audio_result unmute(
-+ struct audio *audio,
-+ enum engine_id engine_id,
-+ enum signal_type signal)
-+{
-+ /*DCE specific, must be implemented in derived*/
-+ BREAK_TO_DEBUGGER();
-+ return AUDIO_RESULT_OK;
-+}
-+
-+static enum audio_result mute(
-+ struct audio *audio,
-+ enum engine_id engine_id,
-+ enum signal_type signal)
-+{
-+ /*DCE specific, must be implemented in derived*/
-+ BREAK_TO_DEBUGGER();
-+ return AUDIO_RESULT_OK;
-+}
-+
-+static enum audio_result initialize(
-+ struct audio *audio)
-+{
-+ /*DCE specific, must be implemented in derived. Implemeentaion of
-+ *initialize will create audio hw context. create_hw_ctx
-+ */
-+ BREAK_TO_DEBUGGER();
-+ return AUDIO_RESULT_OK;
-+}
-+
-+static void enable_channel_splitting_mapping(
-+ struct audio *audio,
-+ enum engine_id engine_id,
-+ enum signal_type signal,
-+ const struct audio_channel_associate_info *audio_mapping,
-+ bool enable)
-+{
-+ /*DCE specific, must be implemented in derived*/
-+ BREAK_TO_DEBUGGER();
-+}
-+
-+/* get current multi channel split. */
-+static enum audio_result get_channel_splitting_mapping(
-+ struct audio *audio,
-+ enum engine_id engine_id,
-+ struct audio_channel_associate_info *audio_mapping)
-+{
-+ /*DCE specific, must be implemented in derived*/
-+ BREAK_TO_DEBUGGER();
-+ return AUDIO_RESULT_OK;
-+}
-+
-+/* set payload value for the unsolicited response */
-+static void set_unsolicited_response_payload(
-+ struct audio *audio,
-+ enum audio_payload payload)
-+{
-+ /*DCE specific, must be implemented in derived*/
-+ BREAK_TO_DEBUGGER();
-+}
-+
-+/* update audio wall clock source */
-+static void setup_audio_wall_dto(
-+ struct audio *audio,
-+ enum signal_type signal,
-+ const struct audio_crtc_info *crtc_info,
-+ const struct audio_pll_info *pll_info)
-+{
-+ /*DCE specific, must be implemented in derived*/
-+ BREAK_TO_DEBUGGER();
-+}
-+
-+static struct audio_feature_support get_supported_features(struct audio *audio)
-+{
-+ /*DCE specific, must be implemented in derived*/
-+ struct audio_feature_support features;
-+
-+ dc_service_memset(&features, 0, sizeof(features));
-+
-+ features.ENGINE_DIGA = 1;
-+ features.ENGINE_DIGB = 1;
-+
-+ return features;
-+}
-+
-+static const struct audio_funcs audio_funcs = {
-+ .destroy = destroy,
-+ .setup = setup,
-+ .enable_output = enable_output,
-+ .disable_output = disable_output,
-+ .unmute = unmute,
-+ .mute = mute,
-+ .initialize = initialize,
-+ .enable_channel_splitting_mapping =
-+ enable_channel_splitting_mapping,
-+ .get_channel_splitting_mapping =
-+ get_channel_splitting_mapping,
-+ .set_unsolicited_response_payload =
-+ set_unsolicited_response_payload,
-+ .setup_audio_wall_dto = setup_audio_wall_dto,
-+ .get_supported_features = get_supported_features,
-+};
-+
-+/***** SCOPE : declare in audio.h. use within dal-audio. *****/
-+
-+bool dal_audio_construct_base(
-+ struct audio *audio,
-+ const struct audio_init_data *init_data)
-+{
-+ enum signal_type signals = SIGNAL_TYPE_HDMI_TYPE_A;
-+
-+ ASSERT(init_data->as != NULL);
-+
-+ /* base hook functions */
-+ audio->funcs = &audio_funcs;
-+
-+ /*setup pointers to get service from dal service compoenents*/
-+ audio->adapter_service = init_data->as;
-+
-+ audio->ctx = init_data->ctx;
-+
-+ /* save audio endpoint number to identify object creating */
-+ audio->id = init_data->audio_stream_id;
-+
-+ /* Fill supported signals. !!! be aware that android definition is
-+ * already shift to vector.
-+ */
-+ signals |= SIGNAL_TYPE_DISPLAY_PORT;
-+ signals |= SIGNAL_TYPE_DISPLAY_PORT_MST;
-+ signals |= SIGNAL_TYPE_EDP;
-+ signals |= SIGNAL_TYPE_DISPLAY_PORT;
-+ signals |= SIGNAL_TYPE_WIRELESS;
-+
-+ /* Audio supports same set for input and output signals */
-+ audio->input_signals = signals;
-+ audio->output_signals = signals;
-+
-+ return true;
-+}
-+
-+/* except hw_ctx, no other hw need reset. so do nothing */
-+void dal_audio_destruct_base(
-+ struct audio *audio)
-+{
-+}
-+
-+/* Enumerate Graphics Object supported Input/Output Signal Types */
-+uint32_t dal_audio_enumerate_input_signals(
-+ struct audio *audio)
-+{
-+ return audio->input_signals;
-+}
-+
-+uint32_t dal_audio_enumerate_output_signals(
-+ struct audio *audio)
-+{
-+ return audio->output_signals;
-+}
-+
-+/* Check if signal supported by GraphicsObject */
-+bool dal_audio_is_input_signal_supported(
-+ struct audio *audio,
-+ enum signal_type signal)
-+{
-+ return (signal & audio->output_signals) != 0;
-+}
-+
-+bool dal_audio_is_output_signal_supported(
-+ struct audio *audio,
-+ enum signal_type signal)
-+{
-+ return (signal & audio->input_signals) != 0;
-+}
-+
-+/***** SCOPE : declare in dal\include *****/
-+
-+/* audio object creator triage. memory allocate and release will be
-+ * done within dal_audio_create_dcexx
-+ */
-+struct audio *dal_audio_create(
-+ const struct audio_init_data *init_data)
-+{
-+ struct adapter_service *as;
-+
-+ if (init_data->as == NULL)
-+ return NULL;
-+
-+ as = init_data->as;
-+ switch (dal_adapter_service_get_dce_version(as)) {
-+#if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
-+ case DCE_VERSION_11_0:
-+ return dal_audio_create_dce110(init_data);
-+#endif
-+ default:
-+ BREAK_TO_DEBUGGER();
-+ return NULL;
-+ }
-+
-+ return NULL;
-+}
-+
-+/* audio object creator triage.
-+ * memory for "struct audio dal_audio_create_dce8x" allocate
-+ * will happens within dal_audio_dce8x. memory allocate is done
-+ * with dal_audio_create_dce8x. memory release is initiated by
-+ * dal_audio_destroy. It will call hook function which will finially
-+ * used destroy() of dal_audio_dce8x. therefore, no memroy allocate
-+ *and release happen physcially at audio base object.
-+ */
-+void dal_audio_destroy(
-+ struct audio **audio)
-+{
-+ if (!audio || !*audio) {
-+ BREAK_TO_DEBUGGER();
-+ return;
-+ }
-+
-+ (*audio)->funcs->destroy(audio);
-+
-+ *audio = NULL;
-+}
-+
-+const struct graphics_object_id dal_audio_get_graphics_object_id(
-+ const struct audio *audio)
-+{
-+ return audio->id;
-+}
-+
-+/* enable azalia audio endpoint. This function call hw_ctx directly
-+ *not overwitten at audio level.
-+ */
-+enum audio_result dal_audio_enable_azalia_audio_jack_presence(
-+ struct audio *audio,
-+ enum engine_id engine_id)
-+{
-+ audio->hw_ctx->funcs->enable_azalia_audio(audio->hw_ctx, engine_id);
-+ return AUDIO_RESULT_OK;
-+}
-+
-+/* disable azalia audio endpoint. This function call hw_ctx directly
-+ *not overwitten at audio level.
-+ */
-+enum audio_result dal_audio_disable_azalia_audio_jack_presence(
-+ struct audio *audio,
-+ enum engine_id engine_id)
-+{
-+ audio->hw_ctx->funcs->disable_azalia_audio(audio->hw_ctx, engine_id);
-+ return AUDIO_RESULT_OK;
-+}
-+
-+/* get audio bandwidth information. This function call hw_ctx directly
-+ *not overwitten at audio level.
-+ */
-+void dal_audio_check_audio_bandwidth(
-+ struct audio *audio,
-+ const struct audio_crtc_info *info,
-+ uint32_t channel_count,
-+ enum signal_type signal,
-+ union audio_sample_rates *sample_rates)
-+{
-+ dal_hw_ctx_audio_check_audio_bandwidth(
-+ audio->hw_ctx, info, channel_count, signal, sample_rates);
-+}
-+
-+/* DP Audio register write access. This function call hw_ctx directly
-+ * not overwitten at audio level.
-+ */
-+
-+/*assign GTC group and enable GTC value embedding*/
-+void dal_audio_enable_gtc_embedding_with_group(
-+ struct audio *audio,
-+ uint32_t group_num,
-+ uint32_t audio_latency)
-+{
-+ audio->hw_ctx->funcs->enable_gtc_embedding_with_group(
-+ audio->hw_ctx, group_num, audio_latency);
-+}
-+
-+/* disable GTC value embedding */
-+void dal_audio_disable_gtc_embedding(
-+ struct audio *audio)
-+{
-+ audio->hw_ctx->funcs->disable_gtc_embedding(audio->hw_ctx);
-+}
-+
-+/* perform power up sequence (boot up, resume, recovery) */
-+enum audio_result dal_audio_power_up(
-+ struct audio *audio)
-+{
-+ return audio->funcs->initialize(audio);
-+}
-+
-+/* perform power down (shut down, stand by) */
-+enum audio_result dal_audio_power_down(
-+ struct audio *audio)
-+{
-+ return AUDIO_RESULT_OK;
-+}
-+
-+/* setup audio */
-+enum audio_result dal_audio_setup(
-+ struct audio *audio,
-+ struct audio_output *output,
-+ struct audio_info *info)
-+{
-+ return audio->funcs->setup(audio, output, info);
-+}
-+
-+/* enable audio */
-+enum audio_result dal_audio_enable_output(
-+ struct audio *audio,
-+ enum engine_id engine_id,
-+ enum signal_type signal)
-+{
-+ return audio->funcs->enable_output(audio, engine_id, signal);
-+}
-+
-+/* disable audio */
-+enum audio_result dal_audio_disable_output(
-+ struct audio *audio,
-+ enum engine_id engine_id,
-+ enum signal_type signal)
-+{
-+ return audio->funcs->disable_output(audio, engine_id, signal);
-+}
-+
-+/* unmute audio */
-+enum audio_result dal_audio_unmute(
-+ struct audio *audio,
-+ enum engine_id engine_id,
-+ enum signal_type signal)
-+{
-+ return audio->funcs->unmute(audio, engine_id, signal);
-+}
-+
-+/* mute audio */
-+enum audio_result dal_audio_mute(
-+ struct audio *audio,
-+ enum engine_id engine_id,
-+ enum signal_type signal)
-+{
-+ return audio->funcs->mute(audio, engine_id, signal);
-+}
-+
-+/* Enable multi channel split */
-+void dal_audio_enable_channel_splitting_mapping(
-+ struct audio *audio,
-+ enum engine_id engine_id,
-+ enum signal_type signal,
-+ const struct audio_channel_associate_info *audio_mapping,
-+ bool enable)
-+{
-+ audio->funcs->enable_channel_splitting_mapping(
-+ audio, engine_id, signal, audio_mapping, enable);
-+}
-+
-+/* get current multi channel split. */
-+enum audio_result dal_audio_get_channel_splitting_mapping(
-+ struct audio *audio,
-+ enum engine_id engine_id,
-+ struct audio_channel_associate_info *audio_mapping)
-+{
-+ return audio->funcs->get_channel_splitting_mapping(
-+ audio, engine_id, audio_mapping);
-+}
-+
-+/* set payload value for the unsolicited response */
-+void dal_audio_set_unsolicited_response_payload(
-+ struct audio *audio,
-+ enum audio_payload payload)
-+{
-+ audio->funcs->set_unsolicited_response_payload(audio, payload);
-+}
-+
-+/* update audio wall clock source */
-+void dal_audio_setup_audio_wall_dto(
-+ struct audio *audio,
-+ enum signal_type signal,
-+ const struct audio_crtc_info *crtc_info,
-+ const struct audio_pll_info *pll_info)
-+{
-+ audio->funcs->setup_audio_wall_dto(audio, signal, crtc_info, pll_info);
-+}
-+
-+struct audio_feature_support dal_audio_get_supported_features(
-+ struct audio *audio)
-+{
-+ return audio->funcs->get_supported_features(audio);
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/audio/dce110/audio_dce110.c b/drivers/gpu/drm/amd/dal/dc/audio/dce110/audio_dce110.c
-new file mode 100644
-index 0000000..f284870
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/audio/dce110/audio_dce110.c
-@@ -0,0 +1,452 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+#include "include/logger_interface.h"
-+
-+#include "audio_dce110.h"
-+
-+/***** static functions *****/
-+
-+static void destruct(struct audio_dce110 *audio)
-+{
-+ /*release memory allocated for hw_ctx -- allocated is initiated
-+ *by audio_dce110 power_up
-+ *audio->base->hw_ctx = NULL is done within hw-ctx->destroy
-+ */
-+ if (audio->base.hw_ctx)
-+ audio->base.hw_ctx->funcs->destroy(&(audio->base.hw_ctx));
-+
-+ /* reset base_audio_block */
-+ dal_audio_destruct_base(&audio->base);
-+}
-+
-+static void destroy(struct audio **ptr)
-+{
-+ struct audio_dce110 *audio = NULL;
-+
-+ audio = container_of(*ptr, struct audio_dce110, base);
-+
-+ destruct(audio);
-+
-+ /* release memory allocated for audio_dce110*/
-+ dc_service_free((*ptr)->ctx, audio);
-+ *ptr = NULL;
-+}
-+
-+
-+/* The inital call of hook function comes from audio object level.
-+ *The passing object handle "struct audio *audio" point to base object
-+ *already.There is not need to get base object from audio_dce110.
-+ */
-+
-+/**
-+* setup
-+*
-+* @brief
-+* setup Audio HW block, to be called by dal_audio_setup
-+*
-+*/
-+static enum audio_result setup(
-+ struct audio *audio,
-+ struct audio_output *output,
-+ struct audio_info *info)
-+{
-+ switch (output->signal) {
-+ case SIGNAL_TYPE_HDMI_TYPE_A:
-+ /*setup HDMI audio engine*/
-+ audio->hw_ctx->funcs->enable_afmt_clock(
-+ audio->hw_ctx,
-+ output->engine_id,
-+ true);
-+ audio->hw_ctx->funcs->setup_hdmi_audio(
-+ audio->hw_ctx, output->engine_id, &output->crtc_info);
-+
-+ audio->hw_ctx->funcs->setup_azalia(
-+ audio->hw_ctx,
-+ output->engine_id,
-+ output->signal,
-+ &output->crtc_info,
-+ &output->pll_info,
-+ info);
-+ break;
-+
-+ case SIGNAL_TYPE_WIRELESS:
-+ /* setup Azalia block for Wireless Display - This
-+ is different than for wired
-+ displays because there is no
-+ DIG to program.*/
-+ /*TODO:
-+ audio->hw_ctx->funcs->setup_azalia_for_vce(
-+ audio->hw_ctx,
-+ audio->signal,
-+ audio->crtc_info,
-+ info);
-+ */
-+ break;
-+ case SIGNAL_TYPE_DISPLAY_PORT:
-+ case SIGNAL_TYPE_DISPLAY_PORT_MST:
-+ case SIGNAL_TYPE_EDP:
-+ /* setup DP audio engine will be done at enable output */
-+
-+ /* setup Azalia block*/
-+ audio->hw_ctx->funcs->setup_azalia(
-+ audio->hw_ctx,
-+ output->engine_id,
-+ output->signal,
-+ &output->crtc_info,
-+ &output->pll_info,
-+ info);
-+
-+ break;
-+ default:
-+ return AUDIO_RESULT_ERROR;
-+ }
-+
-+ return AUDIO_RESULT_OK;
-+}
-+
-+/**
-+* enable_output
-+*
-+* @brief
-+* enable Audio HW block, to be called by dal_audio_enable_output
-+*/
-+static enum audio_result enable_output(
-+ struct audio *audio,
-+ enum engine_id engine_id,
-+ enum signal_type signal)
-+{
-+ /* enable audio output */
-+ switch (signal) {
-+ case SIGNAL_TYPE_HDMI_TYPE_A:
-+ break;
-+ case SIGNAL_TYPE_DISPLAY_PORT:
-+ case SIGNAL_TYPE_DISPLAY_PORT_MST:
-+ case SIGNAL_TYPE_EDP: {
-+ /* enable AFMT clock before enable audio*/
-+ audio->hw_ctx->funcs->enable_afmt_clock(
-+ audio->hw_ctx, engine_id, true);
-+ /* setup DP audio engine */
-+ audio->hw_ctx->funcs->setup_dp_audio(
-+ audio->hw_ctx, engine_id);
-+ /* enabl DP audio packets will be done at unblank */
-+ audio->hw_ctx->funcs->enable_dp_audio(
-+ audio->hw_ctx, engine_id);
-+ }
-+ break;
-+ case SIGNAL_TYPE_WIRELESS:
-+ /* route audio to VCE block */
-+ audio->hw_ctx->funcs->setup_vce_audio(audio->hw_ctx);
-+ break;
-+ default:
-+ return AUDIO_RESULT_ERROR;
-+ }
-+ return AUDIO_RESULT_OK;
-+}
-+
-+/**
-+* disable_output
-+*
-+* @brief
-+* disable Audio HW block, to be called by dal_audio_disable_output
-+*
-+*/
-+static enum audio_result disable_output(
-+ struct audio *audio,
-+ enum engine_id engine_id,
-+ enum signal_type signal)
-+{
-+ switch (signal) {
-+ case SIGNAL_TYPE_HDMI_TYPE_A:
-+ case SIGNAL_TYPE_WIRELESS:
-+ /* disable HDMI audio */
-+ audio->hw_ctx->
-+ funcs->disable_azalia_audio(
-+ audio->hw_ctx, engine_id);
-+ audio->hw_ctx->
-+ funcs->enable_afmt_clock(
-+ audio->hw_ctx, engine_id,
-+ false);
-+
-+ break;
-+ case SIGNAL_TYPE_DISPLAY_PORT:
-+ case SIGNAL_TYPE_DISPLAY_PORT_MST:
-+ case SIGNAL_TYPE_EDP: {
-+ /* disable DP audio */
-+ audio->hw_ctx->funcs->disable_dp_audio(
-+ audio->hw_ctx, engine_id);
-+ audio->hw_ctx->funcs->disable_azalia_audio(
-+ audio->hw_ctx, engine_id);
-+ audio->hw_ctx->funcs->enable_afmt_clock(
-+ audio->hw_ctx, engine_id, false);
-+ }
-+ break;
-+ default:
-+ return AUDIO_RESULT_ERROR;
-+ }
-+
-+ return AUDIO_RESULT_OK;
-+}
-+
-+/**
-+* unmute
-+*
-+* @brief
-+* unmute audio, to be called by dal_audio_unmute
-+*
-+*/
-+static enum audio_result unmute(
-+ struct audio *audio,
-+ enum engine_id engine_id,
-+ enum signal_type signal)
-+{
-+ switch (signal) {
-+ case SIGNAL_TYPE_HDMI_TYPE_A:
-+ case SIGNAL_TYPE_DISPLAY_PORT:
-+ case SIGNAL_TYPE_DISPLAY_PORT_MST:
-+ case SIGNAL_TYPE_EDP:
-+ /* unmute Azalia audio */
-+ audio->hw_ctx->funcs->unmute_azalia_audio(
-+ audio->hw_ctx, engine_id);
-+ break;
-+ case SIGNAL_TYPE_WIRELESS:
-+ /*Do nothing for wireless display*/
-+ break;
-+ default:
-+ return AUDIO_RESULT_ERROR;
-+ }
-+ return AUDIO_RESULT_OK;
-+}
-+
-+/**
-+* mute
-+*
-+* @brief
-+* mute audio, to be called by dal_audio_nmute
-+*
-+*/
-+static enum audio_result mute(
-+ struct audio *audio,
-+ enum engine_id engine_id,
-+ enum signal_type signal)
-+{
-+ switch (signal) {
-+ case SIGNAL_TYPE_HDMI_TYPE_A:
-+ case SIGNAL_TYPE_DISPLAY_PORT:
-+ case SIGNAL_TYPE_DISPLAY_PORT_MST:
-+ case SIGNAL_TYPE_EDP:
-+ /* mute Azalia audio */
-+ audio->hw_ctx->funcs->mute_azalia_audio(
-+ audio->hw_ctx, engine_id);
-+ break;
-+ case SIGNAL_TYPE_WIRELESS:
-+ /*Do nothing for wireless display*/
-+ break;
-+ default:
-+ return AUDIO_RESULT_ERROR;
-+ }
-+ return AUDIO_RESULT_OK;
-+}
-+
-+/**
-+* initialize
-+*
-+* @brief
-+* Perform SW initialization - create audio hw context. Then do HW
-+* initialization. this function is called at dal_audio_power_up.
-+*
-+*/
-+static enum audio_result initialize(
-+ struct audio *audio)
-+{
-+ uint8_t audio_endpoint_enum_id = 0;
-+
-+ audio_endpoint_enum_id = audio->id.enum_id;
-+
-+ /* HW CTX already create*/
-+ if (audio->hw_ctx != NULL)
-+ return AUDIO_RESULT_OK;
-+
-+ audio->hw_ctx = dal_hw_ctx_audio_dce110_create(
-+ audio->ctx,
-+ audio_endpoint_enum_id);
-+
-+ if (audio->hw_ctx == NULL)
-+ return AUDIO_RESULT_ERROR;
-+
-+ /* override HW default settings */
-+ audio->hw_ctx->funcs->hw_initialize(audio->hw_ctx);
-+
-+ return AUDIO_RESULT_OK;
-+}
-+
-+/* enable multi channel split */
-+static void enable_channel_splitting_mapping(
-+ struct audio *audio,
-+ enum engine_id engine_id,
-+ enum signal_type signal,
-+ const struct audio_channel_associate_info *audio_mapping,
-+ bool enable)
-+{
-+ audio->hw_ctx->funcs->setup_channel_splitting_mapping(
-+ audio->hw_ctx,
-+ engine_id,
-+ signal,
-+ audio_mapping, enable);
-+}
-+
-+/* get current multi channel split. */
-+static enum audio_result get_channel_splitting_mapping(
-+ struct audio *audio,
-+ enum engine_id engine_id,
-+ struct audio_channel_associate_info *audio_mapping)
-+{
-+ if (audio->hw_ctx->funcs->get_channel_splitting_mapping(
-+ audio->hw_ctx, engine_id, audio_mapping)) {
-+ return AUDIO_RESULT_OK;
-+ } else {
-+ return AUDIO_RESULT_ERROR;
-+ }
-+}
-+
-+/**
-+* set_unsolicited_response_payload
-+*
-+* @brief
-+* Set payload value for the unsolicited response
-+*/
-+static void set_unsolicited_response_payload(
-+ struct audio *audio,
-+ enum audio_payload payload)
-+{
-+ audio->hw_ctx->funcs->set_unsolicited_response_payload(
-+ audio->hw_ctx, payload);
-+}
-+
-+/**
-+* setup_audio_wall_dto
-+*
-+* @brief
-+* Update audio source clock from hardware context.
-+*
-+*/
-+static void setup_audio_wall_dto(
-+ struct audio *audio,
-+ enum signal_type signal,
-+ const struct audio_crtc_info *crtc_info,
-+ const struct audio_pll_info *pll_info)
-+{
-+ audio->hw_ctx->funcs->setup_audio_wall_dto(
-+ audio->hw_ctx, signal, crtc_info, pll_info);
-+}
-+
-+/**
-+* get_supported_features
-+*
-+* @brief
-+* options and features supported by Audio
-+* returns supported engines, signals.
-+* features are reported for HW audio/Azalia block rather then Audio object
-+* itself the difference for DCE6.x is that MultiStream Audio is now supported
-+*
-+*/
-+static struct audio_feature_support get_supported_features(struct audio *audio)
-+{
-+ struct audio_feature_support afs = {0};
-+
-+ afs.ENGINE_DIGA = 1;
-+ afs.ENGINE_DIGB = 1;
-+ afs.ENGINE_DIGC = 1;
-+ afs.MULTISTREAM_AUDIO = 1;
-+
-+ return afs;
-+}
-+
-+static const struct audio_funcs funcs = {
-+ .destroy = destroy,
-+ .setup = setup,
-+ .enable_output = enable_output,
-+ .disable_output = disable_output,
-+ .unmute = unmute,
-+ .mute = mute,
-+ .initialize = initialize,
-+ .enable_channel_splitting_mapping =
-+ enable_channel_splitting_mapping,
-+ .get_channel_splitting_mapping =
-+ get_channel_splitting_mapping,
-+ .set_unsolicited_response_payload =
-+ set_unsolicited_response_payload,
-+ .setup_audio_wall_dto = setup_audio_wall_dto,
-+ .get_supported_features = get_supported_features,
-+};
-+
-+static bool construct(
-+ struct audio_dce110 *audio,
-+ const struct audio_init_data *init_data)
-+{
-+ struct audio *base = &audio->base;
-+
-+ /* base audio construct*/
-+ if (!dal_audio_construct_base(base, init_data))
-+ return false;
-+
-+ /*vtable methods*/
-+ base->funcs = &funcs;
-+ return true;
-+}
-+
-+
-+/* --- audio scope functions --- */
-+
-+struct audio *dal_audio_create_dce110(
-+ const struct audio_init_data *init_data)
-+{
-+ /*allocate memory for audio_dce110 */
-+ struct audio_dce110 *audio = dc_service_alloc(init_data->ctx, sizeof(*audio));
-+
-+ if (audio == NULL) {
-+ ASSERT_CRITICAL(audio);
-+ return NULL;
-+ }
-+ /*pointer to base_audio_block of audio_dce110 ==> audio base object */
-+ if (construct(audio, init_data))
-+ return &audio->base;
-+
-+ dal_logger_write(
-+ init_data->ctx->logger,
-+ LOG_MAJOR_ERROR,
-+ LOG_MINOR_COMPONENT_AUDIO,
-+ "Failed to create audio object for DCE11\n");
-+
-+ /*release memory allocated if fail */
-+ dc_service_free(init_data->ctx, audio);
-+ return NULL;
-+}
-+
-+/* Do not need expose construct_dce110 and destruct_dce110 becuase there is
-+ *derived object after dce110
-+ */
-+
-diff --git a/drivers/gpu/drm/amd/dal/dc/audio/dce110/audio_dce110.h b/drivers/gpu/drm/amd/dal/dc/audio/dce110/audio_dce110.h
-new file mode 100644
-index 0000000..e5ff823
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/audio/dce110/audio_dce110.h
-@@ -0,0 +1,42 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+#ifndef __DAL_AUDIO_DCE_110_H__
-+#define __DAL_AUDIO_DCE_110_H__
-+
-+#include "audio/audio.h"
-+#include "audio/hw_ctx_audio.h"
-+#include "audio/dce110/hw_ctx_audio_dce110.h"
-+
-+
-+
-+struct audio_dce110 {
-+ struct audio base;
-+ /* dce-specific members are following */
-+ /* none */
-+};
-+
-+struct audio *dal_audio_create_dce110(const struct audio_init_data *init_data);
-+
-+#endif /*__DAL_AUDIO_DCE_110_H__*/
-diff --git a/drivers/gpu/drm/amd/dal/dc/audio/dce110/hw_ctx_audio_dce110.c b/drivers/gpu/drm/amd/dal/dc/audio/dce110/hw_ctx_audio_dce110.c
-new file mode 100644
-index 0000000..a13b2ab
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/audio/dce110/hw_ctx_audio_dce110.c
-@@ -0,0 +1,1929 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+#include "include/logger_interface.h"
-+#include "../hw_ctx_audio.h"
-+#include "hw_ctx_audio_dce110.h"
-+
-+#include "dce/dce_11_0_d.h"
-+#include "dce/dce_11_0_sh_mask.h"
-+
-+#define FROM_BASE(ptr) \
-+ container_of((ptr), struct hw_ctx_audio_dce110, base)
-+
-+#define DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT 0x8000
-+#define DP_AUDIO_DTO_MODULE_WITHOUT_SS 360
-+#define DP_AUDIO_DTO_PHASE_WITHOUT_SS 24
-+
-+#define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUDIO_FRONT_END 0
-+#define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC 1
-+#define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__REGISTER_PROGRAMMABLE 2
-+
-+#define FIRST_AUDIO_STREAM_ID 1
-+
-+#define NOT_IMPLEMENTED() DAL_LOGGER_NOT_IMPL(LOG_MINOR_COMPONENT_AUDIO, \
-+ "Audio:%s()\n", __func__)
-+
-+static const uint32_t engine_offset[] = {
-+ 0,
-+ mmDIG1_DIG_FE_CNTL - mmDIG0_DIG_FE_CNTL,
-+ mmDIG2_DIG_FE_CNTL - mmDIG0_DIG_FE_CNTL,
-+ mmDIG3_DIG_FE_CNTL - mmDIG0_DIG_FE_CNTL
-+};
-+
-+static void destruct(
-+ struct hw_ctx_audio_dce110 *hw_ctx_dce110)
-+{
-+ dal_audio_destruct_hw_ctx_audio(&hw_ctx_dce110->base);
-+}
-+
-+static void destroy(
-+ struct hw_ctx_audio **ptr)
-+{
-+ struct hw_ctx_audio_dce110 *hw_ctx_dce110;
-+
-+ hw_ctx_dce110 = container_of(
-+ *ptr, struct hw_ctx_audio_dce110, base);
-+
-+ destruct(hw_ctx_dce110);
-+ /* release memory allocated for struct hw_ctx_audio_dce110 */
-+ dc_service_free((*ptr)->ctx, hw_ctx_dce110);
-+
-+ *ptr = NULL;
-+}
-+
-+/* --- helpers --- */
-+static void write_indirect_azalia_reg(
-+ const struct hw_ctx_audio *hw_ctx,
-+ uint32_t reg_index,
-+ uint32_t reg_data)
-+{
-+ uint32_t addr = 0;
-+ uint32_t value = 0;
-+ /* AZALIA_F0_CODEC_ENDPOINT_INDEX endpoint index */
-+ {
-+ addr =
-+ FROM_BASE(hw_ctx)->az_mm_reg_offsets.
-+ azf0endpointx_azalia_f0_codec_endpoint_index;
-+
-+ set_reg_field_value(value, reg_index,
-+ AZALIA_F0_CODEC_ENDPOINT_INDEX,
-+ AZALIA_ENDPOINT_REG_INDEX);
-+
-+ dal_write_reg(hw_ctx->ctx, addr, value);
-+ }
-+
-+ /* AZALIA_F0_CODEC_ENDPOINT_DATA endpoint data */
-+ {
-+ addr =
-+ FROM_BASE(hw_ctx)->az_mm_reg_offsets.
-+ azf0endpointx_azalia_f0_codec_endpoint_data;
-+
-+ value = 0;
-+ set_reg_field_value(value, reg_data,
-+ AZALIA_F0_CODEC_ENDPOINT_DATA,
-+ AZALIA_ENDPOINT_REG_DATA);
-+ dal_write_reg(hw_ctx->ctx, addr, value);
-+ }
-+
-+ dal_logger_write(
-+ hw_ctx->ctx->logger,
-+ LOG_MAJOR_HW_TRACE,
-+ LOG_MINOR_HW_TRACE_AUDIO,
-+ "AUDIO:write_indirect_azalia_reg: index: %u data: %u\n",
-+ reg_index, reg_data);
-+}
-+
-+static uint32_t read_indirect_azalia_reg(
-+ const struct hw_ctx_audio *hw_ctx,
-+ uint32_t reg_index)
-+{
-+ uint32_t ret_val = 0;
-+ uint32_t addr = 0;
-+ uint32_t value = 0;
-+
-+
-+ /* AZALIA_F0_CODEC_ENDPOINT_INDEX endpoint index */
-+ {
-+ addr =
-+ FROM_BASE(hw_ctx)->az_mm_reg_offsets.
-+ azf0endpointx_azalia_f0_codec_endpoint_index;
-+
-+ set_reg_field_value(value, reg_index,
-+ AZALIA_F0_CODEC_ENDPOINT_INDEX,
-+ AZALIA_ENDPOINT_REG_INDEX);
-+
-+ dal_write_reg(hw_ctx->ctx, addr, value);
-+ }
-+
-+ /* AZALIA_F0_CODEC_ENDPOINT_DATA endpoint data */
-+ {
-+ addr =
-+ FROM_BASE(hw_ctx)->az_mm_reg_offsets.
-+ azf0endpointx_azalia_f0_codec_endpoint_data;
-+
-+ value = dal_read_reg(hw_ctx->ctx, addr);
-+ ret_val = value;
-+ }
-+
-+ dal_logger_write(
-+ hw_ctx->ctx->logger,
-+ LOG_MAJOR_HW_TRACE,
-+ LOG_MINOR_HW_TRACE_AUDIO,
-+ "AUDIO:read_indirect_azalia_reg: index: %u data: %u\n",
-+ reg_index, ret_val);
-+
-+ return ret_val;
-+}
-+
-+/* expose/not expose HBR capability to Audio driver */
-+static void set_high_bit_rate_capable(
-+ const struct hw_ctx_audio *hw_ctx,
-+ bool capable)
-+{
-+ uint32_t value = 0;
-+
-+ /* set high bit rate audio capable*/
-+ value = read_indirect_azalia_reg(
-+ hw_ctx,
-+ ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR);
-+
-+ set_reg_field_value(value, capable,
-+ AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR,
-+ HBR_CAPABLE);
-+
-+ write_indirect_azalia_reg(
-+ hw_ctx,
-+ ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR,
-+ value);
-+}
-+
-+/* set HBR channnel count *
-+static void set_hbr_channel_count(
-+ const struct hw_ctx_audio *hw_ctx,
-+ uint32_t hbr_channel_count)
-+{
-+ uint32_t value = 0;
-+
-+ if (hbr_channel_count > 7)
-+ return;
-+
-+ value = dal_read_reg(hw_ctx->ctx,
-+ mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL);
-+
-+ set_reg_field_value(value, hbr_channel_count,
-+ AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL,
-+ HBR_CHANNEL_COUNT);
-+
-+ dal_write_reg(hw_ctx->ctx,
-+ mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL, value);
-+
-+}
-+
-+*set compressed audio channel count *
-+static void set_compressed_audio_channel_count(
-+ const struct hw_ctx_audio *hw_ctx,
-+ uint32_t compressed_audio_ch_count)
-+{
-+ uint32_t value = 0;
-+ if (compressed_audio_ch_count > 7)
-+ return;
-+
-+ value = dal_read_reg(hw_ctx->ctx,
-+ mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL);
-+
-+ set_reg_field_value(value, compressed_audio_ch_count,
-+ AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL,
-+ COMPRESSED_CHANNEL_COUNT);
-+
-+ dal_write_reg(hw_ctx->ctx,
-+ mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL,
-+ value);
-+
-+}
-+*/
-+/* set video latency in in ms/2+1 */
-+static void set_video_latency(
-+ const struct hw_ctx_audio *hw_ctx,
-+ int latency_in_ms)
-+{
-+ uint32_t value = 0;
-+
-+ if ((latency_in_ms < 0) || (latency_in_ms > 255))
-+ return;
-+
-+
-+ value = read_indirect_azalia_reg(
-+ hw_ctx,
-+ ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC);
-+
-+ set_reg_field_value(value, latency_in_ms,
-+ AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
-+ VIDEO_LIPSYNC);
-+
-+ write_indirect_azalia_reg(
-+ hw_ctx,
-+ ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
-+ value);
-+
-+}
-+
-+/* set audio latency in in ms/2+1 */
-+static void set_audio_latency(
-+ const struct hw_ctx_audio *hw_ctx,
-+ int latency_in_ms)
-+{
-+ uint32_t value = 0;
-+
-+ if (latency_in_ms < 0)
-+ latency_in_ms = 0;
-+
-+ if (latency_in_ms > 255)
-+ latency_in_ms = 255;
-+
-+ value = read_indirect_azalia_reg(
-+ hw_ctx,
-+ ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC);
-+
-+ set_reg_field_value(value, latency_in_ms,
-+ AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
-+ AUDIO_LIPSYNC);
-+
-+ write_indirect_azalia_reg(
-+ hw_ctx,
-+ ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
-+ value);
-+
-+}
-+
-+/* enable HW/SW Sync */
-+/*static void enable_hw_sw_sync(
-+ const struct hw_ctx_audio *hw_ctx)
-+{
-+ union AZALIA_CYCLIC_BUFFER_SYNC value;
-+
-+ value = dal_read_reg(mmAZALIA_CYCLIC_BUFFER_SYNC);
-+ value.bits.CYCLIC_BUFFER_SYNC_ENABLE = 1;
-+ dal_write_reg(mmAZALIA_CYCLIC_BUFFER_SYNC, value);
-+}*/
-+
-+/* disable HW/SW Sync */
-+/*static void disable_hw_sw_sync(
-+ const struct hw_ctx_audio *hw_ctx)
-+{
-+ union AZALIA_CYCLIC_BUFFER_SYNC value;
-+
-+ value = dal_read_reg(
-+ mmAZALIA_CYCLIC_BUFFER_SYNC);
-+ value.bits.CYCLIC_BUFFER_SYNC_ENABLE = 0;
-+ dal_write_reg(
-+ mmAZALIA_CYCLIC_BUFFER_SYNC, value);
-+}*/
-+
-+/* update hardware with software's current position in cyclic buffer */
-+/*static void update_sw_write_ptr(
-+ const struct hw_ctx_audio *hw_ctx,
-+ uint32_t offset)
-+{
-+ union AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER value;
-+
-+ value = dal_read_reg(
-+ mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER);
-+ value.bits.APPLICATION_POSITION_IN_CYCLIC_BUFFER = offset;
-+ dal_write_reg(
-+ mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER,
-+ value);
-+}*/
-+
-+/* update Audio/Video association */
-+/*static void update_av_association(
-+ const struct hw_ctx_audio *hw_ctx,
-+ enum engine_id engine_id,
-+ enum signal_type signal,
-+ uint32_t displayId)
-+{
-+
-+}*/
-+
-+/* --- hook functions --- */
-+static bool get_azalia_clock_info_hdmi(
-+ const struct hw_ctx_audio *hw_ctx,
-+ uint32_t crtc_pixel_clock_in_khz,
-+ uint32_t actual_pixel_clock_in_khz,
-+ struct azalia_clock_info *azalia_clock_info);
-+
-+static bool get_azalia_clock_info_dp(
-+ const struct hw_ctx_audio *hw_ctx,
-+ uint32_t requested_pixel_clock_in_khz,
-+ const struct audio_pll_info *pll_info,
-+ struct azalia_clock_info *azalia_clock_info);
-+
-+static void setup_audio_wall_dto(
-+ const struct hw_ctx_audio *hw_ctx,
-+ enum signal_type signal,
-+ const struct audio_crtc_info *crtc_info,
-+ const struct audio_pll_info *pll_info)
-+{
-+ struct azalia_clock_info clock_info = { 0 };
-+
-+ uint32_t value = dal_read_reg(hw_ctx->ctx, mmDCCG_AUDIO_DTO_SOURCE);
-+
-+ /* TODO: GraphicsObject\inc\GraphicsObjectDefs.hpp(131):
-+ *inline bool isHdmiSignal(SignalType signal)
-+ *if (Signals::isHdmiSignal(signal))
-+ */
-+ if (dc_is_hdmi_signal(signal)) {
-+ /*DTO0 Programming goal:
-+ -generate 24MHz, 128*Fs from 24MHz
-+ -use DTO0 when an active HDMI port is connected
-+ (optionally a DP is connected) */
-+
-+ /* calculate DTO settings */
-+ get_azalia_clock_info_hdmi(
-+ hw_ctx,
-+ crtc_info->requested_pixel_clock,
-+ crtc_info->calculated_pixel_clock,
-+ &clock_info);
-+
-+ /* On TN/SI, Program DTO source select and DTO select before
-+ programming DTO modulo and DTO phase. These bits must be
-+ programmed first, otherwise there will be no HDMI audio at boot
-+ up. This is a HW sequence change (different from old ASICs).
-+ Caution when changing this programming sequence.
-+
-+ HDMI enabled, using DTO0
-+ program master CRTC for DTO0 */
-+ {
-+ set_reg_field_value(value,
-+ pll_info->dto_source - DTO_SOURCE_ID0,
-+ DCCG_AUDIO_DTO_SOURCE,
-+ DCCG_AUDIO_DTO0_SOURCE_SEL);
-+
-+ set_reg_field_value(value,
-+ 0,
-+ DCCG_AUDIO_DTO_SOURCE,
-+ DCCG_AUDIO_DTO_SEL);
-+
-+ dal_write_reg(hw_ctx->ctx,
-+ mmDCCG_AUDIO_DTO_SOURCE, value);
-+ }
-+
-+ /* module */
-+ {
-+ value = dal_read_reg(hw_ctx->ctx,
-+ mmDCCG_AUDIO_DTO0_MODULE);
-+ set_reg_field_value(value,
-+ clock_info.audio_dto_module,
-+ DCCG_AUDIO_DTO0_MODULE,
-+ DCCG_AUDIO_DTO0_MODULE);
-+ dal_write_reg(hw_ctx->ctx,
-+ mmDCCG_AUDIO_DTO0_MODULE, value);
-+ }
-+
-+ /* phase */
-+ {
-+ value = 0;
-+
-+ value = dal_read_reg(hw_ctx->ctx,
-+ mmDCCG_AUDIO_DTO0_PHASE);
-+ set_reg_field_value(value,
-+ clock_info.audio_dto_phase,
-+ DCCG_AUDIO_DTO0_PHASE,
-+ DCCG_AUDIO_DTO0_PHASE);
-+
-+ dal_write_reg(hw_ctx->ctx,
-+ mmDCCG_AUDIO_DTO0_PHASE, value);
-+ }
-+
-+ } else {
-+ /*DTO1 Programming goal:
-+ -generate 24MHz, 512*Fs, 128*Fs from 24MHz
-+ -default is to used DTO1, and switch to DTO0 when an audio
-+ master HDMI port is connected
-+ -use as default for DP
-+
-+ calculate DTO settings */
-+ get_azalia_clock_info_dp(
-+ hw_ctx,
-+ crtc_info->requested_pixel_clock,
-+ pll_info,
-+ &clock_info);
-+
-+ /* Program DTO select before programming DTO modulo and DTO
-+ phase. default to use DTO1 */
-+
-+ {
-+ set_reg_field_value(value, 1,
-+ DCCG_AUDIO_DTO_SOURCE,
-+ DCCG_AUDIO_DTO_SEL);
-+ /*dal_write_reg(mmDCCG_AUDIO_DTO_SOURCE, value)*/
-+
-+ /* Select 512fs for DP TODO: web register definition
-+ does not match register header file
-+ set_reg_field_value(value, 1,
-+ DCCG_AUDIO_DTO_SOURCE,
-+ DCCG_AUDIO_DTO2_USE_512FBR_DTO);
-+ */
-+
-+ dal_write_reg(hw_ctx->ctx,
-+ mmDCCG_AUDIO_DTO_SOURCE, value);
-+ }
-+
-+ /* module */
-+ {
-+ value = 0;
-+
-+ value = dal_read_reg(hw_ctx->ctx,
-+ mmDCCG_AUDIO_DTO1_MODULE);
-+
-+ set_reg_field_value(value,
-+ clock_info.audio_dto_module,
-+ DCCG_AUDIO_DTO1_MODULE,
-+ DCCG_AUDIO_DTO1_MODULE);
-+
-+ dal_write_reg(hw_ctx->ctx,
-+ mmDCCG_AUDIO_DTO1_MODULE, value);
-+ }
-+
-+ /* phase */
-+ {
-+ value = 0;
-+
-+ value = dal_read_reg(hw_ctx->ctx,
-+ mmDCCG_AUDIO_DTO1_PHASE);
-+
-+ set_reg_field_value(value,
-+ clock_info.audio_dto_phase,
-+ DCCG_AUDIO_DTO1_PHASE,
-+ DCCG_AUDIO_DTO1_PHASE);
-+
-+ dal_write_reg(hw_ctx->ctx,
-+ mmDCCG_AUDIO_DTO1_PHASE, value);
-+ }
-+
-+ /* DAL2 code separate DCCG_AUDIO_DTO_SEL and
-+ DCCG_AUDIO_DTO2_USE_512FBR_DTO programming into two different
-+ location. merge together should not hurt */
-+ /*value.bits.DCCG_AUDIO_DTO2_USE_512FBR_DTO = 1;
-+ dal_write_reg(mmDCCG_AUDIO_DTO_SOURCE, value);*/
-+ }
-+}
-+
-+/* setup HDMI audio */
-+static void setup_hdmi_audio(
-+ const struct hw_ctx_audio *hw_ctx,
-+ enum engine_id engine_id,
-+ const struct audio_crtc_info *crtc_info)
-+{
-+ struct audio_clock_info audio_clock_info = {0};
-+ uint32_t max_packets_per_line;
-+ uint32_t addr = 0;
-+ uint32_t value = 0;
-+
-+ /* For now still do calculation, although this field is ignored when
-+ above HDMI_PACKET_GEN_VERSION set to 1 */
-+ max_packets_per_line =
-+ dal_audio_hw_ctx_calc_max_audio_packets_per_line(
-+ hw_ctx,
-+ crtc_info);
-+
-+ /* HDMI_AUDIO_PACKET_CONTROL */
-+ {
-+ addr =
-+ mmHDMI_AUDIO_PACKET_CONTROL + engine_offset[engine_id];
-+
-+ value = dal_read_reg(hw_ctx->ctx, addr);
-+
-+ set_reg_field_value(value, max_packets_per_line,
-+ HDMI_AUDIO_PACKET_CONTROL,
-+ HDMI_AUDIO_PACKETS_PER_LINE);
-+ /* still apply RS600's default setting which is 1. */
-+ set_reg_field_value(value, 1,
-+ HDMI_AUDIO_PACKET_CONTROL,
-+ HDMI_AUDIO_DELAY_EN);
-+
-+ dal_write_reg(hw_ctx->ctx, addr, value);
-+ }
-+
-+ /* AFMT_AUDIO_PACKET_CONTROL */
-+ {
-+ addr = mmAFMT_AUDIO_PACKET_CONTROL + engine_offset[engine_id];
-+
-+ value = dal_read_reg(hw_ctx->ctx, addr);
-+
-+ set_reg_field_value(value, 1,
-+ AFMT_AUDIO_PACKET_CONTROL,
-+ AFMT_60958_CS_UPDATE);
-+
-+ dal_write_reg(hw_ctx->ctx, addr, value);
-+ }
-+
-+ /* AFMT_AUDIO_PACKET_CONTROL2 */
-+ {
-+ addr = mmAFMT_AUDIO_PACKET_CONTROL2 + engine_offset[engine_id];
-+
-+ value = dal_read_reg(hw_ctx->ctx, addr);
-+
-+ set_reg_field_value(value, 0,
-+ AFMT_AUDIO_PACKET_CONTROL2,
-+ AFMT_AUDIO_LAYOUT_OVRD);
-+
-+ /*Register field changed.*/
-+ set_reg_field_value(value, 0,
-+ AFMT_AUDIO_PACKET_CONTROL2,
-+ AFMT_60958_OSF_OVRD);
-+
-+ dal_write_reg(hw_ctx->ctx, addr, value);
-+ }
-+
-+ /* HDMI_ACR_PACKET_CONTROL */
-+ {
-+ addr = mmHDMI_ACR_PACKET_CONTROL + engine_offset[engine_id];
-+
-+ value = dal_read_reg(hw_ctx->ctx, addr);
-+ set_reg_field_value(value, 1,
-+ HDMI_ACR_PACKET_CONTROL,
-+ HDMI_ACR_AUTO_SEND);
-+
-+ /* Set HDMI_ACR_SOURCE to 0, to use hardwre
-+ * computed CTS values.*/
-+ set_reg_field_value(value, 0,
-+ HDMI_ACR_PACKET_CONTROL,
-+ HDMI_ACR_SOURCE);
-+
-+ /* For now clear HDMI_ACR_AUDIO_PRIORITY =>ACR packet has
-+ higher priority over Audio Sample */
-+ set_reg_field_value(value, 0,
-+ HDMI_ACR_PACKET_CONTROL,
-+ HDMI_ACR_AUDIO_PRIORITY);
-+
-+ dal_write_reg(hw_ctx->ctx, addr, value);
-+ }
-+
-+ /* Program audio clock sample/regeneration parameters */
-+ if (dal_audio_hw_ctx_get_audio_clock_info(
-+ hw_ctx,
-+ crtc_info->color_depth,
-+ crtc_info->requested_pixel_clock,
-+ crtc_info->calculated_pixel_clock,
-+ &audio_clock_info)) {
-+
-+ /* HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK */
-+ {
-+ addr = mmHDMI_ACR_32_0 + engine_offset[engine_id];
-+
-+ value = dal_read_reg(hw_ctx->ctx, addr);
-+
-+ set_reg_field_value(value, audio_clock_info.cts_32khz,
-+ HDMI_ACR_32_0,
-+ HDMI_ACR_CTS_32);
-+
-+ dal_write_reg(hw_ctx->ctx, addr, value);
-+ }
-+
-+ /* HDMI_ACR_32_1__HDMI_ACR_N_32_MASK */
-+ {
-+ addr = mmHDMI_ACR_32_1 + engine_offset[engine_id];
-+
-+ value = dal_read_reg(hw_ctx->ctx, addr);
-+ set_reg_field_value(value, audio_clock_info.n_32khz,
-+ HDMI_ACR_32_1,
-+ HDMI_ACR_N_32);
-+
-+ dal_write_reg(hw_ctx->ctx, addr, value);
-+ }
-+
-+ /* HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK */
-+ {
-+ addr = mmHDMI_ACR_44_0 + engine_offset[engine_id];
-+
-+ value = dal_read_reg(hw_ctx->ctx, addr);
-+ set_reg_field_value(value, audio_clock_info.cts_44khz,
-+ HDMI_ACR_44_0,
-+ HDMI_ACR_CTS_44);
-+
-+ dal_write_reg(hw_ctx->ctx, addr, value);
-+ }
-+
-+ /* HDMI_ACR_44_1__HDMI_ACR_N_44_MASK */
-+ {
-+ addr = mmHDMI_ACR_44_1 + engine_offset[engine_id];
-+
-+ value = dal_read_reg(hw_ctx->ctx, addr);
-+ set_reg_field_value(value, audio_clock_info.n_44khz,
-+ HDMI_ACR_44_1,
-+ HDMI_ACR_N_44);
-+
-+ dal_write_reg(hw_ctx->ctx, addr, value);
-+ }
-+
-+ /* HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK */
-+ {
-+ addr = mmHDMI_ACR_48_0 + engine_offset[engine_id];
-+
-+ value = dal_read_reg(hw_ctx->ctx, addr);
-+ set_reg_field_value(value, audio_clock_info.cts_48khz,
-+ HDMI_ACR_48_0,
-+ HDMI_ACR_CTS_48);
-+
-+ dal_write_reg(hw_ctx->ctx, addr, value);
-+ }
-+
-+ /* HDMI_ACR_48_1__HDMI_ACR_N_48_MASK */
-+ {
-+ addr = mmHDMI_ACR_48_1 + engine_offset[engine_id];
-+
-+ value = dal_read_reg(hw_ctx->ctx, addr);
-+ set_reg_field_value(value, audio_clock_info.n_48khz,
-+ HDMI_ACR_48_1,
-+ HDMI_ACR_N_48);
-+
-+ dal_write_reg(hw_ctx->ctx, addr, value);
-+ }
-+
-+ /* Video driver cannot know in advance which sample rate will
-+ be used by HD Audio driver
-+ HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE field is
-+ programmed below in interruppt callback */
-+ } /* if */
-+
-+ /* AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK &
-+ AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK */
-+ {
-+ addr = mmAFMT_60958_0 + engine_offset[engine_id];
-+
-+ value = dal_read_reg(hw_ctx->ctx, addr);
-+ set_reg_field_value(value, 1,
-+ AFMT_60958_0,
-+ AFMT_60958_CS_CHANNEL_NUMBER_L);
-+
-+ /*HW default */
-+ set_reg_field_value(value, 0,
-+ AFMT_60958_0,
-+ AFMT_60958_CS_CLOCK_ACCURACY);
-+
-+ dal_write_reg(hw_ctx->ctx, addr, value);
-+ }
-+
-+ /* AFMT_60958_1 AFMT_60958_CS_CHALNNEL_NUMBER_R */
-+ {
-+ addr = mmAFMT_60958_1 + engine_offset[engine_id];
-+
-+ value = dal_read_reg(hw_ctx->ctx, addr);
-+ set_reg_field_value(value, 2,
-+ AFMT_60958_1,
-+ AFMT_60958_CS_CHANNEL_NUMBER_R);
-+
-+ dal_write_reg(hw_ctx->ctx, addr, value);
-+ }
-+
-+ /*AFMT_60958_2 now keep this settings until
-+ * Programming guide comes out*/
-+ {
-+ addr = mmAFMT_60958_2 + engine_offset[engine_id];
-+
-+ value = dal_read_reg(hw_ctx->ctx, addr);
-+ set_reg_field_value(value, 3,
-+ AFMT_60958_2,
-+ AFMT_60958_CS_CHANNEL_NUMBER_2);
-+
-+ set_reg_field_value(value, 4,
-+ AFMT_60958_2,
-+ AFMT_60958_CS_CHANNEL_NUMBER_3);
-+
-+ set_reg_field_value(value, 5,
-+ AFMT_60958_2,
-+ AFMT_60958_CS_CHANNEL_NUMBER_4);
-+
-+ set_reg_field_value(value, 6,
-+ AFMT_60958_2,
-+ AFMT_60958_CS_CHANNEL_NUMBER_5);
-+
-+ set_reg_field_value(value, 7,
-+ AFMT_60958_2,
-+ AFMT_60958_CS_CHANNEL_NUMBER_6);
-+
-+ set_reg_field_value(value, 8,
-+ AFMT_60958_2,
-+ AFMT_60958_CS_CHANNEL_NUMBER_7);
-+
-+ dal_write_reg(hw_ctx->ctx, addr, value);
-+ }
-+}
-+
-+ /* setup DP audio */
-+static void setup_dp_audio(
-+ const struct hw_ctx_audio *hw_ctx,
-+ enum engine_id engine_id)
-+{
-+ /* --- DP Audio packet configurations --- */
-+ uint32_t addr = 0;
-+ uint32_t value = 0;
-+
-+ /* ATP Configuration */
-+ {
-+ addr = mmDP_SEC_AUD_N + engine_offset[engine_id];
-+
-+ set_reg_field_value(value,
-+ DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT,
-+ DP_SEC_AUD_N,
-+ DP_SEC_AUD_N);
-+ dal_write_reg(hw_ctx->ctx, addr, value);
-+ }
-+
-+ /* Async/auto-calc timestamp mode */
-+ {
-+ addr = mmDP_SEC_TIMESTAMP +
-+ engine_offset[engine_id];
-+
-+ value = 0;
-+
-+ set_reg_field_value(value,
-+ DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC,
-+ DP_SEC_TIMESTAMP,
-+ DP_SEC_TIMESTAMP_MODE);
-+
-+ dal_write_reg(hw_ctx->ctx, addr, value);
-+ }
-+
-+ /* --- The following are the registers
-+ * copied from the SetupHDMI --- */
-+
-+
-+ /* AFMT_AUDIO_PACKET_CONTROL */
-+ {
-+ addr = mmAFMT_AUDIO_PACKET_CONTROL +
-+ engine_offset[engine_id];
-+
-+ value = 0;
-+
-+ value = dal_read_reg(hw_ctx->ctx, addr);
-+ set_reg_field_value(value,
-+ 1,
-+ AFMT_AUDIO_PACKET_CONTROL,
-+ AFMT_60958_CS_UPDATE);
-+
-+ dal_write_reg(hw_ctx->ctx, addr, value);
-+ }
-+
-+ /* AFMT_AUDIO_PACKET_CONTROL2 */
-+ {
-+ addr =
-+ mmAFMT_AUDIO_PACKET_CONTROL2 + engine_offset[engine_id];
-+
-+ value = 0;
-+
-+ value = dal_read_reg(hw_ctx->ctx, addr);
-+ set_reg_field_value(value,
-+ 0,
-+ AFMT_AUDIO_PACKET_CONTROL2,
-+ AFMT_AUDIO_LAYOUT_OVRD);
-+
-+ set_reg_field_value(value,
-+ 0,
-+ AFMT_AUDIO_PACKET_CONTROL2,
-+ AFMT_60958_OSF_OVRD);
-+
-+ dal_write_reg(hw_ctx->ctx, addr, value);
-+ }
-+
-+ /* AFMT_INFOFRAME_CONTROL0 */
-+ {
-+ addr =
-+ mmAFMT_INFOFRAME_CONTROL0 + engine_offset[engine_id];
-+
-+ value = 0;
-+
-+ value = dal_read_reg(hw_ctx->ctx, addr);
-+
-+ set_reg_field_value(value,
-+ 1,
-+ AFMT_INFOFRAME_CONTROL0,
-+ AFMT_AUDIO_INFO_UPDATE);
-+
-+ dal_write_reg(hw_ctx->ctx, addr, value);
-+ }
-+
-+ /* AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK */
-+ {
-+ addr = mmAFMT_60958_0 + engine_offset[engine_id];
-+
-+ value = 0;
-+
-+ value = dal_read_reg(hw_ctx->ctx, addr);
-+ set_reg_field_value(value,
-+ 0,
-+ AFMT_60958_0,
-+ AFMT_60958_CS_CLOCK_ACCURACY);
-+
-+ dal_write_reg(hw_ctx->ctx, addr, value);
-+ }
-+}
-+
-+ /* setup VCE audio */
-+static void setup_vce_audio(
-+ const struct hw_ctx_audio *hw_ctx)
-+{
-+ struct dc_context *ctx = hw_ctx->ctx;
-+
-+ NOT_IMPLEMENTED();
-+
-+ /*TODO:
-+ const uint32_t addr = mmDOUT_DCE_VCE_CONTROL;
-+ uint32_t value = 0;
-+
-+ value = dal_read_reg(hw_ctx->ctx,
-+ addr);
-+
-+ set_reg_field_value(value,
-+ FROM_BASE(hw_ctx)->azalia_stream_id - 1,
-+ DOUT_DCE_VCE_CONTROL,
-+ DC_VCE_AUDIO_STREAM_SELECT);
-+
-+ dal_write_reg(hw_ctx->ctx,
-+ addr, value);*/
-+}
-+
-+static void enable_afmt_clock(
-+ const struct hw_ctx_audio *hw_ctx,
-+ enum engine_id engine_id,
-+ bool enable_flag)
-+{
-+ uint32_t engine_offs = engine_offset[engine_id];
-+ uint32_t value;
-+ uint32_t count = 0;
-+ uint32_t enable = enable_flag ? 1:0;
-+
-+ /* Enable Audio packets*/
-+ value = dal_read_reg(hw_ctx->ctx, mmAFMT_CNTL + engine_offs);
-+
-+ /*enable AFMT clock*/
-+ set_reg_field_value(value, enable,
-+ AFMT_CNTL, AFMT_AUDIO_CLOCK_EN);
-+ dal_write_reg(hw_ctx->ctx, mmAFMT_CNTL + engine_offs, value);
-+
-+ /*wait for AFMT clock to turn on,
-+ * the expectation is that this
-+ * should complete in 1-2 reads)
-+ */
-+ do {
-+ /* Wait for 1us between subsequent register reads.*/
-+ dc_service_delay_in_microseconds(hw_ctx->ctx, 1);
-+ value = dal_read_reg(hw_ctx->ctx,
-+ mmAFMT_CNTL + engine_offs);
-+ } while (get_reg_field_value(value,
-+ AFMT_CNTL, AFMT_AUDIO_CLOCK_ON) !=
-+ enable && count++ < 10);
-+}
-+
-+/* enable Azalia audio */
-+static void enable_azalia_audio(
-+ const struct hw_ctx_audio *hw_ctx,
-+ enum engine_id engine_id)
-+{
-+ uint32_t value;
-+
-+ value = read_indirect_azalia_reg(
-+ hw_ctx,
-+ ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
-+
-+ if (get_reg_field_value(value,
-+ AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
-+ AUDIO_ENABLED) != 1)
-+ set_reg_field_value(value, 1,
-+ AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
-+ AUDIO_ENABLED);
-+
-+ write_indirect_azalia_reg(
-+ hw_ctx,
-+ ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
-+ value);
-+}
-+
-+/* disable Azalia audio */
-+static void disable_azalia_audio(
-+ const struct hw_ctx_audio *hw_ctx,
-+ enum engine_id engine_id)
-+{
-+ uint32_t value;
-+
-+ value = read_indirect_azalia_reg(
-+ hw_ctx,
-+ ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
-+
-+ set_reg_field_value(value, 0,
-+ AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
-+ AUDIO_ENABLED);
-+
-+ write_indirect_azalia_reg(
-+ hw_ctx,
-+ ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
-+ value);
-+}
-+
-+/* enable DP audio */
-+static void enable_dp_audio(
-+ const struct hw_ctx_audio *hw_ctx,
-+ enum engine_id engine_id)
-+{
-+ const uint32_t addr = mmDP_SEC_CNTL + engine_offset[engine_id];
-+
-+ uint32_t value;
-+
-+ /* Enable Audio packets */
-+ value = dal_read_reg(hw_ctx->ctx, addr);
-+ set_reg_field_value(value, 1,
-+ DP_SEC_CNTL,
-+ DP_SEC_ASP_ENABLE);
-+
-+ dal_write_reg(hw_ctx->ctx, addr, value);
-+
-+ /* Program the ATP and AIP next */
-+ set_reg_field_value(value, 1,
-+ DP_SEC_CNTL,
-+ DP_SEC_ATP_ENABLE);
-+
-+ set_reg_field_value(value, 1,
-+ DP_SEC_CNTL,
-+ DP_SEC_AIP_ENABLE);
-+
-+ dal_write_reg(hw_ctx->ctx, addr, value);
-+
-+ /* Program STREAM_ENABLE after all the other enables. */
-+ set_reg_field_value(value, 1,
-+ DP_SEC_CNTL,
-+ DP_SEC_STREAM_ENABLE);
-+
-+ dal_write_reg(hw_ctx->ctx, addr, value);
-+}
-+
-+/* disable DP audio */
-+static void disable_dp_audio(
-+ const struct hw_ctx_audio *hw_ctx,
-+ enum engine_id engine_id)
-+{
-+ const uint32_t addr = mmDP_SEC_CNTL + engine_offset[engine_id];
-+
-+ uint32_t value;
-+
-+ /* Disable Audio packets */
-+ value = dal_read_reg(hw_ctx->ctx, addr);
-+
-+ set_reg_field_value(value, 0,
-+ DP_SEC_CNTL,
-+ DP_SEC_ASP_ENABLE);
-+
-+ set_reg_field_value(value, 0,
-+ DP_SEC_CNTL,
-+ DP_SEC_ATP_ENABLE);
-+
-+ set_reg_field_value(value, 0,
-+ DP_SEC_CNTL,
-+ DP_SEC_AIP_ENABLE);
-+
-+ set_reg_field_value(value, 0,
-+ DP_SEC_CNTL,
-+ DP_SEC_ACM_ENABLE);
-+
-+ set_reg_field_value(value, 0,
-+ DP_SEC_CNTL,
-+ DP_SEC_STREAM_ENABLE);
-+
-+ /* This register shared with encoder info frame. Therefore we need to
-+ keep master enabled if at least on of the fields is not 0 */
-+ if (value != 0)
-+ set_reg_field_value(value, 1,
-+ DP_SEC_CNTL,
-+ DP_SEC_STREAM_ENABLE);
-+
-+ dal_write_reg(hw_ctx->ctx, addr, value);
-+}
-+
-+static void configure_azalia(
-+ const struct hw_ctx_audio *hw_ctx,
-+ enum signal_type signal,
-+ const struct audio_crtc_info *crtc_info,
-+ const struct audio_info *audio_info)
-+{
-+ uint32_t speakers = audio_info->flags.info.ALLSPEAKERS;
-+ uint32_t value;
-+ uint32_t field = 0;
-+ enum audio_format_code audio_format_code;
-+ uint32_t format_index;
-+ uint32_t index;
-+ bool is_ac3_supported = false;
-+ bool is_audio_format_supported = false;
-+ union audio_sample_rates sample_rate;
-+ uint32_t strlen = 0;
-+
-+ /* Speaker Allocation */
-+ /*
-+ uint32_t value;
-+ uint32_t field = 0;*/
-+ value = read_indirect_azalia_reg(
-+ hw_ctx,
-+ ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
-+
-+ set_reg_field_value(value,
-+ speakers,
-+ AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
-+ SPEAKER_ALLOCATION);
-+
-+ /* LFE_PLAYBACK_LEVEL = LFEPBL
-+ * LFEPBL = 0 : Unknown or refer to other information
-+ * LFEPBL = 1 : 0dB playback
-+ * LFEPBL = 2 : +10dB playback
-+ * LFE_BL = 3 : Reserved
-+ */
-+ set_reg_field_value(value,
-+ 0,
-+ AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
-+ LFE_PLAYBACK_LEVEL);
-+
-+ set_reg_field_value(value,
-+ 0,
-+ AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
-+ HDMI_CONNECTION);
-+
-+ set_reg_field_value(value,
-+ 0,
-+ AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
-+ DP_CONNECTION);
-+
-+ field = get_reg_field_value(value,
-+ AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
-+ EXTRA_CONNECTION_INFO);
-+
-+ field &= ~0x1;
-+
-+ set_reg_field_value(value,
-+ field,
-+ AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
-+ EXTRA_CONNECTION_INFO);
-+
-+ /* set audio for output signal */
-+ switch (signal) {
-+ case SIGNAL_TYPE_HDMI_TYPE_A:
-+ set_reg_field_value(value,
-+ 1,
-+ AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
-+ HDMI_CONNECTION);
-+
-+ break;
-+ case SIGNAL_TYPE_WIRELESS: {
-+ /*LSB used for "is wireless" flag */
-+ field = 0;
-+ field = get_reg_field_value(value,
-+ AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
-+ EXTRA_CONNECTION_INFO);
-+ field |= 0x1;
-+ set_reg_field_value(value,
-+ field,
-+ AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
-+ EXTRA_CONNECTION_INFO);
-+
-+ set_reg_field_value(value,
-+ 1,
-+ AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
-+ HDMI_CONNECTION);
-+
-+ }
-+ break;
-+ case SIGNAL_TYPE_EDP:
-+ case SIGNAL_TYPE_DISPLAY_PORT:
-+ case SIGNAL_TYPE_DISPLAY_PORT_MST:
-+ set_reg_field_value(value,
-+ 1,
-+ AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
-+ DP_CONNECTION);
-+
-+ break;
-+ default:
-+ break;
-+ }
-+
-+ write_indirect_azalia_reg(
-+ hw_ctx,
-+ ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
-+ value);
-+
-+ /* Wireless Display identification */
-+ value = read_indirect_azalia_reg(
-+ hw_ctx,
-+ ixAZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION);
-+
-+ set_reg_field_value(value,
-+ signal == SIGNAL_TYPE_WIRELESS ? 1 : 0,
-+ AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION,
-+ WIRELESS_DISPLAY_IDENTIFICATION);
-+
-+ write_indirect_azalia_reg(
-+ hw_ctx,
-+ ixAZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION,
-+ value);
-+
-+ /* Audio Descriptors */
-+ /* pass through all formats */
-+ for (format_index = 0; format_index < AUDIO_FORMAT_CODE_COUNT;
-+ format_index++) {
-+ audio_format_code =
-+ (AUDIO_FORMAT_CODE_FIRST + format_index);
-+
-+ /* those are unsupported, skip programming */
-+ if (audio_format_code == AUDIO_FORMAT_CODE_1BITAUDIO ||
-+ audio_format_code == AUDIO_FORMAT_CODE_DST)
-+ continue;
-+
-+ value = 0;
-+
-+ /* check if supported */
-+ is_audio_format_supported =
-+ dal_audio_hw_ctx_is_audio_format_supported(
-+ hw_ctx,
-+ audio_info,
-+ audio_format_code, &index);
-+
-+ if (is_audio_format_supported) {
-+ const struct audio_mode *audio_mode =
-+ &audio_info->modes[index];
-+ union audio_sample_rates sample_rates =
-+ audio_mode->sample_rates;
-+ uint8_t byte2 = audio_mode->max_bit_rate;
-+
-+ /* adjust specific properties */
-+ switch (audio_format_code) {
-+ case AUDIO_FORMAT_CODE_LINEARPCM: {
-+ dal_hw_ctx_audio_check_audio_bandwidth(
-+ hw_ctx,
-+ crtc_info,
-+ audio_mode->channel_count,
-+ signal,
-+ &sample_rates);
-+
-+ byte2 = audio_mode->sample_size;
-+
-+ set_reg_field_value(value,
-+ sample_rates.all,
-+ AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
-+ SUPPORTED_FREQUENCIES_STEREO);
-+
-+ }
-+ break;
-+ case AUDIO_FORMAT_CODE_AC3:
-+ is_ac3_supported = true;
-+ break;
-+ case AUDIO_FORMAT_CODE_DOLBYDIGITALPLUS:
-+ case AUDIO_FORMAT_CODE_DTS_HD:
-+ case AUDIO_FORMAT_CODE_MAT_MLP:
-+ case AUDIO_FORMAT_CODE_DST:
-+ case AUDIO_FORMAT_CODE_WMAPRO:
-+ byte2 = audio_mode->vendor_specific;
-+ break;
-+ default:
-+ break;
-+ }
-+
-+ /* fill audio format data */
-+ set_reg_field_value(value,
-+ audio_mode->channel_count - 1,
-+ AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
-+ MAX_CHANNELS);
-+
-+ set_reg_field_value(value,
-+ sample_rates.all,
-+ AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
-+ SUPPORTED_FREQUENCIES);
-+
-+ set_reg_field_value(value,
-+ byte2,
-+ AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
-+ DESCRIPTOR_BYTE_2);
-+
-+ } /* if */
-+
-+ write_indirect_azalia_reg(
-+ hw_ctx,
-+ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 +
-+ format_index,
-+ value);
-+ } /* for */
-+
-+ if (is_ac3_supported)
-+ dal_write_reg(hw_ctx->ctx,
-+ mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS,
-+ 0x05);
-+
-+ /* check for 192khz/8-Ch support for HBR requirements */
-+ sample_rate.all = 0;
-+ sample_rate.rate.RATE_192 = 1;
-+ dal_hw_ctx_audio_check_audio_bandwidth(
-+ hw_ctx,
-+ crtc_info,
-+ 8,
-+ signal,
-+ &sample_rate);
-+
-+ set_high_bit_rate_capable(hw_ctx, sample_rate.rate.RATE_192);
-+
-+ /* Audio and Video Lipsync */
-+ set_video_latency(hw_ctx, audio_info->video_latency);
-+ set_audio_latency(hw_ctx, audio_info->audio_latency);
-+
-+ value = 0;
-+ set_reg_field_value(value, audio_info->manufacture_id,
-+ AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0,
-+ MANUFACTURER_ID);
-+
-+ set_reg_field_value(value, audio_info->product_id,
-+ AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0,
-+ PRODUCT_ID);
-+
-+ write_indirect_azalia_reg(
-+ hw_ctx,
-+ ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0,
-+ value);
-+
-+
-+ value = 0;
-+
-+ /*get display name string length */
-+ while (audio_info->display_name[strlen++] != '\0') {
-+ if (strlen >=
-+ MAX_HW_AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS)
-+ break;
-+ }
-+ set_reg_field_value(value, strlen,
-+ AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1,
-+ SINK_DESCRIPTION_LEN);
-+
-+ write_indirect_azalia_reg(
-+ hw_ctx,
-+ ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1,
-+ value);
-+
-+
-+ /*
-+ *write the port ID:
-+ *PORT_ID0 = display index
-+ *PORT_ID1 = 16bit BDF
-+ *(format MSB->LSB: 8bit Bus, 5bit Device, 3bit Function)
-+ */
-+
-+ value = 0;
-+
-+ set_reg_field_value(value, audio_info->port_id[0],
-+ AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2,
-+ PORT_ID0);
-+
-+ write_indirect_azalia_reg(
-+ hw_ctx,
-+ ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2,
-+ value);
-+
-+ value = 0;
-+ set_reg_field_value(value, audio_info->port_id[1],
-+ AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3,
-+ PORT_ID1);
-+
-+ write_indirect_azalia_reg(
-+ hw_ctx,
-+ ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3,
-+ value);
-+
-+ /*write the 18 char monitor string */
-+
-+ value = 0;
-+ set_reg_field_value(value, audio_info->display_name[0],
-+ AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4,
-+ DESCRIPTION0);
-+
-+ set_reg_field_value(value, audio_info->display_name[1],
-+ AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4,
-+ DESCRIPTION1);
-+
-+ set_reg_field_value(value, audio_info->display_name[2],
-+ AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4,
-+ DESCRIPTION2);
-+
-+ set_reg_field_value(value, audio_info->display_name[3],
-+ AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4,
-+ DESCRIPTION3);
-+
-+ write_indirect_azalia_reg(
-+ hw_ctx,
-+ ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4,
-+ value);
-+
-+
-+ value = 0;
-+ set_reg_field_value(value, audio_info->display_name[4],
-+ AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5,
-+ DESCRIPTION4);
-+
-+ set_reg_field_value(value, audio_info->display_name[5],
-+ AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5,
-+ DESCRIPTION5);
-+
-+ set_reg_field_value(value, audio_info->display_name[6],
-+ AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5,
-+ DESCRIPTION6);
-+
-+ set_reg_field_value(value, audio_info->display_name[7],
-+ AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5,
-+ DESCRIPTION7);
-+
-+ write_indirect_azalia_reg(
-+ hw_ctx,
-+ ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5,
-+ value);
-+
-+ value = 0;
-+ set_reg_field_value(value, audio_info->display_name[8],
-+ AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6,
-+ DESCRIPTION8);
-+
-+ set_reg_field_value(value, audio_info->display_name[9],
-+ AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6,
-+ DESCRIPTION9);
-+
-+ set_reg_field_value(value, audio_info->display_name[10],
-+ AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6,
-+ DESCRIPTION10);
-+
-+ set_reg_field_value(value, audio_info->display_name[11],
-+ AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6,
-+ DESCRIPTION11);
-+
-+ write_indirect_azalia_reg(
-+ hw_ctx,
-+ ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6,
-+ value);
-+
-+ value = 0;
-+ set_reg_field_value(value, audio_info->display_name[12],
-+ AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7,
-+ DESCRIPTION12);
-+
-+ set_reg_field_value(value, audio_info->display_name[13],
-+ AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7,
-+ DESCRIPTION13);
-+
-+ set_reg_field_value(value, audio_info->display_name[14],
-+ AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7,
-+ DESCRIPTION14);
-+
-+ set_reg_field_value(value, audio_info->display_name[15],
-+ AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7,
-+ DESCRIPTION15);
-+
-+ write_indirect_azalia_reg(
-+ hw_ctx,
-+ ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7,
-+ value);
-+
-+
-+ value = 0;
-+ set_reg_field_value(value, audio_info->display_name[16],
-+ AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8,
-+ DESCRIPTION16);
-+
-+ set_reg_field_value(value, audio_info->display_name[17],
-+ AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8,
-+ DESCRIPTION17);
-+
-+ write_indirect_azalia_reg(
-+ hw_ctx,
-+ ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8,
-+ value);
-+
-+}
-+
-+/* setup Azalia HW block */
-+static void setup_azalia(
-+ const struct hw_ctx_audio *hw_ctx,
-+ enum engine_id engine_id,
-+ enum signal_type signal,
-+ const struct audio_crtc_info *crtc_info,
-+ const struct audio_pll_info *pll_info,
-+ const struct audio_info *audio_info)
-+{
-+ uint32_t speakers = 0;
-+ uint32_t channels = 0;
-+
-+ if (audio_info == NULL)
-+ /* This should not happen.it does so we don't get BSOD*/
-+ return;
-+
-+ speakers = audio_info->flags.info.ALLSPEAKERS;
-+ channels = dal_audio_hw_ctx_speakers_to_channels(
-+ hw_ctx,
-+ audio_info->flags.speaker_flags).all;
-+
-+ /* setup the audio stream source select (audio -> dig mapping) */
-+ {
-+ const uint32_t addr =
-+ mmAFMT_AUDIO_SRC_CONTROL + engine_offset[engine_id];
-+
-+ uint32_t value = 0;
-+ /*convert one-based index to zero-based */
-+ set_reg_field_value(value,
-+ FROM_BASE(hw_ctx)->azalia_stream_id - 1,
-+ AFMT_AUDIO_SRC_CONTROL,
-+ AFMT_AUDIO_SRC_SELECT);
-+
-+ dal_write_reg(hw_ctx->ctx, addr, value);
-+ }
-+
-+ /* Channel allocation */
-+ {
-+ const uint32_t addr =
-+ mmAFMT_AUDIO_PACKET_CONTROL2 + engine_offset[engine_id];
-+ uint32_t value = dal_read_reg(hw_ctx->ctx, addr);
-+
-+ set_reg_field_value(value,
-+ channels,
-+ AFMT_AUDIO_PACKET_CONTROL2,
-+ AFMT_AUDIO_CHANNEL_ENABLE);
-+
-+ dal_write_reg(hw_ctx->ctx, addr, value);
-+ }
-+
-+ configure_azalia(hw_ctx, signal, crtc_info, audio_info);
-+}
-+
-+/* unmute audio */
-+static void unmute_azalia_audio(
-+ const struct hw_ctx_audio *hw_ctx,
-+ enum engine_id engine_id)
-+{
-+ const uint32_t addr = mmAFMT_AUDIO_PACKET_CONTROL +
-+ engine_offset[engine_id];
-+
-+ uint32_t value = 0;
-+
-+ value = dal_read_reg(hw_ctx->ctx, addr);
-+
-+ set_reg_field_value(value, 1,
-+ AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND);
-+
-+ dal_write_reg(hw_ctx->ctx, addr, value);
-+}
-+
-+/* mute audio */
-+static void mute_azalia_audio(
-+ const struct hw_ctx_audio *hw_ctx,
-+ enum engine_id engine_id)
-+{
-+ const uint32_t addr = mmAFMT_AUDIO_PACKET_CONTROL +
-+ engine_offset[engine_id];
-+
-+ uint32_t value = 0;
-+
-+ value = dal_read_reg(hw_ctx->ctx, addr);
-+
-+ set_reg_field_value(value, 0,
-+ AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND);
-+
-+ dal_write_reg(hw_ctx->ctx, addr, value);
-+}
-+
-+/* enable channel splitting mapping */
-+static void setup_channel_splitting_mapping(
-+ const struct hw_ctx_audio *hw_ctx,
-+ enum engine_id engine_id,
-+ enum signal_type signal,
-+ const struct audio_channel_associate_info *audio_mapping,
-+ bool enable)
-+{
-+ uint32_t value = 0;
-+
-+ if ((audio_mapping == NULL || audio_mapping->u32all == 0) && enable)
-+ return;
-+
-+
-+ value = audio_mapping->u32all;
-+
-+ if (enable == false)
-+ /*0xFFFFFFFF;*/
-+ value = MULTI_CHANNEL_SPLIT_NO_ASSO_INFO;
-+
-+ write_indirect_azalia_reg(
-+ hw_ctx,
-+ ixAZALIA_F0_CODEC_PIN_ASSOCIATION_INFO,
-+ value);
-+}
-+
-+/* get current channel spliting */
-+static bool get_channel_splitting_mapping(
-+ const struct hw_ctx_audio *hw_ctx,
-+ enum engine_id engine_id,
-+ struct audio_channel_associate_info *audio_mapping)
-+{
-+ uint32_t value = 0;
-+
-+ if (audio_mapping == NULL)
-+ return false;
-+
-+ value = read_indirect_azalia_reg(
-+ hw_ctx,
-+ ixAZALIA_F0_CODEC_PIN_ASSOCIATION_INFO);
-+
-+ /*0xFFFFFFFF*/
-+ if (get_reg_field_value(value,
-+ AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO,
-+ ASSOCIATION_INFO) !=
-+ MULTI_CHANNEL_SPLIT_NO_ASSO_INFO) {
-+ uint32_t multi_channel01_enable = 0;
-+ uint32_t multi_channel23_enable = 0;
-+ uint32_t multi_channel45_enable = 0;
-+ uint32_t multi_channel67_enable = 0;
-+ /* get the one we set.*/
-+ audio_mapping->u32all = value;
-+
-+ /* check each enable status*/
-+ value = read_indirect_azalia_reg(
-+ hw_ctx,
-+ ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE);
-+
-+ multi_channel01_enable = get_reg_field_value(value,
-+ AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE,
-+ MULTICHANNEL01_ENABLE);
-+
-+ multi_channel23_enable = get_reg_field_value(value,
-+ AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE,
-+ MULTICHANNEL23_ENABLE);
-+
-+ multi_channel45_enable = get_reg_field_value(value,
-+ AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE,
-+ MULTICHANNEL45_ENABLE);
-+
-+ multi_channel67_enable = get_reg_field_value(value,
-+ AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE,
-+ MULTICHANNEL67_ENABLE);
-+
-+ if (multi_channel01_enable == 0 &&
-+ multi_channel23_enable == 0 &&
-+ multi_channel45_enable == 0 &&
-+ multi_channel67_enable == 0)
-+ dal_logger_write(hw_ctx->ctx->logger,
-+ LOG_MAJOR_HW_TRACE,
-+ LOG_MINOR_COMPONENT_AUDIO,
-+ "Audio driver did not enable multi-channel\n");
-+
-+ return true;
-+ }
-+
-+ return false;
-+}
-+
-+/* set the payload value for the unsolicited response */
-+static void set_unsolicited_response_payload(
-+ const struct hw_ctx_audio *hw_ctx,
-+ enum audio_payload payload)
-+{
-+ /* set the payload value for the unsolicited response
-+ Jack presence is not required to be enabled */
-+ uint32_t value = 0;
-+
-+ value = read_indirect_azalia_reg(
-+ hw_ctx,
-+ ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE);
-+
-+ set_reg_field_value(value, payload,
-+ AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE,
-+ UNSOLICITED_RESPONSE_PAYLOAD);
-+
-+ set_reg_field_value(value, 1,
-+ AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE,
-+ UNSOLICITED_RESPONSE_FORCE);
-+
-+ write_indirect_azalia_reg(
-+ hw_ctx,
-+ ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE,
-+ value);
-+}
-+
-+/* initialize HW state */
-+static void hw_initialize(
-+ const struct hw_ctx_audio *hw_ctx)
-+{
-+ uint32_t stream_id = FROM_BASE(hw_ctx)->azalia_stream_id;
-+ uint32_t addr;
-+
-+ /* we only need to program the following registers once, so we only do
-+ it for the first audio stream.*/
-+ if (stream_id != FIRST_AUDIO_STREAM_ID)
-+ return;
-+
-+ /* Suport R5 - 32khz
-+ * Suport R6 - 44.1khz
-+ * Suport R7 - 48khz
-+ */
-+ addr = mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES;
-+ {
-+ uint32_t value;
-+
-+ value = dal_read_reg(hw_ctx->ctx, addr);
-+
-+ set_reg_field_value(value, 0x70,
-+ AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES,
-+ AUDIO_RATE_CAPABILITIES);
-+
-+ dal_write_reg(hw_ctx->ctx, addr, value);
-+ }
-+
-+ /*Keep alive bit to verify HW block in BU. */
-+ addr = mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES;
-+ {
-+ uint32_t value;
-+
-+ value = dal_read_reg(hw_ctx->ctx, addr);
-+
-+ set_reg_field_value(value, 1,
-+ AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES,
-+ CLKSTOP);
-+
-+ set_reg_field_value(value, 1,
-+ AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES,
-+ EPSS);
-+ dal_write_reg(hw_ctx->ctx, addr, value);
-+ }
-+}
-+
-+/* Assign GTC group and enable GTC value embedding */
-+static void enable_gtc_embedding_with_group(
-+ const struct hw_ctx_audio *hw_ctx,
-+ uint32_t group_num,
-+ uint32_t audio_latency)
-+{
-+ /*need to replace the static number with variable */
-+ if (group_num <= 6) {
-+ uint32_t value = read_indirect_azalia_reg(
-+ hw_ctx,
-+ ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING);
-+
-+ set_reg_field_value(
-+ value,
-+ group_num,
-+ AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING,
-+ PRESENTATION_TIME_EMBEDDING_GROUP);
-+
-+ set_reg_field_value(
-+ value,
-+ 1,
-+ AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING,
-+ PRESENTATION_TIME_EMBEDDING_ENABLE);
-+
-+ write_indirect_azalia_reg(
-+ hw_ctx,
-+ ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING,
-+ value);
-+
-+ /*update audio latency to LIPSYNC*/
-+ set_audio_latency(hw_ctx, audio_latency);
-+ } else {
-+ dal_logger_write(
-+ hw_ctx->ctx->logger,
-+ LOG_MAJOR_HW_TRACE,
-+ LOG_MINOR_COMPONENT_AUDIO,
-+ "GTC group number %d is too big",
-+ group_num);
-+ }
-+}
-+
-+ /* Disable GTC value embedding */
-+static void disable_gtc_embedding(
-+ const struct hw_ctx_audio *hw_ctx)
-+{
-+ uint32_t value = 0;
-+
-+ value = read_indirect_azalia_reg(
-+ hw_ctx,
-+ ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING);
-+
-+ set_reg_field_value(value, 0,
-+ AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING,
-+ PRESENTATION_TIME_EMBEDDING_ENABLE);
-+
-+ set_reg_field_value(value, 0,
-+ AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING,
-+ PRESENTATION_TIME_EMBEDDING_GROUP);
-+
-+ write_indirect_azalia_reg(
-+ hw_ctx,
-+ ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING,
-+ value);
-+}
-+
-+/* search pixel clock value for Azalia HDMI Audio */
-+static bool get_azalia_clock_info_hdmi(
-+ const struct hw_ctx_audio *hw_ctx,
-+ uint32_t crtc_pixel_clock_in_khz,
-+ uint32_t actual_pixel_clock_in_khz,
-+ struct azalia_clock_info *azalia_clock_info)
-+{
-+ if (azalia_clock_info == NULL)
-+ return false;
-+
-+ /* audio_dto_phase= 24 * 10,000;
-+ * 24MHz in [100Hz] units */
-+ azalia_clock_info->audio_dto_phase =
-+ 24 * 10000;
-+
-+ /* audio_dto_module = PCLKFrequency * 10,000;
-+ * [khz] -> [100Hz] */
-+ azalia_clock_info->audio_dto_module =
-+ actual_pixel_clock_in_khz * 10;
-+
-+ return true;
-+}
-+
-+/* search pixel clock value for Azalia DP Audio */
-+static bool get_azalia_clock_info_dp(
-+ const struct hw_ctx_audio *hw_ctx,
-+ uint32_t requested_pixel_clock_in_khz,
-+ const struct audio_pll_info *pll_info,
-+ struct azalia_clock_info *azalia_clock_info)
-+{
-+ if (pll_info == NULL || azalia_clock_info == NULL)
-+ return false;
-+
-+ /* Reported dpDtoSourceClockInkhz value for
-+ * DCE8 already adjusted for SS, do not need any
-+ * adjustment here anymore
-+ */
-+
-+ /*audio_dto_phase = 24 * 10,000;
-+ * 24MHz in [100Hz] units */
-+ azalia_clock_info->audio_dto_phase = 24 * 10000;
-+
-+ /*audio_dto_module = dpDtoSourceClockInkhz * 10,000;
-+ * [khz] ->[100Hz] */
-+ azalia_clock_info->audio_dto_module =
-+ pll_info->dp_dto_source_clock_in_khz * 10;
-+
-+ return true;
-+}
-+
-+static const struct hw_ctx_audio_funcs funcs = {
-+ .destroy = destroy,
-+ .setup_audio_wall_dto =
-+ setup_audio_wall_dto,
-+ .setup_hdmi_audio =
-+ setup_hdmi_audio,
-+ .setup_dp_audio = setup_dp_audio,
-+ .setup_vce_audio = setup_vce_audio,
-+ .enable_azalia_audio =
-+ enable_azalia_audio,
-+ .disable_azalia_audio =
-+ disable_azalia_audio,
-+ .enable_dp_audio =
-+ enable_dp_audio,
-+ .disable_dp_audio =
-+ disable_dp_audio,
-+ .setup_azalia =
-+ setup_azalia,
-+ .disable_az_clock_gating = NULL,
-+ .unmute_azalia_audio =
-+ unmute_azalia_audio,
-+ .mute_azalia_audio =
-+ mute_azalia_audio,
-+ .setup_channel_splitting_mapping =
-+ setup_channel_splitting_mapping,
-+ .get_channel_splitting_mapping =
-+ get_channel_splitting_mapping,
-+ .set_unsolicited_response_payload =
-+ set_unsolicited_response_payload,
-+ .hw_initialize =
-+ hw_initialize,
-+ .enable_gtc_embedding_with_group =
-+ enable_gtc_embedding_with_group,
-+ .disable_gtc_embedding =
-+ disable_gtc_embedding,
-+ .get_azalia_clock_info_hdmi =
-+ get_azalia_clock_info_hdmi,
-+ .get_azalia_clock_info_dp =
-+ get_azalia_clock_info_dp,
-+ .enable_afmt_clock = enable_afmt_clock
-+};
-+
-+static bool construct(
-+ struct hw_ctx_audio_dce110 *hw_ctx,
-+ uint8_t azalia_stream_id,
-+ struct dc_context *ctx)
-+{
-+ struct hw_ctx_audio *base = &hw_ctx->base;
-+
-+ if (!dal_audio_construct_hw_ctx_audio(base))
-+ return false;
-+
-+ base->funcs = &funcs;
-+
-+ /* save audio endpoint or dig front for current dce110 audio object */
-+ hw_ctx->azalia_stream_id = azalia_stream_id;
-+ hw_ctx->base.ctx = ctx;
-+
-+ /* azalia audio endpoints register offsets. azalia is associated with
-+ DIG front. save AUDIO register offset */
-+ switch (azalia_stream_id) {
-+ case 1: {
-+ hw_ctx->az_mm_reg_offsets.
-+ azf0endpointx_azalia_f0_codec_endpoint_index =
-+ mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX;
-+ hw_ctx->az_mm_reg_offsets.
-+ azf0endpointx_azalia_f0_codec_endpoint_data =
-+ mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA;
-+ }
-+ break;
-+ case 2: {
-+ hw_ctx->az_mm_reg_offsets.
-+ azf0endpointx_azalia_f0_codec_endpoint_index =
-+ mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX;
-+ hw_ctx->az_mm_reg_offsets.
-+ azf0endpointx_azalia_f0_codec_endpoint_data =
-+ mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA;
-+ }
-+ break;
-+ case 3: {
-+ hw_ctx->az_mm_reg_offsets.
-+ azf0endpointx_azalia_f0_codec_endpoint_index =
-+ mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX;
-+ hw_ctx->az_mm_reg_offsets.
-+ azf0endpointx_azalia_f0_codec_endpoint_data =
-+ mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA;
-+ }
-+ break;
-+ case 4: {
-+ hw_ctx->az_mm_reg_offsets.
-+ azf0endpointx_azalia_f0_codec_endpoint_index =
-+ mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX;
-+ hw_ctx->az_mm_reg_offsets.
-+ azf0endpointx_azalia_f0_codec_endpoint_data =
-+ mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA;
-+ }
-+ break;
-+ default:
-+ dal_logger_write(
-+ hw_ctx->base.ctx->logger,
-+ LOG_MAJOR_WARNING,
-+ LOG_MINOR_COMPONENT_AUDIO,
-+ "Invalid Azalia stream ID!");
-+ break;
-+ }
-+
-+ return true;
-+}
-+
-+/* audio_dce110 is derived from audio directly, not via dce80 */
-+struct hw_ctx_audio *dal_hw_ctx_audio_dce110_create(
-+ struct dc_context *ctx,
-+ uint32_t azalia_stream_id)
-+{
-+ /* allocate memory for struc hw_ctx_audio_dce110 */
-+ struct hw_ctx_audio_dce110 *hw_ctx_dce110 =
-+ dc_service_alloc(ctx, sizeof(struct hw_ctx_audio_dce110));
-+
-+ if (!hw_ctx_dce110) {
-+ ASSERT_CRITICAL(hw_ctx_dce110);
-+ return NULL;
-+ }
-+
-+ /*return pointer to hw_ctx_audio back to caller -- audio object */
-+ if (construct(
-+ hw_ctx_dce110, azalia_stream_id, ctx))
-+ return &hw_ctx_dce110->base;
-+
-+ dal_logger_write(
-+ ctx->logger,
-+ LOG_MAJOR_ERROR,
-+ LOG_MINOR_COMPONENT_AUDIO,
-+ "Failed to create hw_ctx_audio for DCE11\n");
-+
-+
-+ dc_service_free(ctx, hw_ctx_dce110);
-+
-+ return NULL;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/audio/dce110/hw_ctx_audio_dce110.h b/drivers/gpu/drm/amd/dal/dc/audio/dce110/hw_ctx_audio_dce110.h
-new file mode 100644
-index 0000000..1ad3826
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/audio/dce110/hw_ctx_audio_dce110.h
-@@ -0,0 +1,47 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_HW_CTX_AUDIO_DCE110_H__
-+#define __DAL_HW_CTX_AUDIO_DCE110_H__
-+
-+#include "audio/hw_ctx_audio.h"
-+
-+struct hw_ctx_audio_dce110 {
-+ struct hw_ctx_audio base;
-+
-+ /* azalia stream id 1 based indexing, corresponding to audio GO enumId*/
-+ uint32_t azalia_stream_id;
-+
-+ /* azalia stream endpoint register offsets */
-+ struct azalia_reg_offsets az_mm_reg_offsets;
-+
-+ /* audio encoder block MM register offset -- associate with DIG FRONT */
-+};
-+
-+struct hw_ctx_audio *dal_hw_ctx_audio_dce110_create(
-+ struct dc_context *ctx,
-+ uint32_t azalia_stream_id);
-+
-+#endif /* __DAL_HW_CTX_AUDIO_DCE110_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/audio/hw_ctx_audio.c b/drivers/gpu/drm/amd/dal/dc/audio/hw_ctx_audio.c
-new file mode 100644
-index 0000000..f1f1298
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/audio/hw_ctx_audio.c
-@@ -0,0 +1,771 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+
-+#include "hw_ctx_audio.h"
-+
-+/* 25.2MHz/1.001*/
-+/* 25.2MHz/1.001*/
-+/* 25.2MHz*/
-+/* 27MHz */
-+/* 27MHz*1.001*/
-+/* 27MHz*1.001*/
-+/* 54MHz*/
-+/* 54MHz*1.001*/
-+/* 74.25MHz/1.001*/
-+/* 74.25MHz*/
-+/* 148.5MHz/1.001*/
-+/* 148.5MHz*/
-+
-+static const struct audio_clock_info audio_clock_info_table[12] = {
-+ {2517, 4576, 28125, 7007, 31250, 6864, 28125},
-+ {2518, 4576, 28125, 7007, 31250, 6864, 28125},
-+ {2520, 4096, 25200, 6272, 28000, 6144, 25200},
-+ {2700, 4096, 27000, 6272, 30000, 6144, 27000},
-+ {2702, 4096, 27027, 6272, 30030, 6144, 27027},
-+ {2703, 4096, 27027, 6272, 30030, 6144, 27027},
-+ {5400, 4096, 54000, 6272, 60000, 6144, 54000},
-+ {5405, 4096, 54054, 6272, 60060, 6144, 54054},
-+ {7417, 11648, 210937, 17836, 234375, 11648, 140625},
-+ {7425, 4096, 74250, 6272, 82500, 6144, 74250},
-+ {14835, 11648, 421875, 8918, 234375, 5824, 140625},
-+ {14850, 4096, 148500, 6272, 165000, 6144, 148500}
-+};
-+
-+static const struct audio_clock_info audio_clock_info_table_36bpc[12] = {
-+ {2517, 9152, 84375, 7007, 48875, 9152, 56250},
-+ {2518, 9152, 84375, 7007, 48875, 9152, 56250},
-+ {2520, 4096, 37800, 6272, 42000, 6144, 37800},
-+ {2700, 4096, 40500, 6272, 45000, 6144, 40500},
-+ {2702, 8192, 81081, 6272, 45045, 8192, 54054},
-+ {2703, 8192, 81081, 6272, 45045, 8192, 54054},
-+ {5400, 4096, 81000, 6272, 90000, 6144, 81000},
-+ {5405, 4096, 81081, 6272, 90090, 6144, 81081},
-+ {7417, 11648, 316406, 17836, 351562, 11648, 210937},
-+ {7425, 4096, 111375, 6272, 123750, 6144, 111375},
-+ {14835, 11648, 632812, 17836, 703125, 11648, 421875},
-+ {14850, 4096, 222750, 6272, 247500, 6144, 222750}
-+};
-+
-+static const struct audio_clock_info audio_clock_info_table_48bpc[12] = {
-+ {2517, 4576, 56250, 7007, 62500, 6864, 56250},
-+ {2518, 4576, 56250, 7007, 62500, 6864, 56250},
-+ {2520, 4096, 50400, 6272, 56000, 6144, 50400},
-+ {2700, 4096, 54000, 6272, 60000, 6144, 54000},
-+ {2702, 4096, 54054, 6267, 60060, 8192, 54054},
-+ {2703, 4096, 54054, 6272, 60060, 8192, 54054},
-+ {5400, 4096, 108000, 6272, 120000, 6144, 108000},
-+ {5405, 4096, 108108, 6272, 120120, 6144, 108108},
-+ {7417, 11648, 421875, 17836, 468750, 11648, 281250},
-+ {7425, 4096, 148500, 6272, 165000, 6144, 148500},
-+ {14835, 11648, 843750, 8918, 468750, 11648, 281250},
-+ {14850, 4096, 297000, 6272, 330000, 6144, 297000}
-+};
-+
-+
-+/***** static function *****/
-+
-+/*
-+ * except of HW context create function, caller will access other functions of
-+ * hw ctx via handle hw_ctx. Memory allocation for struct hw_ctx_audio_dce8x
-+ * will happen in hw_ctx_audio_dce8x. Memory allocation is done with
-+ * dal_audio_create_hw_ctx_audio_dce8x. Memory release is done by caller
-+ * via hw_ctx->functions.destroy(). It will finally use destroy() of
-+ * hw_ctx_audio_dce8x. Therefore, no memory allocate and release happen
-+ * physically at hw ctx base object.
-+ */
-+static void destroy(
-+ struct hw_ctx_audio **ptr)
-+{
-+ /* Attention!
-+ * You must override this method in derived class */
-+}
-+
-+static void setup_audio_wall_dto(
-+ const struct hw_ctx_audio *hw_ctx,
-+ enum signal_type signal,
-+ const struct audio_crtc_info *crtc_info,
-+ const struct audio_pll_info *pll_info)
-+{
-+ /*DCE specific, must be implemented in derived*/
-+ BREAK_TO_DEBUGGER();
-+}
-+
-+/* setup HDMI audio */
-+static void setup_hdmi_audio(
-+ const struct hw_ctx_audio *hw_ctx,
-+ enum engine_id engine_id,
-+ const struct audio_crtc_info *crtc_info)
-+{
-+ /*DCE specific, must be implemented in derived*/
-+ BREAK_TO_DEBUGGER();
-+}
-+
-+ /* setup DP audio */
-+static void setup_dp_audio(
-+ const struct hw_ctx_audio *hw_ctx,
-+ enum engine_id engine_id)
-+{
-+ /*DCE specific, must be implemented in derived*/
-+ BREAK_TO_DEBUGGER();
-+}
-+
-+ /* setup VCE audio */
-+static void setup_vce_audio(
-+ const struct hw_ctx_audio *hw_ctx)
-+{
-+ /*DCE specific, must be implemented in derived*/
-+ BREAK_TO_DEBUGGER();
-+}
-+
-+/* enable Azalia audio */
-+static void enable_azalia_audio(
-+ const struct hw_ctx_audio *hw_ctx,
-+ enum engine_id engine_id)
-+{
-+ /*DCE specific, must be implemented in derived*/
-+ BREAK_TO_DEBUGGER();
-+}
-+
-+/* disable Azalia audio */
-+static void disable_azalia_audio(
-+ const struct hw_ctx_audio *hw_ctx,
-+ enum engine_id engine_id)
-+{
-+ /*DCE specific, must be implemented in derived*/
-+ BREAK_TO_DEBUGGER();
-+}
-+
-+/* enable DP audio */
-+static void enable_dp_audio(
-+ const struct hw_ctx_audio *hw_ctx,
-+ enum engine_id engine_id)
-+{
-+ /*DCE specific, must be implemented in derived*/
-+ BREAK_TO_DEBUGGER();
-+}
-+
-+/* disable DP audio */
-+static void disable_dp_audio(
-+ const struct hw_ctx_audio *hw_ctx,
-+ enum engine_id engine_id)
-+{
-+ /*DCE specific, must be implemented in derived*/
-+ BREAK_TO_DEBUGGER();
-+}
-+
-+/* setup Azalia HW block */
-+static void setup_azalia(
-+ const struct hw_ctx_audio *hw_ctx,
-+ enum engine_id engine_id,
-+ enum signal_type signal,
-+ const struct audio_crtc_info *crtc_info,
-+ const struct audio_pll_info *pll_info,
-+ const struct audio_info *audio_info)
-+{
-+ /*DCE specific, must be implemented in derived*/
-+ BREAK_TO_DEBUGGER();
-+}
-+
-+/* unmute audio */
-+static void unmute_azalia_audio(
-+ const struct hw_ctx_audio *hw_ctx,
-+ enum engine_id engine_id)
-+{
-+ /*DCE specific, must be implemented in derived*/
-+ BREAK_TO_DEBUGGER();
-+}
-+
-+/* mute audio */
-+static void mute_azalia_audio(
-+ const struct hw_ctx_audio *hw_ctx,
-+ enum engine_id engine_id)
-+{
-+ /*DCE specific, must be implemented in derived*/
-+ BREAK_TO_DEBUGGER();
-+}
-+
-+/* enable channel splitting mapping */
-+static void setup_channel_splitting_mapping(
-+ const struct hw_ctx_audio *hw_ctx,
-+ enum engine_id engine_id,
-+ enum signal_type signal,
-+ const struct audio_channel_associate_info *audio_mapping,
-+ bool enable)
-+{
-+ /*DCE specific, must be implemented in derived*/
-+ BREAK_TO_DEBUGGER();
-+}
-+
-+/* get current channel spliting */
-+static bool get_channel_splitting_mapping(
-+ const struct hw_ctx_audio *hw_ctx,
-+ enum engine_id engine_id,
-+ struct audio_channel_associate_info *audio_mapping)
-+{
-+ /*DCE specific, must be implemented in derived*/
-+ BREAK_TO_DEBUGGER();
-+ return false;
-+}
-+
-+/* set the payload value for the unsolicited response */
-+static void set_unsolicited_response_payload(
-+ const struct hw_ctx_audio *hw_ctx,
-+ enum audio_payload payload)
-+{
-+ /*DCE specific, must be implemented in derived*/
-+ BREAK_TO_DEBUGGER();
-+}
-+
-+/* initialize HW state */
-+static void hw_initialize(
-+ const struct hw_ctx_audio *hw_ctx)
-+{
-+ /*DCE specific, must be implemented in derived*/
-+ BREAK_TO_DEBUGGER();
-+}
-+
-+/* Assign GTC group and enable GTC value embedding */
-+static void enable_gtc_embedding_with_group(
-+ const struct hw_ctx_audio *hw_ctx,
-+ uint32_t groupNum,
-+ uint32_t audioLatency)
-+{
-+ /*DCE specific, must be implemented in derived*/
-+ BREAK_TO_DEBUGGER();
-+}
-+
-+/* Disable GTC value embedding */
-+static void disable_gtc_embedding(
-+ const struct hw_ctx_audio *hw_ctx)
-+{
-+ /*DCE specific, must be implemented in derived*/
-+ BREAK_TO_DEBUGGER();
-+}
-+
-+/* Disable Azalia Clock Gating Feature */
-+static void disable_az_clock_gating(
-+ const struct hw_ctx_audio *hw_ctx)
-+{
-+ /*DCE specific, must be implemented in derived*/
-+ BREAK_TO_DEBUGGER();
-+}
-+
-+/* search pixel clock value for Azalia HDMI Audio */
-+static bool get_azalia_clock_info_hdmi(
-+ const struct hw_ctx_audio *hw_ctx,
-+ uint32_t crtc_pixel_clock_in_khz,
-+ uint32_t actual_pixel_clock_in_khz,
-+ struct azalia_clock_info *azalia_clock_info)
-+{
-+ /*DCE specific, must be implemented in derived*/
-+ BREAK_TO_DEBUGGER();
-+ return false;
-+}
-+
-+/* search pixel clock value for Azalia DP Audio */
-+static bool get_azalia_clock_info_dp(
-+ const struct hw_ctx_audio *hw_ctx,
-+ uint32_t requested_pixel_clock_in_khz,
-+ const struct audio_pll_info *pll_info,
-+ struct azalia_clock_info *azalia_clock_info)
-+{
-+ /*DCE specific, must be implemented in derived*/
-+ BREAK_TO_DEBUGGER();
-+ return false;
-+}
-+
-+
-+
-+
-+
-+
-+
-+
-+
-+/*****SCOPE : within audio hw context dal-audio-hw-ctx *****/
-+
-+
-+/* check whether specified sample rates can fit into a given timing */
-+void dal_hw_ctx_audio_check_audio_bandwidth(
-+ const struct hw_ctx_audio *hw_ctx,
-+ const struct audio_crtc_info *crtc_info,
-+ uint32_t channel_count,
-+ enum signal_type signal,
-+ union audio_sample_rates *sample_rates)
-+{
-+ switch (signal) {
-+ case SIGNAL_TYPE_HDMI_TYPE_A:
-+ dal_audio_hw_ctx_check_audio_bandwidth_hdmi(
-+ hw_ctx, crtc_info, channel_count, sample_rates);
-+ break;
-+ case SIGNAL_TYPE_EDP:
-+ case SIGNAL_TYPE_DISPLAY_PORT:
-+ dal_audio_hw_ctx_check_audio_bandwidth_dpsst(
-+ hw_ctx, crtc_info, channel_count, sample_rates);
-+ break;
-+ case SIGNAL_TYPE_DISPLAY_PORT_MST:
-+ dal_audio_hw_ctx_check_audio_bandwidth_dpmst(
-+ hw_ctx, crtc_info, channel_count, sample_rates);
-+ break;
-+ default:
-+ break;
-+ }
-+}
-+
-+/*For HDMI, calculate if specified sample rates can fit into a given timing */
-+void dal_audio_hw_ctx_check_audio_bandwidth_hdmi(
-+ const struct hw_ctx_audio *hw_ctx,
-+ const struct audio_crtc_info *crtc_info,
-+ uint32_t channel_count,
-+ union audio_sample_rates *sample_rates)
-+{
-+ uint32_t samples;
-+ uint32_t h_blank;
-+ bool limit_freq_to_48_khz = false;
-+ bool limit_freq_to_88_2_khz = false;
-+ bool limit_freq_to_96_khz = false;
-+ bool limit_freq_to_174_4_khz = false;
-+
-+ /* For two channels supported return whatever sink support,unmodified*/
-+ if (channel_count > 2) {
-+
-+ /* Based on HDMI spec 1.3 Table 7.5 */
-+ if ((crtc_info->requested_pixel_clock <= 27000) &&
-+ (crtc_info->v_active <= 576) &&
-+ !(crtc_info->interlaced) &&
-+ !(crtc_info->pixel_repetition == 2 ||
-+ crtc_info->pixel_repetition == 4)) {
-+ limit_freq_to_48_khz = true;
-+
-+ } else if ((crtc_info->requested_pixel_clock <= 27000) &&
-+ (crtc_info->v_active <= 576) &&
-+ (crtc_info->interlaced) &&
-+ (crtc_info->pixel_repetition == 2)) {
-+ limit_freq_to_88_2_khz = true;
-+
-+ } else if ((crtc_info->requested_pixel_clock <= 54000) &&
-+ (crtc_info->v_active <= 576) &&
-+ !(crtc_info->interlaced)) {
-+ limit_freq_to_174_4_khz = true;
-+ }
-+ }
-+
-+ /* Also do some calculation for the available Audio Bandwidth for the
-+ * 8 ch (i.e. for the Layout 1 => ch > 2)
-+ */
-+ h_blank = crtc_info->h_total - crtc_info->h_active;
-+
-+ if (crtc_info->pixel_repetition)
-+ h_blank *= crtc_info->pixel_repetition;
-+
-+ /*based on HDMI spec 1.3 Table 7.5 */
-+ h_blank -= 58;
-+ /*for Control Period */
-+ h_blank -= 16;
-+
-+ samples = h_blank * 10;
-+ /* Number of Audio Packets (multiplied by 10) per Line (for 8 ch number
-+ * of Audio samples per line multiplied by 10 - Layout 1)
-+ */
-+ samples /= 32;
-+ samples *= crtc_info->v_active;
-+ /*Number of samples multiplied by 10, per second */
-+ samples *= crtc_info->refresh_rate;
-+ /*Number of Audio samples per second */
-+ samples /= 10;
-+
-+ /* @todo do it after deep color is implemented
-+ * 8xx - deep color bandwidth scaling
-+ * Extra bandwidth is avaliable in deep color b/c link runs faster than
-+ * pixel rate. This has the effect of allowing more tmds characters to
-+ * be transmitted during blank
-+ */
-+
-+ switch (crtc_info->color_depth) {
-+ case COLOR_DEPTH_888:
-+ samples *= 4;
-+ break;
-+ case COLOR_DEPTH_101010:
-+ samples *= 5;
-+ break;
-+ case COLOR_DEPTH_121212:
-+ samples *= 6;
-+ break;
-+ default:
-+ samples *= 4;
-+ break;
-+ }
-+
-+ samples /= 4;
-+
-+ /*check limitation*/
-+ if (samples < 88200)
-+ limit_freq_to_48_khz = true;
-+ else if (samples < 96000)
-+ limit_freq_to_88_2_khz = true;
-+ else if (samples < 176400)
-+ limit_freq_to_96_khz = true;
-+ else if (samples < 192000)
-+ limit_freq_to_174_4_khz = true;
-+
-+ if (sample_rates != NULL) {
-+ /* limit frequencies */
-+ if (limit_freq_to_174_4_khz)
-+ sample_rates->rate.RATE_192 = 0;
-+
-+ if (limit_freq_to_96_khz) {
-+ sample_rates->rate.RATE_192 = 0;
-+ sample_rates->rate.RATE_176_4 = 0;
-+ }
-+ if (limit_freq_to_88_2_khz) {
-+ sample_rates->rate.RATE_192 = 0;
-+ sample_rates->rate.RATE_176_4 = 0;
-+ sample_rates->rate.RATE_96 = 0;
-+ }
-+ if (limit_freq_to_48_khz) {
-+ sample_rates->rate.RATE_192 = 0;
-+ sample_rates->rate.RATE_176_4 = 0;
-+ sample_rates->rate.RATE_96 = 0;
-+ sample_rates->rate.RATE_88_2 = 0;
-+ }
-+ }
-+}
-+
-+/*For DP SST, calculate if specified sample rates can fit into a given timing */
-+void dal_audio_hw_ctx_check_audio_bandwidth_dpsst(
-+ const struct hw_ctx_audio *hw_ctx,
-+ const struct audio_crtc_info *crtc_info,
-+ uint32_t channel_count,
-+ union audio_sample_rates *sample_rates)
-+{
-+ /* do nothing */
-+}
-+
-+/*For DP MST, calculate if specified sample rates can fit into a given timing */
-+void dal_audio_hw_ctx_check_audio_bandwidth_dpmst(
-+ const struct hw_ctx_audio *hw_ctx,
-+ const struct audio_crtc_info *crtc_info,
-+ uint32_t channel_count,
-+ union audio_sample_rates *sample_rates)
-+{
-+ /* do nothing */
-+}
-+
-+/* calculate max number of Audio packets per line */
-+uint32_t dal_audio_hw_ctx_calc_max_audio_packets_per_line(
-+ const struct hw_ctx_audio *hw_ctx,
-+ const struct audio_crtc_info *crtc_info)
-+{
-+ uint32_t max_packets_per_line;
-+
-+ max_packets_per_line =
-+ crtc_info->h_total - crtc_info->h_active;
-+
-+ if (crtc_info->pixel_repetition)
-+ max_packets_per_line *= crtc_info->pixel_repetition;
-+
-+ /* for other hdmi features */
-+ max_packets_per_line -= 58;
-+ /* for Control Period */
-+ max_packets_per_line -= 16;
-+ /* Number of Audio Packets per Line */
-+ max_packets_per_line /= 32;
-+
-+ return max_packets_per_line;
-+}
-+
-+/**
-+* speakersToChannels
-+*
-+* @brief
-+* translate speakers to channels
-+*
-+* FL - Front Left
-+* FR - Front Right
-+* RL - Rear Left
-+* RR - Rear Right
-+* RC - Rear Center
-+* FC - Front Center
-+* FLC - Front Left Center
-+* FRC - Front Right Center
-+* RLC - Rear Left Center
-+* RRC - Rear Right Center
-+* LFE - Low Freq Effect
-+*
-+* FC
-+* FLC FRC
-+* FL FR
-+*
-+* LFE
-+* ()
-+*
-+*
-+* RL RR
-+* RLC RRC
-+* RC
-+*
-+* ch 8 7 6 5 4 3 2 1
-+* 0b00000011 - - - - - - FR FL
-+* 0b00000111 - - - - - LFE FR FL
-+* 0b00001011 - - - - FC - FR FL
-+* 0b00001111 - - - - FC LFE FR FL
-+* 0b00010011 - - - RC - - FR FL
-+* 0b00010111 - - - RC - LFE FR FL
-+* 0b00011011 - - - RC FC - FR FL
-+* 0b00011111 - - - RC FC LFE FR FL
-+* 0b00110011 - - RR RL - - FR FL
-+* 0b00110111 - - RR RL - LFE FR FL
-+* 0b00111011 - - RR RL FC - FR FL
-+* 0b00111111 - - RR RL FC LFE FR FL
-+* 0b01110011 - RC RR RL - - FR FL
-+* 0b01110111 - RC RR RL - LFE FR FL
-+* 0b01111011 - RC RR RL FC - FR FL
-+* 0b01111111 - RC RR RL FC LFE FR FL
-+* 0b11110011 RRC RLC RR RL - - FR FL
-+* 0b11110111 RRC RLC RR RL - LFE FR FL
-+* 0b11111011 RRC RLC RR RL FC - FR FL
-+* 0b11111111 RRC RLC RR RL FC LFE FR FL
-+* 0b11000011 FRC FLC - - - - FR FL
-+* 0b11000111 FRC FLC - - - LFE FR FL
-+* 0b11001011 FRC FLC - - FC - FR FL
-+* 0b11001111 FRC FLC - - FC LFE FR FL
-+* 0b11010011 FRC FLC - RC - - FR FL
-+* 0b11010111 FRC FLC - RC - LFE FR FL
-+* 0b11011011 FRC FLC - RC FC - FR FL
-+* 0b11011111 FRC FLC - RC FC LFE FR FL
-+* 0b11110011 FRC FLC RR RL - - FR FL
-+* 0b11110111 FRC FLC RR RL - LFE FR FL
-+* 0b11111011 FRC FLC RR RL FC - FR FL
-+* 0b11111111 FRC FLC RR RL FC LFE FR FL
-+*
-+* @param
-+* speakers - speaker information as it comes from CEA audio block
-+*/
-+/* translate speakers to channels */
-+union audio_cea_channels dal_audio_hw_ctx_speakers_to_channels(
-+ const struct hw_ctx_audio *hw_ctx,
-+ struct audio_speaker_flags speaker_flags)
-+{
-+ union audio_cea_channels cea_channels = {0};
-+
-+ /* these are one to one */
-+ cea_channels.channels.FL = speaker_flags.FL_FR;
-+ cea_channels.channels.FR = speaker_flags.FL_FR;
-+ cea_channels.channels.LFE = speaker_flags.LFE;
-+ cea_channels.channels.FC = speaker_flags.FC;
-+
-+ /* if Rear Left and Right exist move RC speaker to channel 7
-+ * otherwise to channel 5
-+ */
-+ if (speaker_flags.RL_RR) {
-+ cea_channels.channels.RL_RC = speaker_flags.RL_RR;
-+ cea_channels.channels.RR = speaker_flags.RL_RR;
-+ cea_channels.channels.RC_RLC_FLC = speaker_flags.RC;
-+ } else {
-+ cea_channels.channels.RL_RC = speaker_flags.RC;
-+ }
-+
-+ /* FRONT Left Right Center and REAR Left Right Center are exclusive */
-+ if (speaker_flags.FLC_FRC) {
-+ cea_channels.channels.RC_RLC_FLC = speaker_flags.FLC_FRC;
-+ cea_channels.channels.RRC_FRC = speaker_flags.FLC_FRC;
-+ } else {
-+ cea_channels.channels.RC_RLC_FLC = speaker_flags.RLC_RRC;
-+ cea_channels.channels.RRC_FRC = speaker_flags.RLC_RRC;
-+ }
-+
-+ return cea_channels;
-+}
-+
-+/* check whether specified audio format supported */
-+bool dal_audio_hw_ctx_is_audio_format_supported(
-+ const struct hw_ctx_audio *hw_ctx,
-+ const struct audio_info *audio_info,
-+ enum audio_format_code audio_format_code,
-+ uint32_t *format_index)
-+{
-+ uint32_t index;
-+ uint32_t max_channe_index = 0;
-+ bool found = false;
-+
-+ if (audio_info == NULL)
-+ return found;
-+
-+ /* pass through whole array */
-+ for (index = 0; index < audio_info->mode_count; index++) {
-+ if (audio_info->modes[index].format_code == audio_format_code) {
-+ if (found) {
-+ /* format has multiply entries, choose one with
-+ * highst number of channels */
-+ if (audio_info->modes[index].channel_count >
-+ audio_info->modes[max_channe_index].channel_count) {
-+ max_channe_index = index;
-+ }
-+ } else {
-+ /* format found, save it's index */
-+ found = true;
-+ max_channe_index = index;
-+ }
-+ }
-+ }
-+
-+ /* return index */
-+ if (found && format_index != NULL)
-+ *format_index = max_channe_index;
-+
-+ return found;
-+}
-+
-+/* search pixel clock value for HDMI */
-+bool dal_audio_hw_ctx_get_audio_clock_info(
-+ const struct hw_ctx_audio *hw_ctx,
-+ enum dc_color_depth color_depth,
-+ uint32_t crtc_pixel_clock_in_khz,
-+ uint32_t actual_pixel_clock_in_khz,
-+ struct audio_clock_info *audio_clock_info)
-+{
-+ const struct audio_clock_info *clock_info;
-+ uint32_t index;
-+ uint32_t crtc_pixel_clock_in_10khz = crtc_pixel_clock_in_khz / 10;
-+ uint32_t audio_array_size;
-+
-+ if (audio_clock_info == NULL)
-+ return false; /* should not happen */
-+
-+ switch (color_depth) {
-+ case COLOR_DEPTH_161616:
-+ clock_info = audio_clock_info_table_48bpc;
-+ audio_array_size = ARRAY_SIZE(
-+ audio_clock_info_table_48bpc);
-+ break;
-+ case COLOR_DEPTH_121212:
-+ clock_info = audio_clock_info_table_36bpc;
-+ audio_array_size = ARRAY_SIZE(
-+ audio_clock_info_table_36bpc);
-+ break;
-+ default:
-+ clock_info = audio_clock_info_table;
-+ audio_array_size = ARRAY_SIZE(
-+ audio_clock_info_table);
-+ break;
-+ }
-+
-+ if (clock_info != NULL) {
-+ /* search for exact pixel clock in table */
-+ for (index = 0; index < audio_array_size; index++) {
-+ if (clock_info[index].pixel_clock_in_10khz >
-+ crtc_pixel_clock_in_10khz)
-+ break; /* not match */
-+ else if (clock_info[index].pixel_clock_in_10khz ==
-+ crtc_pixel_clock_in_10khz) {
-+ /* match found */
-+ if (audio_clock_info != NULL) {
-+ *audio_clock_info = clock_info[index];
-+ return true;
-+ }
-+ }
-+ }
-+ }
-+
-+
-+ /* not found */
-+ if (actual_pixel_clock_in_khz == 0)
-+ actual_pixel_clock_in_khz = crtc_pixel_clock_in_khz;
-+
-+ /* See HDMI spec the table entry under
-+ * pixel clock of "Other". */
-+ audio_clock_info->pixel_clock_in_10khz =
-+ actual_pixel_clock_in_khz / 10;
-+ audio_clock_info->cts_32khz = actual_pixel_clock_in_khz;
-+ audio_clock_info->cts_44khz = actual_pixel_clock_in_khz;
-+ audio_clock_info->cts_48khz = actual_pixel_clock_in_khz;
-+
-+ audio_clock_info->n_32khz = 4096;
-+ audio_clock_info->n_44khz = 6272;
-+ audio_clock_info->n_48khz = 6144;
-+
-+ return true;
-+}
-+
-+static const struct hw_ctx_audio_funcs funcs = {
-+ .destroy = destroy,
-+ .setup_audio_wall_dto =
-+ setup_audio_wall_dto,
-+ .setup_hdmi_audio =
-+ setup_hdmi_audio,
-+ .setup_dp_audio = setup_dp_audio,
-+ .setup_vce_audio = setup_vce_audio,
-+ .enable_azalia_audio =
-+ enable_azalia_audio,
-+ .disable_azalia_audio =
-+ disable_azalia_audio,
-+ .enable_dp_audio =
-+ enable_dp_audio,
-+ .disable_dp_audio =
-+ disable_dp_audio,
-+ .setup_azalia =
-+ setup_azalia,
-+ .disable_az_clock_gating =
-+ disable_az_clock_gating,
-+ .unmute_azalia_audio =
-+ unmute_azalia_audio,
-+ .mute_azalia_audio =
-+ mute_azalia_audio,
-+ .setup_channel_splitting_mapping =
-+ setup_channel_splitting_mapping,
-+ .get_channel_splitting_mapping =
-+ get_channel_splitting_mapping,
-+ .set_unsolicited_response_payload =
-+ set_unsolicited_response_payload,
-+ .hw_initialize =
-+ hw_initialize,
-+ .enable_gtc_embedding_with_group =
-+ enable_gtc_embedding_with_group,
-+ .disable_gtc_embedding =
-+ disable_gtc_embedding,
-+ .get_azalia_clock_info_hdmi =
-+ get_azalia_clock_info_hdmi,
-+ .get_azalia_clock_info_dp =
-+ get_azalia_clock_info_dp,
-+};
-+/* --- object creator, destroy, construct, destruct --- */
-+
-+bool dal_audio_construct_hw_ctx_audio(
-+ struct hw_ctx_audio *ctx)
-+{
-+ ctx->funcs = &funcs;
-+
-+ /* internal variables */
-+
-+ return true;
-+}
-+
-+void dal_audio_destruct_hw_ctx_audio(
-+ struct hw_ctx_audio *ctx)
-+{
-+ /* nothing to do */
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/audio/hw_ctx_audio.h b/drivers/gpu/drm/amd/dal/dc/audio/hw_ctx_audio.h
-new file mode 100644
-index 0000000..8ab2e58
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/audio/hw_ctx_audio.h
-@@ -0,0 +1,285 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_HW_CTX_AUDIO_H__
-+#define __DAL_HW_CTX_AUDIO_H__
-+
-+#include "include/audio_interface.h"
-+#include "include/link_service_types.h"
-+
-+struct hw_ctx_audio;
-+
-+
-+struct azalia_reg_offsets {
-+ uint32_t azf0endpointx_azalia_f0_codec_endpoint_index;
-+ uint32_t azf0endpointx_azalia_f0_codec_endpoint_data;
-+};
-+
-+/***** hook functions *****/
-+
-+struct hw_ctx_audio_funcs {
-+
-+ /* functions for hw_ctx creation */
-+ void (*destroy)(
-+ struct hw_ctx_audio **ptr);
-+
-+ /***** from dal2 hwcontextaudio.hpp *****/
-+
-+ void (*setup_audio_wall_dto)(
-+ const struct hw_ctx_audio *hw_ctx,
-+ enum signal_type signal,
-+ const struct audio_crtc_info *crtc_info,
-+ const struct audio_pll_info *pll_info);
-+
-+ /* MM register access read_register write_register */
-+
-+ /***** from dal2 hwcontextaudio_hal.hpp *****/
-+
-+ /* setup HDMI audio */
-+ void (*setup_hdmi_audio)(
-+ const struct hw_ctx_audio *hw_ctx,
-+ enum engine_id engine_id,
-+ const struct audio_crtc_info *crtc_info);
-+
-+ /* setup DP audio */
-+ void (*setup_dp_audio)(
-+ const struct hw_ctx_audio *hw_ctx,
-+ enum engine_id engine_id);
-+
-+ /* setup VCE audio */
-+ void (*setup_vce_audio)(
-+ const struct hw_ctx_audio *hw_ctx);
-+
-+ /* enable Azalia audio */
-+ void (*enable_azalia_audio)(
-+ const struct hw_ctx_audio *hw_ctx,
-+ enum engine_id engine_id);
-+
-+ /* disable Azalia audio */
-+ void (*disable_azalia_audio)(
-+ const struct hw_ctx_audio *hw_ctx,
-+ enum engine_id engine_id);
-+
-+ /* enable DP audio */
-+ void (*enable_dp_audio)(
-+ const struct hw_ctx_audio *hw_ctx,
-+ enum engine_id engine_id);
-+
-+ /* disable DP audio */
-+ void (*disable_dp_audio)(
-+ const struct hw_ctx_audio *hw_ctx,
-+ enum engine_id engine_id);
-+
-+ /* setup Azalia HW block */
-+ void (*setup_azalia)(
-+ const struct hw_ctx_audio *hw_ctx,
-+ enum engine_id engine_id,
-+ enum signal_type signal,
-+ const struct audio_crtc_info *crtc_info,
-+ const struct audio_pll_info *pll_info,
-+ const struct audio_info *audio_info);
-+
-+ /* unmute audio */
-+ void (*unmute_azalia_audio)(
-+ const struct hw_ctx_audio *hw_ctx,
-+ enum engine_id engine_id);
-+
-+ /* mute audio */
-+ void (*mute_azalia_audio)(
-+ const struct hw_ctx_audio *hw_ctx,
-+ enum engine_id engine_id);
-+
-+ /* enable channel splitting mapping */
-+ void (*setup_channel_splitting_mapping)(
-+ const struct hw_ctx_audio *hw_ctx,
-+ enum engine_id engine_id,
-+ enum signal_type signal,
-+ const struct audio_channel_associate_info *audio_mapping,
-+ bool enable);
-+
-+ /* get current channel spliting */
-+ bool (*get_channel_splitting_mapping)(
-+ const struct hw_ctx_audio *hw_ctx,
-+ enum engine_id engine_id,
-+ struct audio_channel_associate_info *audio_mapping);
-+
-+ /* set the payload value for the unsolicited response */
-+ void (*set_unsolicited_response_payload)(
-+ const struct hw_ctx_audio *hw_ctx,
-+ enum audio_payload payload);
-+
-+ /* initialize HW state */
-+ void (*hw_initialize)(
-+ const struct hw_ctx_audio *hw_ctx);
-+
-+ /* check_audio_bandwidth */
-+
-+ /* Assign GTC group and enable GTC value embedding */
-+ void (*enable_gtc_embedding_with_group)(
-+ const struct hw_ctx_audio *hw_ctx,
-+ uint32_t groupNum,
-+ uint32_t audioLatency);
-+
-+ /* Disable GTC value embedding */
-+ void (*disable_gtc_embedding)(
-+ const struct hw_ctx_audio *hw_ctx);
-+
-+ /* Disable Azalia Clock Gating Feature */
-+ void (*disable_az_clock_gating)(
-+ const struct hw_ctx_audio *hw_ctx);
-+
-+ /* ~~~~ protected: ~~~~*/
-+
-+ /* calc_max_audio_packets_per_line */
-+ /* speakers_to_channels */
-+ /* is_audio_format_supported */
-+ /* get_audio_clock_info */
-+
-+ /* search pixel clock value for Azalia HDMI Audio */
-+ bool (*get_azalia_clock_info_hdmi)(
-+ const struct hw_ctx_audio *hw_ctx,
-+ uint32_t crtc_pixel_clock_in_khz,
-+ uint32_t actual_pixel_clock_in_khz,
-+ struct azalia_clock_info *azalia_clock_info);
-+
-+ /* search pixel clock value for Azalia DP Audio */
-+ bool (*get_azalia_clock_info_dp)(
-+ const struct hw_ctx_audio *hw_ctx,
-+ uint32_t requested_pixel_clock_in_khz,
-+ const struct audio_pll_info *pll_info,
-+ struct azalia_clock_info *azalia_clock_info);
-+
-+ void (*enable_afmt_clock)(
-+ const struct hw_ctx_audio *hw_ctx,
-+ enum engine_id engine_id,
-+ bool enable);
-+
-+ /* @@@@ private: @@@@ */
-+
-+ /* check_audio_bandwidth_hdmi */
-+ /* check_audio_bandwidth_dpsst */
-+ /* check_audio_bandwidth_dpmst */
-+
-+};
-+
-+
-+struct hw_ctx_audio {
-+ const struct hw_ctx_audio_funcs *funcs;
-+ struct dc_context *ctx;
-+
-+ /*audio_clock_infoTable[12];
-+ *audio_clock_infoTable_36bpc[12];
-+ *audio_clock_infoTable_48bpc[12];
-+ *used by hw_ctx_audio.c file only. Will declare as static array
-+ *azaliaclockinfoTable[12] -- not used
-+ *BusNumberMask; BusNumberShift; DeviceNumberMask;
-+ *not used by dce6 and after
-+ */
-+};
-+
-+
-+
-+/* --- object construct, destruct --- */
-+
-+/*
-+ *called by derived audio object for specific ASIC. In case no derived object,
-+ *these two functions do not need exposed.
-+ */
-+bool dal_audio_construct_hw_ctx_audio(
-+ struct hw_ctx_audio *hw_ctx);
-+
-+void dal_audio_destruct_hw_ctx_audio(
-+ struct hw_ctx_audio *hw_ctx);
-+
-+/*
-+ *creator of audio HW context will be implemented by specific ASIC object only.
-+ *Top base or interface object does not have implementation of creator.
-+ */
-+
-+
-+/* --- functions called by audio hw context itself --- */
-+
-+/* MM register access */
-+/*read_register - dal_read_reg */
-+/*write_register - dal_write_reg*/
-+
-+
-+/*check whether specified sample rates can fit into a given timing */
-+void dal_hw_ctx_audio_check_audio_bandwidth(
-+ const struct hw_ctx_audio *hw_ctx,
-+ const struct audio_crtc_info *crtc_info,
-+ uint32_t channel_count,
-+ enum signal_type signal,
-+ union audio_sample_rates *sample_rates);
-+
-+/*For HDMI, calculate if specified sample rates can fit into a given timing */
-+void dal_audio_hw_ctx_check_audio_bandwidth_hdmi(
-+ const struct hw_ctx_audio *hw_ctx,
-+ const struct audio_crtc_info *crtc_info,
-+ uint32_t channel_count,
-+ union audio_sample_rates *sample_rates);
-+
-+/*For DPSST, calculate if specified sample rates can fit into a given timing */
-+void dal_audio_hw_ctx_check_audio_bandwidth_dpsst(
-+ const struct hw_ctx_audio *hw_ctx,
-+ const struct audio_crtc_info *crtc_info,
-+ uint32_t channel_count,
-+ union audio_sample_rates *sample_rates);
-+
-+/*For DPMST, calculate if specified sample rates can fit into a given timing */
-+void dal_audio_hw_ctx_check_audio_bandwidth_dpmst(
-+ const struct hw_ctx_audio *hw_ctx,
-+ const struct audio_crtc_info *crtc_info,
-+ uint32_t channel_count,
-+ union audio_sample_rates *sample_rates);
-+
-+/* calculate max number of Audio packets per line */
-+uint32_t dal_audio_hw_ctx_calc_max_audio_packets_per_line(
-+ const struct hw_ctx_audio *hw_ctx,
-+ const struct audio_crtc_info *crtc_info);
-+
-+/* translate speakers to channels */
-+union audio_cea_channels dal_audio_hw_ctx_speakers_to_channels(
-+ const struct hw_ctx_audio *hw_ctx,
-+ struct audio_speaker_flags speaker_flags);
-+
-+/* check whether specified audio format supported */
-+bool dal_audio_hw_ctx_is_audio_format_supported(
-+ const struct hw_ctx_audio *hw_ctx,
-+ const struct audio_info *audio_info,
-+ enum audio_format_code audio_format_code,
-+ uint32_t *format_index);
-+
-+/* search pixel clock value for HDMI */
-+bool dal_audio_hw_ctx_get_audio_clock_info(
-+ const struct hw_ctx_audio *hw_ctx,
-+ enum dc_color_depth color_depth,
-+ uint32_t crtc_pixel_clock_in_khz,
-+ uint32_t actual_pixel_clock_in_khz,
-+ struct audio_clock_info *audio_clock_info);
-+
-+
-+#endif /* __DAL_HW_CTX_AUDIO_H__ */
-+
-diff --git a/drivers/gpu/drm/amd/dal/dc/basics/Makefile b/drivers/gpu/drm/amd/dal/dc/basics/Makefile
-new file mode 100644
-index 0000000..93e2371
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/basics/Makefile
-@@ -0,0 +1,10 @@
-+#
-+# Makefile for the 'utils' sub-component of DAL.
-+# It provides the general basic services required by other DAL
-+# subcomponents.
-+
-+BASICS = conversion.o fixpt31_32.o fixpt32_32.o grph_object_id.o logger.o register_logger.o signal_types.o vector.o
-+
-+AMD_DAL_BASICS = $(addprefix $(AMDDALPATH)/dc/basics/,$(BASICS))
-+
-+AMD_DAL_FILES += $(AMD_DAL_BASICS)
-diff --git a/drivers/gpu/drm/amd/dal/dc/basics/conversion.c b/drivers/gpu/drm/amd/dal/dc/basics/conversion.c
-new file mode 100644
-index 0000000..8c38206
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/basics/conversion.c
-@@ -0,0 +1,223 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+
-+#define DIVIDER 10000
-+
-+/* S2D13 value in [-3.00...0.9999] */
-+#define S2D13_MIN (-3 * DIVIDER)
-+#define S2D13_MAX (3 * DIVIDER)
-+
-+uint16_t fixed_point_to_int_frac(
-+ struct fixed31_32 arg,
-+ uint8_t integer_bits,
-+ uint8_t fractional_bits)
-+{
-+ int32_t numerator;
-+ int32_t divisor = 1 << fractional_bits;
-+
-+ uint16_t result;
-+
-+ uint16_t d = (uint16_t)dal_fixed31_32_floor(
-+ dal_fixed31_32_abs(
-+ arg));
-+
-+ if (d <= (uint16_t)(1 << integer_bits) - (1 / (uint16_t)divisor))
-+ numerator = (uint16_t)dal_fixed31_32_floor(
-+ dal_fixed31_32_mul_int(
-+ arg,
-+ divisor));
-+ else {
-+ numerator = dal_fixed31_32_floor(
-+ dal_fixed31_32_sub(
-+ dal_fixed31_32_from_int(
-+ 1LL << integer_bits),
-+ dal_fixed31_32_recip(
-+ dal_fixed31_32_from_int(
-+ divisor))));
-+ }
-+
-+ if (numerator >= 0)
-+ result = (uint16_t)numerator;
-+ else
-+ result = (uint16_t)(
-+ (1 << (integer_bits + fractional_bits + 1)) + numerator);
-+
-+ if ((result != 0) && dal_fixed31_32_lt(
-+ arg, dal_fixed31_32_zero))
-+ result |= 1 << (integer_bits + fractional_bits);
-+
-+ return result;
-+}
-+/**
-+* convert_float_matrix
-+* This converts a double into HW register spec defined format S2D13.
-+* @param :
-+* @return None
-+*/
-+void convert_float_matrix(
-+ uint16_t *matrix,
-+ struct fixed31_32 *flt,
-+ uint32_t buffer_size)
-+{
-+ const struct fixed31_32 min_2_13 =
-+ dal_fixed31_32_from_fraction(S2D13_MIN, DIVIDER);
-+ const struct fixed31_32 max_2_13 =
-+ dal_fixed31_32_from_fraction(S2D13_MAX, DIVIDER);
-+ uint32_t i;
-+
-+ for (i = 0; i < buffer_size; ++i) {
-+ uint32_t reg_value =
-+ fixed_point_to_int_frac(
-+ dal_fixed31_32_clamp(
-+ flt[i],
-+ min_2_13,
-+ max_2_13),
-+ 2,
-+ 13);
-+
-+ matrix[i] = (uint16_t)reg_value;
-+ }
-+}
-+
-+static void calculate_adjustments_common(
-+ const struct fixed31_32 *ideal_matrix,
-+ const struct dc_csc_adjustments *adjustments,
-+ struct fixed31_32 *matrix)
-+{
-+ const struct fixed31_32 sin_hue =
-+ dal_fixed31_32_sin(adjustments->hue);
-+ const struct fixed31_32 cos_hue =
-+ dal_fixed31_32_cos(adjustments->hue);
-+
-+ const struct fixed31_32 multiplier =
-+ dal_fixed31_32_mul(
-+ adjustments->contrast,
-+ adjustments->saturation);
-+
-+ matrix[0] = dal_fixed31_32_mul(
-+ ideal_matrix[0],
-+ adjustments->contrast);
-+
-+ matrix[1] = dal_fixed31_32_mul(
-+ ideal_matrix[1],
-+ adjustments->contrast);
-+
-+ matrix[2] = dal_fixed31_32_mul(
-+ ideal_matrix[2],
-+ adjustments->contrast);
-+
-+ matrix[4] = dal_fixed31_32_mul(
-+ multiplier,
-+ dal_fixed31_32_add(
-+ dal_fixed31_32_mul(
-+ ideal_matrix[8],
-+ sin_hue),
-+ dal_fixed31_32_mul(
-+ ideal_matrix[4],
-+ cos_hue)));
-+
-+ matrix[5] = dal_fixed31_32_mul(
-+ multiplier,
-+ dal_fixed31_32_add(
-+ dal_fixed31_32_mul(
-+ ideal_matrix[9],
-+ sin_hue),
-+ dal_fixed31_32_mul(
-+ ideal_matrix[5],
-+ cos_hue)));
-+
-+ matrix[6] = dal_fixed31_32_mul(
-+ multiplier,
-+ dal_fixed31_32_add(
-+ dal_fixed31_32_mul(
-+ ideal_matrix[10],
-+ sin_hue),
-+ dal_fixed31_32_mul(
-+ ideal_matrix[6],
-+ cos_hue)));
-+
-+ matrix[7] = ideal_matrix[7];
-+
-+ matrix[8] = dal_fixed31_32_mul(
-+ multiplier,
-+ dal_fixed31_32_sub(
-+ dal_fixed31_32_mul(
-+ ideal_matrix[8],
-+ cos_hue),
-+ dal_fixed31_32_mul(
-+ ideal_matrix[4],
-+ sin_hue)));
-+
-+ matrix[9] = dal_fixed31_32_mul(
-+ multiplier,
-+ dal_fixed31_32_sub(
-+ dal_fixed31_32_mul(
-+ ideal_matrix[9],
-+ cos_hue),
-+ dal_fixed31_32_mul(
-+ ideal_matrix[5],
-+ sin_hue)));
-+
-+ matrix[10] = dal_fixed31_32_mul(
-+ multiplier,
-+ dal_fixed31_32_sub(
-+ dal_fixed31_32_mul(
-+ ideal_matrix[10],
-+ cos_hue),
-+ dal_fixed31_32_mul(
-+ ideal_matrix[6],
-+ sin_hue)));
-+
-+ matrix[11] = ideal_matrix[11];
-+}
-+
-+void calculate_adjustments(
-+ const struct fixed31_32 *ideal_matrix,
-+ const struct dc_csc_adjustments *adjustments,
-+ struct fixed31_32 *matrix)
-+{
-+ calculate_adjustments_common(ideal_matrix, adjustments, matrix);
-+
-+ matrix[3] = dal_fixed31_32_add(
-+ ideal_matrix[3],
-+ dal_fixed31_32_mul(
-+ adjustments->brightness,
-+ dal_fixed31_32_from_fraction(86, 100)));
-+}
-+
-+void calculate_adjustments_y_only(
-+ const struct fixed31_32 *ideal_matrix,
-+ const struct dc_csc_adjustments *adjustments,
-+ struct fixed31_32 *matrix)
-+{
-+ calculate_adjustments_common(ideal_matrix, adjustments, matrix);
-+
-+ matrix[3] = dal_fixed31_32_add(
-+ ideal_matrix[3],
-+ adjustments->brightness);
-+}
-+
-diff --git a/drivers/gpu/drm/amd/dal/dc/basics/conversion.h b/drivers/gpu/drm/amd/dal/dc/basics/conversion.h
-new file mode 100644
-index 0000000..24ff473
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/basics/conversion.h
-@@ -0,0 +1,49 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_CONVERSION_H__
-+#define __DAL_CONVERSION_H__
-+
-+uint16_t fixed_point_to_int_frac(
-+ struct fixed31_32 arg,
-+ uint8_t integer_bits,
-+ uint8_t fractional_bits);
-+
-+void convert_float_matrix(
-+ uint16_t *matrix,
-+ struct fixed31_32 *flt,
-+ uint32_t buffer_size);
-+
-+void calculate_adjustments(
-+ const struct fixed31_32 *ideal_matrix,
-+ const struct dc_csc_adjustments *adjustments,
-+ struct fixed31_32 *matrix);
-+
-+void calculate_adjustments_y_only(
-+ const struct fixed31_32 *ideal_matrix,
-+ const struct dc_csc_adjustments *adjustments,
-+ struct fixed31_32 *matrix);
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/basics/fixpt31_32.c b/drivers/gpu/drm/amd/dal/dc/basics/fixpt31_32.c
-new file mode 100644
-index 0000000..6ce75b3
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/basics/fixpt31_32.c
-@@ -0,0 +1,692 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+#include "include/fixed31_32.h"
-+
-+static inline uint64_t abs_i64(
-+ int64_t arg)
-+{
-+ if (arg > 0)
-+ return (uint64_t)arg;
-+ else
-+ return (uint64_t)(-arg);
-+}
-+
-+/*
-+ * @brief
-+ * result = dividend / divisor
-+ * *remainder = dividend % divisor
-+ */
-+static inline uint64_t complete_integer_division_u64(
-+ uint64_t dividend,
-+ uint64_t divisor,
-+ uint64_t *remainder)
-+{
-+ uint64_t result;
-+
-+ ASSERT(divisor);
-+
-+ result = div64_u64_rem(dividend, divisor, remainder);
-+
-+ return result;
-+}
-+
-+#define BITS_PER_FRACTIONAL_PART \
-+ 32
-+
-+#define FRACTIONAL_PART_MASK \
-+ ((1ULL << BITS_PER_FRACTIONAL_PART) - 1)
-+
-+#define GET_INTEGER_PART(x) \
-+ ((x) >> BITS_PER_FRACTIONAL_PART)
-+
-+#define GET_FRACTIONAL_PART(x) \
-+ (FRACTIONAL_PART_MASK & (x))
-+
-+struct fixed31_32 dal_fixed31_32_from_fraction(
-+ int64_t numerator,
-+ int64_t denominator)
-+{
-+ struct fixed31_32 res;
-+
-+ bool arg1_negative = numerator < 0;
-+ bool arg2_negative = denominator < 0;
-+
-+ uint64_t arg1_value = arg1_negative ? -numerator : numerator;
-+ uint64_t arg2_value = arg2_negative ? -denominator : denominator;
-+
-+ uint64_t remainder;
-+
-+ /* determine integer part */
-+
-+ uint64_t res_value = complete_integer_division_u64(
-+ arg1_value, arg2_value, &remainder);
-+
-+ ASSERT(res_value <= LONG_MAX);
-+
-+ /* determine fractional part */
-+ {
-+ uint32_t i = BITS_PER_FRACTIONAL_PART;
-+
-+ do {
-+ remainder <<= 1;
-+
-+ res_value <<= 1;
-+
-+ if (remainder >= arg2_value) {
-+ res_value |= 1;
-+ remainder -= arg2_value;
-+ }
-+ } while (--i != 0);
-+ }
-+
-+ /* round up LSB */
-+ {
-+ uint64_t summand = (remainder << 1) >= arg2_value;
-+
-+ ASSERT(res_value <= LLONG_MAX - summand);
-+
-+ res_value += summand;
-+ }
-+
-+ res.value = (int64_t)res_value;
-+
-+ if (arg1_negative ^ arg2_negative)
-+ res.value = -res.value;
-+
-+ return res;
-+}
-+
-+struct fixed31_32 dal_fixed31_32_from_int(
-+ int64_t arg)
-+{
-+ struct fixed31_32 res;
-+
-+ ASSERT((LONG_MIN <= arg) && (arg <= LONG_MAX));
-+
-+ res.value = arg << BITS_PER_FRACTIONAL_PART;
-+
-+ return res;
-+}
-+
-+struct fixed31_32 dal_fixed31_32_neg(
-+ struct fixed31_32 arg)
-+{
-+ struct fixed31_32 res;
-+
-+ res.value = -arg.value;
-+
-+ return res;
-+}
-+
-+struct fixed31_32 dal_fixed31_32_abs(
-+ struct fixed31_32 arg)
-+{
-+ if (arg.value < 0)
-+ return dal_fixed31_32_neg(arg);
-+ else
-+ return arg;
-+}
-+
-+bool dal_fixed31_32_lt(
-+ struct fixed31_32 arg1,
-+ struct fixed31_32 arg2)
-+{
-+ return arg1.value < arg2.value;
-+}
-+
-+bool dal_fixed31_32_le(
-+ struct fixed31_32 arg1,
-+ struct fixed31_32 arg2)
-+{
-+ return arg1.value <= arg2.value;
-+}
-+
-+bool dal_fixed31_32_eq(
-+ struct fixed31_32 arg1,
-+ struct fixed31_32 arg2)
-+{
-+ return arg1.value == arg2.value;
-+}
-+
-+struct fixed31_32 dal_fixed31_32_min(
-+ struct fixed31_32 arg1,
-+ struct fixed31_32 arg2)
-+{
-+ if (arg1.value <= arg2.value)
-+ return arg1;
-+ else
-+ return arg2;
-+}
-+
-+struct fixed31_32 dal_fixed31_32_max(
-+ struct fixed31_32 arg1,
-+ struct fixed31_32 arg2)
-+{
-+ if (arg1.value <= arg2.value)
-+ return arg2;
-+ else
-+ return arg1;
-+}
-+
-+struct fixed31_32 dal_fixed31_32_clamp(
-+ struct fixed31_32 arg,
-+ struct fixed31_32 min_value,
-+ struct fixed31_32 max_value)
-+{
-+ if (dal_fixed31_32_le(arg, min_value))
-+ return min_value;
-+ else if (dal_fixed31_32_le(max_value, arg))
-+ return max_value;
-+ else
-+ return arg;
-+}
-+
-+struct fixed31_32 dal_fixed31_32_shl(
-+ struct fixed31_32 arg,
-+ uint8_t shift)
-+{
-+ struct fixed31_32 res;
-+
-+ ASSERT(((arg.value >= 0) && (arg.value <= LLONG_MAX >> shift)) ||
-+ ((arg.value < 0) && (arg.value >= LLONG_MIN >> shift)));
-+
-+ res.value = arg.value << shift;
-+
-+ return res;
-+}
-+
-+struct fixed31_32 dal_fixed31_32_shr(
-+ struct fixed31_32 arg,
-+ uint8_t shift)
-+{
-+ struct fixed31_32 res;
-+
-+ ASSERT(shift < 64);
-+
-+ res.value = arg.value >> shift;
-+
-+ return res;
-+}
-+
-+struct fixed31_32 dal_fixed31_32_add(
-+ struct fixed31_32 arg1,
-+ struct fixed31_32 arg2)
-+{
-+ struct fixed31_32 res;
-+
-+ ASSERT(((arg1.value >= 0) && (LLONG_MAX - arg1.value >= arg2.value)) ||
-+ ((arg1.value < 0) && (LLONG_MIN - arg1.value <= arg2.value)));
-+
-+ res.value = arg1.value + arg2.value;
-+
-+ return res;
-+}
-+
-+struct fixed31_32 dal_fixed31_32_sub_int(
-+ struct fixed31_32 arg1,
-+ int32_t arg2)
-+{
-+ return dal_fixed31_32_sub(
-+ arg1,
-+ dal_fixed31_32_from_int(arg2));
-+}
-+
-+struct fixed31_32 dal_fixed31_32_sub(
-+ struct fixed31_32 arg1,
-+ struct fixed31_32 arg2)
-+{
-+ struct fixed31_32 res;
-+
-+ ASSERT(((arg2.value >= 0) && (LLONG_MIN + arg2.value <= arg1.value)) ||
-+ ((arg2.value < 0) && (LLONG_MAX + arg2.value >= arg1.value)));
-+
-+ res.value = arg1.value - arg2.value;
-+
-+ return res;
-+}
-+
-+struct fixed31_32 dal_fixed31_32_mul_int(
-+ struct fixed31_32 arg1,
-+ int32_t arg2)
-+{
-+ return dal_fixed31_32_mul(
-+ arg1,
-+ dal_fixed31_32_from_int(arg2));
-+}
-+
-+struct fixed31_32 dal_fixed31_32_mul(
-+ struct fixed31_32 arg1,
-+ struct fixed31_32 arg2)
-+{
-+ struct fixed31_32 res;
-+
-+ bool arg1_negative = arg1.value < 0;
-+ bool arg2_negative = arg2.value < 0;
-+
-+ uint64_t arg1_value = arg1_negative ? -arg1.value : arg1.value;
-+ uint64_t arg2_value = arg2_negative ? -arg2.value : arg2.value;
-+
-+ uint64_t arg1_int = GET_INTEGER_PART(arg1_value);
-+ uint64_t arg2_int = GET_INTEGER_PART(arg2_value);
-+
-+ uint64_t arg1_fra = GET_FRACTIONAL_PART(arg1_value);
-+ uint64_t arg2_fra = GET_FRACTIONAL_PART(arg2_value);
-+
-+ uint64_t tmp;
-+
-+ res.value = arg1_int * arg2_int;
-+
-+ ASSERT(res.value <= LONG_MAX);
-+
-+ res.value <<= BITS_PER_FRACTIONAL_PART;
-+
-+ tmp = arg1_int * arg2_fra;
-+
-+ ASSERT(tmp <= (uint64_t)(LLONG_MAX - res.value));
-+
-+ res.value += tmp;
-+
-+ tmp = arg2_int * arg1_fra;
-+
-+ ASSERT(tmp <= (uint64_t)(LLONG_MAX - res.value));
-+
-+ res.value += tmp;
-+
-+ tmp = arg1_fra * arg2_fra;
-+
-+ tmp = (tmp >> BITS_PER_FRACTIONAL_PART) +
-+ (tmp >= (uint64_t)dal_fixed31_32_half.value);
-+
-+ ASSERT(tmp <= (uint64_t)(LLONG_MAX - res.value));
-+
-+ res.value += tmp;
-+
-+ if (arg1_negative ^ arg2_negative)
-+ res.value = -res.value;
-+
-+ return res;
-+}
-+
-+struct fixed31_32 dal_fixed31_32_sqr(
-+ struct fixed31_32 arg)
-+{
-+ struct fixed31_32 res;
-+
-+ uint64_t arg_value = abs_i64(arg.value);
-+
-+ uint64_t arg_int = GET_INTEGER_PART(arg_value);
-+
-+ uint64_t arg_fra = GET_FRACTIONAL_PART(arg_value);
-+
-+ uint64_t tmp;
-+
-+ res.value = arg_int * arg_int;
-+
-+ ASSERT(res.value <= LONG_MAX);
-+
-+ res.value <<= BITS_PER_FRACTIONAL_PART;
-+
-+ tmp = arg_int * arg_fra;
-+
-+ ASSERT(tmp <= (uint64_t)(LLONG_MAX - res.value));
-+
-+ res.value += tmp;
-+
-+ ASSERT(tmp <= (uint64_t)(LLONG_MAX - res.value));
-+
-+ res.value += tmp;
-+
-+ tmp = arg_fra * arg_fra;
-+
-+ tmp = (tmp >> BITS_PER_FRACTIONAL_PART) +
-+ (tmp >= (uint64_t)dal_fixed31_32_half.value);
-+
-+ ASSERT(tmp <= (uint64_t)(LLONG_MAX - res.value));
-+
-+ res.value += tmp;
-+
-+ return res;
-+}
-+
-+struct fixed31_32 dal_fixed31_32_div_int(
-+ struct fixed31_32 arg1,
-+ int64_t arg2)
-+{
-+ return dal_fixed31_32_from_fraction(
-+ arg1.value,
-+ dal_fixed31_32_from_int(arg2).value);
-+}
-+
-+struct fixed31_32 dal_fixed31_32_div(
-+ struct fixed31_32 arg1,
-+ struct fixed31_32 arg2)
-+{
-+ return dal_fixed31_32_from_fraction(
-+ arg1.value,
-+ arg2.value);
-+}
-+
-+struct fixed31_32 dal_fixed31_32_recip(
-+ struct fixed31_32 arg)
-+{
-+ /*
-+ * @note
-+ * Good idea to use Newton's method
-+ */
-+
-+ ASSERT(arg.value);
-+
-+ return dal_fixed31_32_from_fraction(
-+ dal_fixed31_32_one.value,
-+ arg.value);
-+}
-+
-+struct fixed31_32 dal_fixed31_32_sinc(
-+ struct fixed31_32 arg)
-+{
-+ struct fixed31_32 square;
-+
-+ struct fixed31_32 res = dal_fixed31_32_one;
-+
-+ int32_t n = 27;
-+
-+ struct fixed31_32 arg_norm = arg;
-+
-+ if (dal_fixed31_32_le(
-+ dal_fixed31_32_two_pi,
-+ dal_fixed31_32_abs(arg))) {
-+ arg_norm = dal_fixed31_32_sub(
-+ arg_norm,
-+ dal_fixed31_32_mul_int(
-+ dal_fixed31_32_two_pi,
-+ (int32_t)div64_s64(
-+ arg_norm.value,
-+ dal_fixed31_32_two_pi.value)));
-+ }
-+
-+ square = dal_fixed31_32_sqr(arg_norm);
-+
-+ do {
-+ res = dal_fixed31_32_sub(
-+ dal_fixed31_32_one,
-+ dal_fixed31_32_div_int(
-+ dal_fixed31_32_mul(
-+ square,
-+ res),
-+ n * (n - 1)));
-+
-+ n -= 2;
-+ } while (n > 2);
-+
-+ if (arg.value != arg_norm.value)
-+ res = dal_fixed31_32_div(
-+ dal_fixed31_32_mul(res, arg_norm),
-+ arg);
-+
-+ return res;
-+}
-+
-+struct fixed31_32 dal_fixed31_32_sin(
-+ struct fixed31_32 arg)
-+{
-+ return dal_fixed31_32_mul(
-+ arg,
-+ dal_fixed31_32_sinc(arg));
-+}
-+
-+struct fixed31_32 dal_fixed31_32_cos(
-+ struct fixed31_32 arg)
-+{
-+ /* TODO implement argument normalization */
-+
-+ const struct fixed31_32 square = dal_fixed31_32_sqr(arg);
-+
-+ struct fixed31_32 res = dal_fixed31_32_one;
-+
-+ int32_t n = 26;
-+
-+ do {
-+ res = dal_fixed31_32_sub(
-+ dal_fixed31_32_one,
-+ dal_fixed31_32_div_int(
-+ dal_fixed31_32_mul(
-+ square,
-+ res),
-+ n * (n - 1)));
-+
-+ n -= 2;
-+ } while (n != 0);
-+
-+ return res;
-+}
-+
-+/*
-+ * @brief
-+ * result = exp(arg),
-+ * where abs(arg) < 1
-+ *
-+ * Calculated as Taylor series.
-+ */
-+static struct fixed31_32 fixed31_32_exp_from_taylor_series(
-+ struct fixed31_32 arg)
-+{
-+ uint32_t n = 9;
-+
-+ struct fixed31_32 res = dal_fixed31_32_from_fraction(
-+ n + 2,
-+ n + 1);
-+ /* TODO find correct res */
-+
-+ ASSERT(dal_fixed31_32_lt(arg, dal_fixed31_32_one));
-+
-+ do
-+ res = dal_fixed31_32_add(
-+ dal_fixed31_32_one,
-+ dal_fixed31_32_div_int(
-+ dal_fixed31_32_mul(
-+ arg,
-+ res),
-+ n));
-+ while (--n != 1);
-+
-+ return dal_fixed31_32_add(
-+ dal_fixed31_32_one,
-+ dal_fixed31_32_mul(
-+ arg,
-+ res));
-+}
-+
-+struct fixed31_32 dal_fixed31_32_exp(
-+ struct fixed31_32 arg)
-+{
-+ /*
-+ * @brief
-+ * Main equation is:
-+ * exp(x) = exp(r + m * ln(2)) = (1 << m) * exp(r),
-+ * where m = round(x / ln(2)), r = x - m * ln(2)
-+ */
-+
-+ if (dal_fixed31_32_le(
-+ dal_fixed31_32_ln2_div_2,
-+ dal_fixed31_32_abs(arg))) {
-+ int32_t m = dal_fixed31_32_round(
-+ dal_fixed31_32_div(
-+ arg,
-+ dal_fixed31_32_ln2));
-+
-+ struct fixed31_32 r = dal_fixed31_32_sub(
-+ arg,
-+ dal_fixed31_32_mul_int(
-+ dal_fixed31_32_ln2,
-+ m));
-+
-+ ASSERT(m != 0);
-+
-+ ASSERT(dal_fixed31_32_lt(
-+ dal_fixed31_32_abs(r),
-+ dal_fixed31_32_one));
-+
-+ if (m > 0)
-+ return dal_fixed31_32_shl(
-+ fixed31_32_exp_from_taylor_series(r),
-+ (uint8_t)m);
-+ else
-+ return dal_fixed31_32_div_int(
-+ fixed31_32_exp_from_taylor_series(r),
-+ 1LL << -m);
-+ } else if (arg.value != 0)
-+ return fixed31_32_exp_from_taylor_series(arg);
-+ else
-+ return dal_fixed31_32_one;
-+}
-+
-+struct fixed31_32 dal_fixed31_32_log(
-+ struct fixed31_32 arg)
-+{
-+ struct fixed31_32 res = dal_fixed31_32_neg(dal_fixed31_32_one);
-+ /* TODO improve 1st estimation */
-+
-+ struct fixed31_32 error;
-+
-+ ASSERT(arg.value > 0);
-+ /* TODO if arg is negative, return NaN */
-+ /* TODO if arg is zero, return -INF */
-+
-+ do {
-+ struct fixed31_32 res1 = dal_fixed31_32_add(
-+ dal_fixed31_32_sub(
-+ res,
-+ dal_fixed31_32_one),
-+ dal_fixed31_32_div(
-+ arg,
-+ dal_fixed31_32_exp(res)));
-+
-+ error = dal_fixed31_32_sub(
-+ res,
-+ res1);
-+
-+ res = res1;
-+ /* TODO determine max_allowed_error based on quality of exp() */
-+ } while (abs_i64(error.value) > 100ULL);
-+
-+ return res;
-+}
-+
-+struct fixed31_32 dal_fixed31_32_pow(
-+ struct fixed31_32 arg1,
-+ struct fixed31_32 arg2)
-+{
-+ return dal_fixed31_32_exp(
-+ dal_fixed31_32_mul(
-+ dal_fixed31_32_log(arg1),
-+ arg2));
-+}
-+
-+int32_t dal_fixed31_32_floor(
-+ struct fixed31_32 arg)
-+{
-+ uint64_t arg_value = abs_i64(arg.value);
-+
-+ if (arg.value >= 0)
-+ return (int32_t)GET_INTEGER_PART(arg_value);
-+ else
-+ return -(int32_t)GET_INTEGER_PART(arg_value);
-+}
-+
-+int32_t dal_fixed31_32_round(
-+ struct fixed31_32 arg)
-+{
-+ uint64_t arg_value = abs_i64(arg.value);
-+
-+ const int64_t summand = dal_fixed31_32_half.value;
-+
-+ ASSERT(LLONG_MAX - (int64_t)arg_value >= summand);
-+
-+ arg_value += summand;
-+
-+ if (arg.value >= 0)
-+ return (int32_t)GET_INTEGER_PART(arg_value);
-+ else
-+ return -(int32_t)GET_INTEGER_PART(arg_value);
-+}
-+
-+int32_t dal_fixed31_32_ceil(
-+ struct fixed31_32 arg)
-+{
-+ uint64_t arg_value = abs_i64(arg.value);
-+
-+ const int64_t summand = dal_fixed31_32_one.value -
-+ dal_fixed31_32_epsilon.value;
-+
-+ ASSERT(LLONG_MAX - (int64_t)arg_value >= summand);
-+
-+ arg_value += summand;
-+
-+ if (arg.value >= 0)
-+ return (int32_t)GET_INTEGER_PART(arg_value);
-+ else
-+ return -(int32_t)GET_INTEGER_PART(arg_value);
-+}
-+
-+/* this function is a generic helper to translate fixed point value to
-+ * specified integer format that will consist of integer_bits integer part and
-+ * fractional_bits fractional part. For example it is used in
-+ * dal_fixed31_32_u2d19 to receive 2 bits integer part and 19 bits fractional
-+ * part in 32 bits. It is used in hw programming (scaler)
-+ */
-+
-+static inline uint32_t ux_dy(
-+ int64_t value,
-+ uint32_t integer_bits,
-+ uint32_t fractional_bits)
-+{
-+ /* 1. create mask of integer part */
-+ uint32_t result =
-+ (1 << integer_bits) - 1;
-+ /* 2. mask out fractional part */
-+ uint32_t fractional_part = FRACTIONAL_PART_MASK & value;
-+ /* 3. shrink fixed point integer part to be of integer_bits width*/
-+ result &= GET_INTEGER_PART(value);
-+ /* 4. make space for fractional part to be filled in after integer */
-+ result <<= fractional_bits;
-+ /* 5. shrink fixed point fractional part to of fractional_bits width*/
-+ fractional_part >>= BITS_PER_FRACTIONAL_PART - fractional_bits;
-+ /* 6. merge the result */
-+ return result | fractional_part;
-+}
-+
-+uint32_t dal_fixed31_32_u2d19(
-+ struct fixed31_32 arg)
-+{
-+ return ux_dy(arg.value, 2, 19);
-+}
-+
-+uint32_t dal_fixed31_32_u0d19(
-+ struct fixed31_32 arg)
-+{
-+ return ux_dy(arg.value, 0, 19);
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/basics/fixpt32_32.c b/drivers/gpu/drm/amd/dal/dc/basics/fixpt32_32.c
-new file mode 100644
-index 0000000..1140132
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/basics/fixpt32_32.c
-@@ -0,0 +1,223 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+#include "include/fixed32_32.h"
-+
-+static uint64_t u64_div(uint64_t n, uint64_t d)
-+{
-+ uint32_t i = 0;
-+ uint64_t r;
-+ uint64_t q = div64_u64_rem(n, d, &r);
-+
-+ for (i = 0; i < 32; ++i) {
-+ uint64_t sbit = q & (1ULL<<63);
-+
-+ r <<= 1;
-+ r |= sbit ? 1 : 0;
-+ q <<= 1;
-+ if (r >= d) {
-+ r -= d;
-+ q |= 1;
-+ }
-+ }
-+
-+ if (2*r >= d)
-+ q += 1;
-+ return q;
-+}
-+
-+struct fixed32_32 dal_fixed32_32_from_fraction(uint32_t n, uint32_t d)
-+{
-+ struct fixed32_32 fx;
-+
-+ fx.value = u64_div((uint64_t)n << 32, (uint64_t)d << 32);
-+ return fx;
-+}
-+
-+struct fixed32_32 dal_fixed32_32_from_int(uint32_t value)
-+{
-+ struct fixed32_32 fx;
-+
-+ fx.value = (uint64_t)value<<32;
-+ return fx;
-+}
-+
-+struct fixed32_32 dal_fixed32_32_add(
-+ struct fixed32_32 lhs,
-+ struct fixed32_32 rhs)
-+{
-+ struct fixed32_32 fx = {lhs.value + rhs.value};
-+
-+ ASSERT(fx.value >= rhs.value);
-+ return fx;
-+}
-+
-+struct fixed32_32 dal_fixed32_32_add_int(struct fixed32_32 lhs, uint32_t rhs)
-+{
-+ struct fixed32_32 fx = {lhs.value + ((uint64_t)rhs << 32)};
-+
-+ ASSERT(fx.value >= (uint64_t)rhs << 32);
-+ return fx;
-+
-+}
-+struct fixed32_32 dal_fixed32_32_sub(
-+ struct fixed32_32 lhs,
-+ struct fixed32_32 rhs)
-+{
-+ struct fixed32_32 fx;
-+
-+ ASSERT(lhs.value >= rhs.value);
-+ fx.value = lhs.value - rhs.value;
-+ return fx;
-+}
-+
-+struct fixed32_32 dal_fixed32_32_sub_int(struct fixed32_32 lhs, uint32_t rhs)
-+{
-+ struct fixed32_32 fx;
-+
-+ ASSERT(lhs.value >= ((uint64_t)rhs<<32));
-+ fx.value = lhs.value - ((uint64_t)rhs<<32);
-+ return fx;
-+}
-+
-+struct fixed32_32 dal_fixed32_32_mul(
-+ struct fixed32_32 lhs,
-+ struct fixed32_32 rhs)
-+{
-+ struct fixed32_32 fx;
-+ uint64_t lhs_int = lhs.value>>32;
-+ uint64_t lhs_frac = (uint32_t)lhs.value;
-+ uint64_t rhs_int = rhs.value>>32;
-+ uint64_t rhs_frac = (uint32_t)rhs.value;
-+ uint64_t ahbh = lhs_int * rhs_int;
-+ uint64_t ahbl = lhs_int * rhs_frac;
-+ uint64_t albh = lhs_frac * rhs_int;
-+ uint64_t albl = lhs_frac * rhs_frac;
-+
-+ ASSERT((ahbh>>32) == 0);
-+
-+ fx.value = (ahbh<<32) + ahbl + albh + (albl>>32);
-+ return fx;
-+
-+}
-+
-+struct fixed32_32 dal_fixed32_32_mul_int(struct fixed32_32 lhs, uint32_t rhs)
-+{
-+ struct fixed32_32 fx;
-+ uint64_t lhsi = (lhs.value>>32) * (uint64_t)rhs;
-+ uint64_t lhsf;
-+
-+ ASSERT((lhsi>>32) == 0);
-+ lhsf = ((uint32_t)lhs.value) * (uint64_t)rhs;
-+ ASSERT((lhsi<<32) + lhsf >= lhsf);
-+ fx.value = (lhsi<<32) + lhsf;
-+ return fx;
-+}
-+
-+
-+
-+struct fixed32_32 dal_fixed32_32_div(
-+ struct fixed32_32 lhs,
-+ struct fixed32_32 rhs)
-+{
-+ struct fixed32_32 fx;
-+
-+ fx.value = u64_div(lhs.value, rhs.value);
-+ return fx;
-+}
-+
-+struct fixed32_32 dal_fixed32_32_div_int(struct fixed32_32 lhs, uint32_t rhs)
-+{
-+ struct fixed32_32 fx;
-+
-+ fx.value = u64_div(lhs.value, (uint64_t)rhs << 32);
-+ return fx;
-+}
-+
-+struct fixed32_32 dal_fixed32_32_min(
-+ struct fixed32_32 lhs,
-+ struct fixed32_32 rhs)
-+{
-+ return (lhs.value < rhs.value) ? lhs : rhs;
-+}
-+
-+struct fixed32_32 dal_fixed32_32_max(
-+ struct fixed32_32 lhs,
-+ struct fixed32_32 rhs)
-+{
-+ return (lhs.value > rhs.value) ? lhs : rhs;
-+}
-+
-+bool dal_fixed32_32_gt(struct fixed32_32 lhs, struct fixed32_32 rhs)
-+{
-+ return lhs.value > rhs.value;
-+}
-+bool dal_fixed32_32_gt_int(struct fixed32_32 lhs, uint32_t rhs)
-+{
-+ return lhs.value > ((uint64_t)rhs<<32);
-+}
-+
-+bool dal_fixed32_32_lt(struct fixed32_32 lhs, struct fixed32_32 rhs)
-+{
-+ return lhs.value < rhs.value;
-+}
-+
-+bool dal_fixed32_32_le(struct fixed32_32 lhs, struct fixed32_32 rhs)
-+{
-+ return lhs.value <= rhs.value;
-+}
-+
-+bool dal_fixed32_32_lt_int(struct fixed32_32 lhs, uint32_t rhs)
-+{
-+ return lhs.value < ((uint64_t)rhs<<32);
-+}
-+
-+bool dal_fixed32_32_le_int(struct fixed32_32 lhs, uint32_t rhs)
-+{
-+ return lhs.value <= ((uint64_t)rhs<<32);
-+}
-+
-+uint32_t dal_fixed32_32_ceil(struct fixed32_32 v)
-+{
-+ ASSERT((uint32_t)v.value ? (v.value >> 32) + 1 >= 1 : true);
-+ return (v.value>>32) + ((uint32_t)v.value ? 1 : 0);
-+}
-+
-+uint32_t dal_fixed32_32_floor(struct fixed32_32 v)
-+{
-+ return v.value>>32;
-+}
-+
-+uint32_t dal_fixed32_32_round(struct fixed32_32 v)
-+{
-+ ASSERT(v.value + (1ULL<<31) >= (1ULL<<31));
-+ return (v.value + (1ULL<<31))>>32;
-+}
-+
-+bool dal_fixed32_32_eq(struct fixed32_32 lhs, struct fixed32_32 rhs)
-+{
-+ return lhs.value == rhs.value;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/basics/grph_object_id.c b/drivers/gpu/drm/amd/dal/dc/basics/grph_object_id.c
-new file mode 100644
-index 0000000..8276f9d
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/basics/grph_object_id.c
-@@ -0,0 +1,135 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+
-+#include "include/grph_object_id.h"
-+
-+bool dal_graphics_object_id_is_valid(struct graphics_object_id id)
-+{
-+ bool rc = true;
-+
-+ switch (id.type) {
-+ case OBJECT_TYPE_UNKNOWN:
-+ rc = false;
-+ break;
-+ case OBJECT_TYPE_GPU:
-+ case OBJECT_TYPE_ENGINE:
-+ /* do NOT check for id.id == 0 */
-+ if (id.enum_id == ENUM_ID_UNKNOWN)
-+ rc = false;
-+ break;
-+ default:
-+ if (id.id == 0 || id.enum_id == ENUM_ID_UNKNOWN)
-+ rc = false;
-+ break;
-+ }
-+
-+ return rc;
-+}
-+
-+bool dal_graphics_object_id_is_equal(
-+ struct graphics_object_id id1,
-+ struct graphics_object_id id2)
-+{
-+ if (false == dal_graphics_object_id_is_valid(id1)) {
-+ dal_output_to_console(
-+ "%s: Warning: comparing invalid object 'id1'!\n", __func__);
-+ return false;
-+ }
-+
-+ if (false == dal_graphics_object_id_is_valid(id2)) {
-+ dal_output_to_console(
-+ "%s: Warning: comparing invalid object 'id2'!\n", __func__);
-+ return false;
-+ }
-+
-+ if (id1.id == id2.id && id1.enum_id == id2.enum_id
-+ && id1.type == id2.type)
-+ return true;
-+
-+ return false;
-+}
-+
-+/* Based on internal data members memory layout */
-+uint32_t dal_graphics_object_id_to_uint(struct graphics_object_id id)
-+{
-+ uint32_t object_id = 0;
-+
-+ object_id = id.id + (id.enum_id << 0x8) + (id.type << 0xc);
-+ return object_id;
-+}
-+
-+/*
-+ * ******* get specific ID - internal safe cast into specific type *******
-+ */
-+
-+enum controller_id dal_graphics_object_id_get_controller_id(
-+ struct graphics_object_id id)
-+{
-+ if (id.type == OBJECT_TYPE_CONTROLLER)
-+ return id.id;
-+ return CONTROLLER_ID_UNDEFINED;
-+}
-+
-+enum clock_source_id dal_graphics_object_id_get_clock_source_id(
-+ struct graphics_object_id id)
-+{
-+ if (id.type == OBJECT_TYPE_CLOCK_SOURCE)
-+ return id.id;
-+ return CLOCK_SOURCE_ID_UNDEFINED;
-+}
-+
-+enum encoder_id dal_graphics_object_id_get_encoder_id(
-+ struct graphics_object_id id)
-+{
-+ if (id.type == OBJECT_TYPE_ENCODER)
-+ return id.id;
-+ return ENCODER_ID_UNKNOWN;
-+}
-+
-+enum connector_id dal_graphics_object_id_get_connector_id(
-+ struct graphics_object_id id)
-+{
-+ if (id.type == OBJECT_TYPE_CONNECTOR)
-+ return id.id;
-+ return CONNECTOR_ID_UNKNOWN;
-+}
-+
-+enum audio_id dal_graphics_object_id_get_audio_id(struct graphics_object_id id)
-+{
-+ if (id.type == OBJECT_TYPE_AUDIO)
-+ return id.id;
-+ return AUDIO_ID_UNKNOWN;
-+}
-+
-+enum engine_id dal_graphics_object_id_get_engine_id(
-+ struct graphics_object_id id)
-+{
-+ if (id.type == OBJECT_TYPE_ENGINE)
-+ return id.id;
-+ return ENGINE_ID_UNKNOWN;
-+}
-+
-diff --git a/drivers/gpu/drm/amd/dal/dc/basics/logger.c b/drivers/gpu/drm/amd/dal/dc/basics/logger.c
-new file mode 100644
-index 0000000..50db743
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/basics/logger.c
-@@ -0,0 +1,947 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+#include <stdarg.h>
-+#include "dal_services.h"
-+#include "include/dal_types.h"
-+#include "include/logger_interface.h"
-+#include "logger.h"
-+
-+/* TODO: for now - empty, use DRM defines from dal services.
-+ Need to define appropriate levels of prints, and implement
-+ this component
-+void dal_log(const char *format, ...)
-+{
-+}
-+*/
-+
-+/* ----------- Logging Major/Minor names ------------ */
-+
-+#define NUM_ELEMENTS(a) (sizeof(a) / sizeof((a)[0]))
-+
-+static const struct log_minor_info component_minor_info_tbl[] = {
-+ {LOG_MINOR_COMPONENT_LINK_SERVICE, "LS"},
-+ {LOG_MINOR_COMPONENT_DAL_INTERFACE, "DalIf"},
-+ {LOG_MINOR_COMPONENT_HWSS, "HWSS"},
-+ {LOG_MINOR_COMPONENT_ADAPTER_SERVICE, "AS"},
-+ {LOG_MINOR_COMPONENT_DISPLAY_SERVICE, "DS"},
-+ {LOG_MINOR_COMPONENT_TOPOLOGY_MANAGER, "TM"},
-+ {LOG_MINOR_COMPONENT_ENCODER, "Encoder"},
-+ {LOG_MINOR_COMPONENT_I2C_AUX, "I2cAux"},
-+ {LOG_MINOR_COMPONENT_AUDIO, "Audio"},
-+ {LOG_MINOR_COMPONENT_DISPLAY_CAPABILITY_SERVICE, "Dcs"},
-+ {LOG_MINOR_COMPONENT_DMCU, "Dmcu"},
-+ {LOG_MINOR_COMPONENT_GPU, "GPU"},
-+ {LOG_MINOR_COMPONENT_CONTROLLER, "Cntrlr"},
-+ {LOG_MINOR_COMPONENT_ISR, "ISR"},
-+ {LOG_MINOR_COMPONENT_BIOS, "BIOS"},
-+ {LOG_MINOR_COMPONENT_DC, "DC"},
-+ {LOG_MINOR_COMPONENT_IRQ_SERVICE, "IRQ SERVICE"},
-+
-+};
-+
-+static const struct log_minor_info hw_trace_minor_info_tbl[] = {
-+ {LOG_MINOR_HW_TRACE_MST, "Mst" },
-+ {LOG_MINOR_HW_TRACE_TRAVIS, "Travis" },
-+ {LOG_MINOR_HW_TRACE_HOTPLUG, "Hotplug" },
-+ {LOG_MINOR_HW_TRACE_LINK_TRAINING, "LinkTraining" },
-+ {LOG_MINOR_HW_TRACE_SET_MODE, "SetMode" },
-+ {LOG_MINOR_HW_TRACE_RESUME_S3, "ResumeS3" },
-+ {LOG_MINOR_HW_TRACE_RESUME_S4, "ResumeS4" },
-+ {LOG_MINOR_HW_TRACE_BOOTUP, "BootUp" },
-+ {LOG_MINOR_HW_TRACE_AUDIO, "Audio"},
-+ {LOG_MINOR_HW_TRACE_HPD_IRQ, "HpdIrq" },
-+ {LOG_MINOR_HW_TRACE_INTERRUPT, "Interrupt" },
-+ {LOG_MINOR_HW_TRACE_MPO, "Planes" },
-+};
-+
-+static const struct log_minor_info mst_minor_info_tbl[] = {
-+ {LOG_MINOR_MST_IRQ_HPD_RX, "IrqHpdRx"},
-+ {LOG_MINOR_MST_IRQ_TIMER, "IrqTimer"},
-+ {LOG_MINOR_MST_NATIVE_AUX, "NativeAux"},
-+ {LOG_MINOR_MST_SIDEBAND_MSG, "SB"},
-+ {LOG_MINOR_MST_MSG_TRANSACTION, "MT"},
-+ {LOG_MINOR_MST_SIDEBAND_MSG_PARSED, "SB Parsed"},
-+ {LOG_MINOR_MST_MSG_TRANSACTION_PARSED, "MT Parsed"},
-+ {LOG_MINOR_MST_AUX_MSG_DPCD_ACCESS, "AuxMsgDpcdAccess"},
-+ {LOG_MINOR_MST_PROGRAMMING, "Programming"},
-+ {LOG_MINOR_MST_TOPOLOGY_DISCOVERY, "TopologyDiscovery"},
-+ {LOG_MINOR_MST_CONVERTER_CAPS, "ConverterCaps"},
-+};
-+
-+static const struct log_minor_info dcs_minor_info_tbl[] = {
-+ {LOG_MINOR_DCS_EDID_EMULATOR, "EdidEmul"},
-+ {LOG_MINOR_DCS_DONGLE_DETECTION, "DongleDetect"},
-+};
-+
-+static const struct log_minor_info dcp_minor_info_tbl[] = {
-+ { LOG_MINOR_DCP_GAMMA_GRPH, "GammaGrph"},
-+ { LOG_MINOR_DCP_GAMMA_OVL, "GammaOvl"},
-+ { LOG_MINOR_DCP_CSC_GRPH, "CscGrph"},
-+ { LOG_MINOR_DCP_CSC_OVL, "CscOvl"},
-+ { LOG_MINOR_DCP_SCALER, "Scaler"},
-+ { LOG_MINOR_DCP_SCALER_TABLES, "ScalerTables"},
-+};
-+
-+static const struct log_minor_info bios_minor_info_tbl[] = {
-+ {LOG_MINOR_BIOS_CMD_TABLE, "CmdTbl"},
-+};
-+
-+static const struct log_minor_info reg_minor_info_tbl[] = {
-+ {LOG_MINOR_REGISTER_INDEX, "Index"},
-+};
-+
-+static const struct log_minor_info info_packet_minor_info_tbl[] = {
-+ {LOG_MINOR_INFO_PACKETS_HDMI, "Hdmi"},
-+};
-+
-+
-+static const struct log_minor_info dsat_minor_info_tbl[] = {
-+ {LOG_MINOR_DSAT_LOGGER, "Logger"},
-+ {LOG_MINOR_DSAT_EDID_OVERRIDE, "EDID_Override"},
-+};
-+
-+static const struct log_minor_info ec_minor_info_tbl[] = {
-+ {LOG_MINOR_EC_PPLIB_NOTIFY, "PPLib_Notify" }, /* PPLib notifies DAL */
-+ {LOG_MINOR_EC_PPLIB_QUERY, "PPLib_Query" } /* DAL requested info from
-+ PPLib */
-+};
-+
-+static const struct log_minor_info bwm_minor_info_tbl[] = {
-+ {LOG_MINOR_BWM_MODE_VALIDATION, "ModeValidation"},
-+ {LOG_MINOR_BWM_REQUIRED_BANDWIDTH_CALCS, "Req_Bandw_Calcs"}
-+};
-+
-+static const struct log_minor_info mode_enum_minor_info_tbl[] = {
-+ {LOG_MINOR_MODE_ENUM_BEST_VIEW_CANDIDATES, "BestviewCandidates"},
-+ {LOG_MINOR_MODE_ENUM_VIEW_SOLUTION, "ViewSolution"},
-+ {LOG_MINOR_MODE_ENUM_TS_LIST_BUILD, "TsListBuild"},
-+ {LOG_MINOR_MODE_ENUM_TS_LIST, "TsList"},
-+ {LOG_MINOR_MODE_ENUM_MASTER_VIEW_LIST, "MasterViewList"},
-+ {LOG_MINOR_MODE_ENUM_MASTER_VIEW_LIST_UPDATE, "MasterViewListUpdate"},
-+};
-+
-+static const struct log_minor_info i2caux_minor_info_tbl[] = {
-+ {LOG_MINOR_I2C_AUX_LOG, "Log"},
-+ {LOG_MINOR_I2C_AUX_AUX_TIMESTAMP, "Timestamp"},
-+ {LOG_MINOR_I2C_AUX_CFG, "Config"}
-+};
-+
-+static const struct log_minor_info line_buffer_minor_info_tbl[] = {
-+ {LOG_MINOR_LINE_BUFFER_POWERGATING, "PowerGating"}
-+};
-+
-+static const struct log_minor_info hwss_minor_info_tbl[] = {
-+ {LOG_MINOR_HWSS_TAPS_VALIDATION, "HWSS Taps"}
-+};
-+
-+static const struct log_minor_info optimization_minor_info_tbl[] = {
-+ {LOG_MINOR_OPTMZ_GENERAL, "General Optimizations"},
-+ {LOG_MINOR_OPTMZ_DO_NOT_TURN_OFF_VCC_DURING_SET_MODE,
-+ "Skip Vcc Off During Set Mode"}
-+};
-+
-+static const struct log_minor_info perf_measure_minor_info_tbl[] = {
-+ {LOG_MINOR_PERF_MEASURE_GENERAL, "General Performance Measurement"},
-+ {LOG_MINOR_PERF_MEASURE_HEAP_MEMORY, "Heap Memory Management"}
-+};
-+
-+static const struct log_minor_info sync_minor_info_tbl[] = {
-+ {LOG_MINOR_SYNC_HW_CLOCK_ADJUST, "Pixel Rate Tune-up"},
-+ {LOG_MINOR_SYNC_TIMING, "Timing"}
-+};
-+
-+static const struct log_minor_info backlight_minor_info_tbl[] = {
-+ {LOG_MINOR_BACKLIGHT_BRIGHTESS_CAPS, "Caps"},
-+ {LOG_MINOR_BACKLIGHT_DMCU_DELTALUT, "DMCU Delta LUT"},
-+ {LOG_MINOR_BACKLIGHT_DMCU_BUILD_DELTALUT, "Build DMCU Delta LUT"},
-+ {LOG_MINOR_BACKLIGHT_INTERFACE, "Interface"},
-+ {LOG_MINOR_BACKLIGHT_LID, "Lid Status"}
-+};
-+
-+
-+static const struct log_minor_info override_feature_minor_info_tbl[] = {
-+ {LOG_MINOR_FEATURE_OVERRIDE, "overriden feature"},
-+};
-+
-+static const struct log_minor_info detection_minor_info_tbl[] = {
-+ {LOG_MINOR_DETECTION_EDID_PARSER, "EDID Parser"},
-+ {LOG_MINOR_DETECTION_DP_CAPS, "DP caps"},
-+};
-+
-+static const struct log_minor_info tm_minor_info_tbl[] = {
-+ {LOG_MINOR_TM_INFO, "INFO"},
-+ {LOG_MINOR_TM_IFACE_TRACE, "IFACE_TRACE"},
-+ {LOG_MINOR_TM_RESOURCES, "RESOURCES"},
-+ {LOG_MINOR_TM_ENCODER_CTL, "ENCODER_CTL"},
-+ {LOG_MINOR_TM_ENG_ASN, "ENG_ASN"},
-+ {LOG_MINOR_TM_CONTROLLER_ASN, "CONTROLLER_ASN"},
-+ {LOG_MINOR_TM_PWR_GATING, "PWR_GATING"},
-+ {LOG_MINOR_TM_BUILD_DSP_PATH, "BUILD_PATH"},
-+ {LOG_MINOR_TM_DISPLAY_DETECT, "DISPLAY_DETECT"},
-+ {LOG_MINOR_TM_LINK_SRV, "LINK_SRV"},
-+ {LOG_MINOR_TM_NOT_IMPLEMENTED, "NOT_IMPL"},
-+ {LOG_MINOR_TM_COFUNC_PATH, "COFUNC_PATH"}
-+};
-+
-+static const struct log_minor_info ds_minor_info_tbl[] = {
-+ {LOG_MINOR_DS_MODE_SETTING, "Mode_Setting"},
-+};
-+
-+
-+struct log_major_mask_info {
-+ struct log_major_info major_info;
-+ uint32_t default_mask;
-+ const struct log_minor_info *minor_tbl;
-+ uint32_t tbl_element_cnt;
-+};
-+
-+/* A mask for each Major.
-+ * Use a mask or zero. */
-+#define LG_ERR_MSK 0xffffffff
-+#define LG_WRN_MSK 0xffffffff
-+#define LG_TM_MSK (1 << LOG_MINOR_TM_INFO)
-+#define LG_FO_MSK (1 << LOG_MINOR_FEATURE_OVERRIDE)
-+#define LG_EC_MSK ((1 << LOG_MINOR_EC_PPLIB_NOTIFY) | \
-+ (1 << LOG_MINOR_EC_PPLIB_QUERY))
-+#define LG_DSAT_MSK (1 << LOG_MINOR_DSAT_EDID_OVERRIDE)
-+#define LG_DT_MSK (1 << LOG_MINOR_DETECTION_EDID_PARSER)
-+
-+/* IFT - InterFaceTrace */
-+#define LG_IFT_MSK (1 << LOG_MINOR_COMPONENT_DC)
-+
-+
-+#define LG_HW_TR_AUD_MSK (1 << LOG_MINOR_HW_TRACE_AUDIO)
-+#define LG_HW_TR_INTERRUPT_MSK (1 << LOG_MINOR_HW_TRACE_INTERRUPT) | \
-+ (1 << LOG_MINOR_HW_TRACE_HPD_IRQ)
-+#define LG_HW_TR_PLANES_MSK (1 << LOG_MINOR_HW_TRACE_MPO)
-+#define LG_ALL_MSK 0xffffffff
-+
-+#define LG_SYNC_MSK (1 << LOG_MINOR_SYNC_TIMING)
-+
-+#define LG_BWM_MSK (1 << LOG_MINOR_BWM_MODE_VALIDATION)
-+
-+
-+static const struct log_major_mask_info log_major_mask_info_tbl[] = {
-+ /* LogMajor major name default MinorTble tblElementCnt */
-+ {{LOG_MAJOR_ERROR, "Error" }, LG_ALL_MSK, component_minor_info_tbl, NUM_ELEMENTS(component_minor_info_tbl)},
-+ {{LOG_MAJOR_WARNING, "Warning" }, LG_ALL_MSK, component_minor_info_tbl, NUM_ELEMENTS(component_minor_info_tbl)},
-+ {{LOG_MAJOR_INTERFACE_TRACE, "IfTrace" }, LG_ALL_MSK, component_minor_info_tbl, NUM_ELEMENTS(component_minor_info_tbl)},
-+ {{LOG_MAJOR_HW_TRACE, "HwTrace" }, (LG_ALL_MSK &
-+ ~((1 << LOG_MINOR_HW_TRACE_LINK_TRAINING) |
-+ (1 << LOG_MINOR_HW_TRACE_AUDIO))),
-+ hw_trace_minor_info_tbl, NUM_ELEMENTS(hw_trace_minor_info_tbl)},
-+ {{LOG_MAJOR_MST, "MST" }, LG_ALL_MSK, mst_minor_info_tbl, NUM_ELEMENTS(mst_minor_info_tbl)},
-+ {{LOG_MAJOR_DCS, "DCS" }, LG_ALL_MSK, dcs_minor_info_tbl, NUM_ELEMENTS(dcs_minor_info_tbl)},
-+ {{LOG_MAJOR_DCP, "DCP" }, LG_ALL_MSK, dcp_minor_info_tbl, NUM_ELEMENTS(dcp_minor_info_tbl)},
-+ {{LOG_MAJOR_BIOS, "Bios" }, LG_ALL_MSK, bios_minor_info_tbl, NUM_ELEMENTS(bios_minor_info_tbl)},
-+ {{LOG_MAJOR_REGISTER, "Register" }, LG_ALL_MSK, reg_minor_info_tbl, NUM_ELEMENTS(reg_minor_info_tbl)},
-+ {{LOG_MAJOR_INFO_PACKETS, "InfoPacket" }, LG_ALL_MSK, info_packet_minor_info_tbl, NUM_ELEMENTS(info_packet_minor_info_tbl)},
-+ {{LOG_MAJOR_DSAT, "DSAT" }, LG_ALL_MSK, dsat_minor_info_tbl, NUM_ELEMENTS(dsat_minor_info_tbl)},
-+ {{LOG_MAJOR_EC, "EC" }, LG_ALL_MSK, ec_minor_info_tbl, NUM_ELEMENTS(ec_minor_info_tbl)},
-+ {{LOG_MAJOR_BWM, "BWM" }, LG_BWM_MSK, bwm_minor_info_tbl, NUM_ELEMENTS(bwm_minor_info_tbl)},
-+ {{LOG_MAJOR_MODE_ENUM, "ModeEnum" }, LG_ALL_MSK, mode_enum_minor_info_tbl, NUM_ELEMENTS(mode_enum_minor_info_tbl)},
-+ {{LOG_MAJOR_I2C_AUX, "I2cAux" }, LG_ALL_MSK, i2caux_minor_info_tbl, NUM_ELEMENTS(i2caux_minor_info_tbl)},
-+ {{LOG_MAJOR_LINE_BUFFER, "LineBuffer" }, LG_ALL_MSK, line_buffer_minor_info_tbl, NUM_ELEMENTS(line_buffer_minor_info_tbl)},
-+ {{LOG_MAJOR_HWSS, "HWSS" }, LG_ALL_MSK, hwss_minor_info_tbl, NUM_ELEMENTS(hwss_minor_info_tbl)},
-+ {{LOG_MAJOR_OPTIMIZATION, "Optimization"}, LG_ALL_MSK, optimization_minor_info_tbl, NUM_ELEMENTS(optimization_minor_info_tbl)},
-+ {{LOG_MAJOR_PERF_MEASURE, "PerfMeasure" }, LG_ALL_MSK, perf_measure_minor_info_tbl, NUM_ELEMENTS(perf_measure_minor_info_tbl)},
-+ {{LOG_MAJOR_SYNC, "Sync" }, LG_SYNC_MSK,sync_minor_info_tbl, NUM_ELEMENTS(sync_minor_info_tbl)},
-+ {{LOG_MAJOR_BACKLIGHT, "Backlight" }, LG_ALL_MSK, backlight_minor_info_tbl, NUM_ELEMENTS(backlight_minor_info_tbl)},
-+ {{LOG_MAJOR_INTERRUPTS, "Interrupts" }, LG_ALL_MSK, component_minor_info_tbl, NUM_ELEMENTS(component_minor_info_tbl)},
-+ {{LOG_MAJOR_TM, "TM" }, 0, tm_minor_info_tbl, NUM_ELEMENTS(tm_minor_info_tbl)},
-+ {{LOG_MAJOR_DISPLAY_SERVICE, "DS" }, LG_ALL_MSK, ds_minor_info_tbl, NUM_ELEMENTS(ds_minor_info_tbl)},
-+ {{LOG_MAJOR_FEATURE_OVERRIDE, "FeatureOverride" }, LG_ALL_MSK, override_feature_minor_info_tbl, NUM_ELEMENTS(override_feature_minor_info_tbl)},
-+ {{LOG_MAJOR_DETECTION, "Detection" }, LG_ALL_MSK, detection_minor_info_tbl, NUM_ELEMENTS(detection_minor_info_tbl)},
-+};
-+
-+/* ----------- Object init and destruction ----------- */
-+static bool construct(struct dc_context *ctx, struct dal_logger *logger)
-+{
-+ uint32_t i;
-+ /* malloc buffer and init offsets */
-+
-+ logger->log_buffer_size = DAL_LOGGER_BUFFER_MAX_SIZE;
-+ logger->log_buffer = (char *)dc_service_alloc(ctx,
-+ logger->log_buffer_size *
-+ sizeof(char));
-+
-+ if (!logger->log_buffer)
-+ return false;
-+
-+ /* todo: Fill buffer with \0 if not done by dal_alloc */
-+
-+ /* Initialize both offsets to start of buffer (empty) */
-+ logger->buffer_read_offset = 0;
-+ logger->buffer_write_offset = 0;
-+
-+ logger->write_wrap_count = 0;
-+ logger->read_wrap_count = 0;
-+ logger->open_count = 0;
-+
-+ logger->flags.bits.ENABLE_CONSOLE = 1;
-+ logger->flags.bits.ENABLE_BUFFER = 0;
-+
-+ logger->ctx = ctx;
-+
-+ /* malloc and init minor mask array */
-+ logger->log_enable_mask_minors =
-+ (uint32_t *)dc_service_alloc(
-+ ctx,
-+ NUM_ELEMENTS(log_major_mask_info_tbl)
-+ * sizeof(uint32_t));
-+ if (!logger->log_enable_mask_minors)
-+ return false;
-+
-+
-+ /* Set default values for mask */
-+ for (i = 0; i < NUM_ELEMENTS(log_major_mask_info_tbl); i++) {
-+
-+ uint32_t dflt_mask = log_major_mask_info_tbl[i].default_mask;
-+
-+ logger->log_enable_mask_minors[i] = dflt_mask;
-+ }
-+
-+ return true;
-+}
-+
-+static void destruct(struct dal_logger *logger)
-+{
-+ if (logger->log_buffer) {
-+ dc_service_free(logger->ctx, logger->log_buffer);
-+ logger->log_buffer = NULL;
-+ }
-+
-+ if (logger->log_enable_mask_minors) {
-+ dc_service_free(logger->ctx, logger->log_enable_mask_minors);
-+ logger->log_enable_mask_minors = NULL;
-+ }
-+}
-+
-+struct dal_logger *dal_logger_create(struct dc_context *ctx)
-+{
-+ /* malloc struct */
-+ struct dal_logger *logger = dc_service_alloc(ctx, sizeof(struct dal_logger));
-+
-+ if (!logger)
-+ return NULL;
-+ if (!construct(ctx, logger)) {
-+ dc_service_free(ctx, logger);
-+ return NULL;
-+ }
-+
-+ return logger;
-+}
-+
-+uint32_t dal_logger_destroy(struct dal_logger **logger)
-+{
-+ if (logger == NULL || *logger == NULL)
-+ return 1;
-+ destruct(*logger);
-+ dc_service_free((*logger)->ctx, *logger);
-+ *logger = NULL;
-+
-+ return 0;
-+}
-+
-+/* ------------------------------------------------------------------------ */
-+
-+static void lock(struct dal_logger *logger)
-+{
-+ /* Todo: lock mutex? */
-+}
-+
-+static void unlock(struct dal_logger *logger)
-+{
-+ /* Todo: unlock mutex */
-+}
-+
-+bool dal_logger_should_log(
-+ struct dal_logger *logger,
-+ enum log_major major,
-+ enum log_minor minor)
-+{
-+ if (major < LOG_MAJOR_COUNT) {
-+
-+ uint32_t minor_mask = logger->log_enable_mask_minors[major];
-+
-+ if ((minor_mask & (1 << minor)) != 0)
-+ return true;
-+ }
-+
-+ return false;
-+}
-+
-+static void log_to_debug_console(struct log_entry *entry)
-+{
-+ struct dal_logger *logger = entry->logger;
-+
-+ if (logger->flags.bits.ENABLE_CONSOLE == 0)
-+ return;
-+
-+ switch (entry->major) {
-+ case LOG_MAJOR_ERROR:
-+ dal_error("%s", entry->buf);
-+ break;
-+ default:
-+ dal_output_to_console("%s", entry->buf);
-+ break;
-+ }
-+}
-+
-+/* Print everything unread existing in log_buffer to debug console*/
-+static void flush_to_debug_console(struct dal_logger *logger)
-+{
-+ int i = logger->buffer_read_offset;
-+ char *string_start = &logger->log_buffer[i];
-+
-+ dal_output_to_console(
-+ "---------------- FLUSHING LOG BUFFER ----------------\n");
-+ while (i < logger->buffer_write_offset) {
-+
-+ if (logger->log_buffer[i] == '\0') {
-+ dal_output_to_console("%s", string_start);
-+ string_start = (char *)logger->log_buffer + i + 1;
-+ }
-+ i++;
-+ }
-+ dal_output_to_console(
-+ "-------------- END FLUSHING LOG BUFFER --------------\n\n");
-+}
-+
-+static void log_to_internal_buffer(struct log_entry *entry)
-+{
-+
-+ uint32_t size = entry->buf_offset;
-+ struct dal_logger *logger = entry->logger;
-+
-+ if (logger->flags.bits.ENABLE_BUFFER == 0)
-+ return;
-+
-+ if (logger->log_buffer == NULL)
-+ return;
-+
-+ if (size > 0 && size < logger->log_buffer_size) {
-+
-+ int total_free_space = 0;
-+ int space_before_wrap = 0;
-+
-+ if (logger->buffer_write_offset > logger->buffer_read_offset) {
-+ total_free_space = logger->log_buffer_size -
-+ logger->buffer_write_offset +
-+ logger->buffer_read_offset;
-+ space_before_wrap = logger->log_buffer_size -
-+ logger->buffer_write_offset;
-+ } else if (logger->buffer_write_offset <
-+ logger->buffer_read_offset) {
-+ total_free_space = logger->log_buffer_size -
-+ logger->buffer_read_offset +
-+ logger->buffer_write_offset;
-+ space_before_wrap = total_free_space;
-+ } else if (logger->write_wrap_count !=
-+ logger->read_wrap_count) {
-+ /* Buffer is completely full already */
-+ total_free_space = 0;
-+ space_before_wrap = 0;
-+ } else {
-+ /* Buffer is empty, start writing at beginning */
-+ total_free_space = logger->log_buffer_size;
-+ space_before_wrap = logger->log_buffer_size;
-+ logger->buffer_write_offset = 0;
-+ logger->buffer_read_offset = 0;
-+ }
-+
-+
-+
-+
-+ if (space_before_wrap > size) {
-+ /* No wrap around, copy 'size' bytes
-+ * from 'entry->buf' to 'log_buffer'
-+ */
-+ dc_service_memmove(logger->log_buffer +
-+ logger->buffer_write_offset,
-+ entry->buf, size);
-+ logger->buffer_write_offset += size;
-+
-+ } else if (total_free_space > size) {
-+ /* We have enough room without flushing,
-+ * but need to wrap around */
-+
-+ int space_after_wrap = total_free_space -
-+ space_before_wrap;
-+
-+ dc_service_memmove(logger->log_buffer +
-+ logger->buffer_write_offset,
-+ entry->buf, space_before_wrap);
-+ dc_service_memmove(logger->log_buffer, entry->buf +
-+ space_before_wrap, space_after_wrap);
-+
-+ logger->buffer_write_offset = space_after_wrap;
-+ logger->write_wrap_count++;
-+
-+ } else {
-+ /* Not enough room remaining, we should flush
-+ * existing logs */
-+
-+ /* Flush existing unread logs to console */
-+ flush_to_debug_console(logger);
-+
-+ /* Start writing to beginning of buffer */
-+ dc_service_memmove(logger->log_buffer, entry->buf, size);
-+ logger->buffer_write_offset = size;
-+ logger->buffer_read_offset = 0;
-+ }
-+
-+ }
-+
-+ unlock(logger);
-+}
-+
-+
-+static void log_timestamp(struct log_entry *entry)
-+{
-+ dal_logger_append(entry, "00:00:00 ");
-+}
-+
-+static void log_major_minor(struct log_entry *entry)
-+{
-+ uint32_t i;
-+ enum log_major major = entry->major;
-+ enum log_minor minor = entry->minor;
-+
-+ for (i = 0; i < NUM_ELEMENTS(log_major_mask_info_tbl); i++) {
-+
-+ const struct log_major_mask_info *maj_mask_info =
-+ &log_major_mask_info_tbl[i];
-+
-+ if (maj_mask_info->major_info.major == major) {
-+
-+ dal_logger_append(entry, "[%s_",
-+ maj_mask_info->major_info.major_name);
-+
-+ if (maj_mask_info->minor_tbl != NULL) {
-+ uint32_t j;
-+
-+ for (j = 0; j < maj_mask_info->tbl_element_cnt; j++) {
-+
-+ const struct log_minor_info *min_info = &maj_mask_info->minor_tbl[j];
-+
-+ if (min_info->minor == minor)
-+ dal_logger_append(entry, "%s]\t", min_info->minor_name);
-+ }
-+ }
-+
-+ break;
-+ }
-+ }
-+}
-+
-+static void log_heading(struct log_entry *entry,
-+ enum log_major major,
-+ enum log_minor minor)
-+{
-+ log_timestamp(entry);
-+ log_major_minor(entry);
-+}
-+
-+
-+static void append_entry(
-+ struct log_entry *entry,
-+ char *buffer,
-+ uint32_t buf_size)
-+{
-+ if (!entry->buf ||
-+ entry->buf_offset + buf_size > entry->max_buf_bytes
-+ ) {
-+ BREAK_TO_DEBUGGER();
-+ return;
-+ }
-+
-+ /* Todo: check if off by 1 byte due to \0 anywhere */
-+ dc_service_memmove(entry->buf + entry->buf_offset, buffer, buf_size);
-+ entry->buf_offset += buf_size;
-+}
-+
-+/* ------------------------------------------------------------------------ */
-+
-+/* Warning: Be careful that 'msg' is null terminated and the total size is
-+ * less than DAL_LOGGER_BUFFER_MAX_LOG_LINE_SIZE (256) including '\0'
-+ */
-+void dal_logger_write(
-+ struct dal_logger *logger,
-+ enum log_major major,
-+ enum log_minor minor,
-+ const char *msg,
-+ ...)
-+{
-+
-+ if (logger && dal_logger_should_log(logger, major, minor)) {
-+
-+ uint32_t size;
-+ va_list args;
-+ char buffer[DAL_LOGGER_BUFFER_MAX_LOG_LINE_SIZE];
-+ struct log_entry entry;
-+
-+ va_start(args, msg);
-+ dal_logger_open(logger, &entry, major, minor);
-+
-+
-+ size = dal_log_to_buffer(
-+ buffer, DAL_LOGGER_BUFFER_MAX_LOG_LINE_SIZE, msg, args);
-+
-+ if (size > 0 && size <
-+ DAL_LOGGER_BUFFER_MAX_LOG_LINE_SIZE - 1) {
-+
-+ if (buffer[size] == '\0')
-+ size++; /* Add one for null terminator */
-+
-+ /* Concatenate onto end of entry buffer */
-+ append_entry(&entry, buffer, size);
-+ } else {
-+ append_entry(&entry, "LOG_ERROR\n", 12);
-+ }
-+
-+ dal_logger_close(&entry);
-+ va_end(args);
-+
-+ }
-+}
-+
-+
-+/* Same as dal_logger_write, except without open() and close(), which must
-+ * be done separately.
-+ */
-+void dal_logger_append(
-+ struct log_entry *entry,
-+ const char *msg,
-+ ...)
-+{
-+ struct dal_logger *logger;
-+
-+ if (!entry) {
-+ BREAK_TO_DEBUGGER();
-+ return;
-+ }
-+
-+ logger = entry->logger;
-+
-+ if (logger && logger->open_count > 0 &&
-+ dal_logger_should_log(logger, entry->major, entry->minor)) {
-+
-+ uint32_t size;
-+ va_list args;
-+ char buffer[DAL_LOGGER_BUFFER_MAX_LOG_LINE_SIZE];
-+
-+ va_start(args, msg);
-+
-+ size = dal_log_to_buffer(
-+ buffer, DAL_LOGGER_BUFFER_MAX_LOG_LINE_SIZE, msg, args);
-+ append_entry(entry, buffer, size);
-+
-+ va_end(args);
-+ }
-+}
-+
-+
-+uint32_t dal_logger_read(
-+ struct dal_logger *logger, /* <[in] */
-+ uint32_t output_buffer_size, /* <[in] */
-+ char *output_buffer, /* >[out] */
-+ uint32_t *bytes_read, /* >[out] */
-+ bool single_line)
-+{
-+ uint32_t bytes_remaining = 0;
-+ uint32_t bytes_read_count = 0;
-+ bool keep_reading = true;
-+
-+ if (!logger || output_buffer == NULL || output_buffer_size == 0) {
-+ BREAK_TO_DEBUGGER();
-+ *bytes_read = 0;
-+ return 0;
-+ }
-+
-+ lock(logger);
-+
-+ /* Read until null terminator (if single_line==true,
-+ * max buffer size, or until we've read everything new
-+ */
-+
-+ do {
-+ char cur;
-+
-+ /* Stop when we've read everything */
-+ if (logger->buffer_read_offset ==
-+ logger->buffer_write_offset) {
-+
-+ break;
-+ }
-+
-+ cur = logger->log_buffer[logger->buffer_read_offset];
-+ logger->buffer_read_offset++;
-+
-+ /* Wrap read pointer if at end */
-+ if (logger->buffer_read_offset == logger->log_buffer_size) {
-+
-+ logger->buffer_read_offset = 0;
-+ logger->read_wrap_count++;
-+ }
-+
-+ /* Don't send null terminators to buffer */
-+ if (cur != '\0') {
-+ output_buffer[bytes_read_count] = cur;
-+ bytes_read_count++;
-+ } else if (single_line) {
-+ keep_reading = false;
-+ }
-+
-+ } while (bytes_read_count <= output_buffer_size && keep_reading);
-+
-+ /* We assume that reading can never be ahead of writing */
-+ if (logger->write_wrap_count > logger->read_wrap_count) {
-+ bytes_remaining = logger->log_buffer_size -
-+ logger->buffer_read_offset +
-+ logger->buffer_write_offset;
-+ } else {
-+ bytes_remaining = logger->buffer_write_offset -
-+ logger->buffer_read_offset;
-+ }
-+
-+ /* reset write/read wrap count to 0 if we've read everything */
-+ if (bytes_remaining == 0) {
-+
-+ logger->write_wrap_count = 0;
-+ logger->read_wrap_count = 0;
-+ }
-+
-+ *bytes_read = bytes_read_count;
-+ unlock(logger);
-+
-+ return bytes_remaining;
-+}
-+
-+void dal_logger_open(
-+ struct dal_logger *logger,
-+ struct log_entry *entry, /* out */
-+ enum log_major major,
-+ enum log_minor minor)
-+{
-+ if (!entry) {
-+ BREAK_TO_DEBUGGER();
-+ return;
-+ }
-+
-+ entry->major = LOG_MAJOR_COUNT;
-+ entry->minor = 0;
-+ entry->logger = logger;
-+
-+ entry->buf = dc_service_alloc(
-+ logger->ctx,
-+ DAL_LOGGER_BUFFER_MAX_LOG_LINE_SIZE * sizeof(char));
-+
-+ entry->buf_offset = 0;
-+ entry->max_buf_bytes =
-+ DAL_LOGGER_BUFFER_MAX_LOG_LINE_SIZE * sizeof(char);
-+
-+ logger->open_count++;
-+ entry->major = major;
-+ entry->minor = minor;
-+
-+ log_heading(entry, major, minor);
-+}
-+
-+void dal_logger_close(struct log_entry *entry)
-+{
-+ struct dal_logger *logger = entry->logger;
-+
-+
-+ if (logger && logger->open_count > 0) {
-+ logger->open_count--;
-+ } else {
-+ BREAK_TO_DEBUGGER();
-+ goto cleanup;
-+ }
-+
-+ /* --Flush log_entry buffer-- */
-+ /* print to kernel console */
-+ log_to_debug_console(entry);
-+ /* log internally for dsat */
-+ log_to_internal_buffer(entry);
-+
-+ /* TODO: Write end heading */
-+
-+cleanup:
-+ if (entry->buf) {
-+ dc_service_free(entry->logger->ctx, entry->buf);
-+ entry->buf = NULL;
-+ entry->buf_offset = 0;
-+ entry->max_buf_bytes = 0;
-+ }
-+}
-+
-+uint32_t dal_logger_get_mask(
-+ struct dal_logger *logger,
-+ enum log_major lvl_major, enum log_minor lvl_minor)
-+{
-+ uint32_t log_mask = 0;
-+
-+ if (logger && lvl_major < LOG_MAJOR_COUNT)
-+ log_mask = logger->log_enable_mask_minors[lvl_major];
-+
-+ log_mask &= 1 << lvl_minor;
-+ return log_mask;
-+}
-+
-+uint32_t dal_logger_set_mask(
-+ struct dal_logger *logger,
-+ enum log_major lvl_major, enum log_minor lvl_minor)
-+{
-+
-+ if (logger && lvl_major < LOG_MAJOR_COUNT) {
-+ if (lvl_minor == LOG_MINOR_MASK_ALL) {
-+ logger->log_enable_mask_minors[lvl_major] = 0xFFFFFFFF;
-+ } else {
-+ logger->log_enable_mask_minors[lvl_major] |=
-+ (1 << lvl_minor);
-+ }
-+ return 0;
-+ }
-+ return 1;
-+}
-+
-+uint32_t dal_logger_get_masks(
-+ struct dal_logger *logger,
-+ enum log_major lvl_major)
-+{
-+ uint32_t log_mask = 0;
-+
-+ if (logger && lvl_major < LOG_MAJOR_COUNT)
-+ log_mask = logger->log_enable_mask_minors[lvl_major];
-+
-+ return log_mask;
-+}
-+
-+void dal_logger_set_masks(
-+ struct dal_logger *logger,
-+ enum log_major lvl_major, uint32_t log_mask)
-+{
-+ if (logger && lvl_major < LOG_MAJOR_COUNT)
-+ logger->log_enable_mask_minors[lvl_major] = log_mask;
-+}
-+
-+uint32_t dal_logger_unset_mask(
-+ struct dal_logger *logger,
-+ enum log_major lvl_major, enum log_minor lvl_minor)
-+{
-+
-+ if (lvl_major < LOG_MAJOR_COUNT) {
-+ if (lvl_minor == LOG_MINOR_MASK_ALL) {
-+ logger->log_enable_mask_minors[lvl_major] = 0;
-+ } else {
-+ logger->log_enable_mask_minors[lvl_major] &=
-+ ~(1 << lvl_minor);
-+ }
-+ return 0;
-+ }
-+ return 1;
-+}
-+
-+uint32_t dal_logger_get_flags(
-+ struct dal_logger *logger)
-+{
-+
-+ return logger->flags.value;
-+}
-+
-+void dal_logger_set_flags(
-+ struct dal_logger *logger,
-+ union logger_flags flags)
-+{
-+
-+ logger->flags = flags;
-+}
-+
-+
-+uint32_t dal_logger_get_buffer_size(struct dal_logger *logger)
-+{
-+ return DAL_LOGGER_BUFFER_MAX_SIZE;
-+}
-+
-+uint32_t dal_logger_set_buffer_size(
-+ struct dal_logger *logger,
-+ uint32_t new_size)
-+{
-+ /* ToDo: implement dynamic size */
-+
-+ /* return new size */
-+ return DAL_LOGGER_BUFFER_MAX_SIZE;
-+}
-+
-+
-+const struct log_major_info *dal_logger_enum_log_major_info(
-+ struct dal_logger *logger,
-+ unsigned int enum_index)
-+{
-+ const struct log_major_info *major_info;
-+
-+ if (enum_index >= NUM_ELEMENTS(log_major_mask_info_tbl))
-+ return NULL;
-+
-+ major_info = &log_major_mask_info_tbl[enum_index].major_info;
-+ return major_info;
-+}
-+
-+const struct log_minor_info *dal_logger_enum_log_minor_info(
-+ struct dal_logger *logger,
-+ enum log_major major,
-+ unsigned int enum_index)
-+{
-+ const struct log_minor_info *minor_info = NULL;
-+ uint32_t i;
-+
-+ for (i = 0; i < NUM_ELEMENTS(log_major_mask_info_tbl); i++) {
-+
-+ const struct log_major_mask_info *maj_mask_info =
-+ &log_major_mask_info_tbl[i];
-+
-+ if (maj_mask_info->major_info.major == major) {
-+
-+ if (maj_mask_info->minor_tbl != NULL) {
-+ uint32_t j;
-+
-+ for (j = 0; j < maj_mask_info->tbl_element_cnt; j++) {
-+
-+ minor_info = &maj_mask_info->minor_tbl[j];
-+
-+ if (minor_info->minor == enum_index)
-+ return minor_info;
-+ }
-+ }
-+
-+ break;
-+ }
-+ }
-+ return NULL;
-+
-+}
-+
-diff --git a/drivers/gpu/drm/amd/dal/dc/basics/logger.h b/drivers/gpu/drm/amd/dal/dc/basics/logger.h
-new file mode 100644
-index 0000000..fba5ec3
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/basics/logger.h
-@@ -0,0 +1,64 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_LOGGER_H__
-+#define __DAL_LOGGER_H__
-+
-+/* Structure for keeping track of offsets, buffer, etc */
-+
-+#define DAL_LOGGER_BUFFER_MAX_SIZE 2048
-+#define DAL_LOGGER_BUFFER_MAX_LOG_LINE_SIZE 256
-+
-+
-+#include "include/logger_types.h"
-+
-+struct dal_logger {
-+
-+ /* How far into the circular buffer has been read by dsat
-+ * Read offset should never cross write offset. Write \0's to
-+ * read data just to be sure?
-+ */
-+ uint32_t buffer_read_offset;
-+
-+ /* How far into the circular buffer we have written
-+ * Write offset should never cross read offset
-+ */
-+ uint32_t buffer_write_offset;
-+
-+ uint32_t write_wrap_count;
-+ uint32_t read_wrap_count;
-+
-+ uint32_t open_count;
-+
-+ char *log_buffer; /* Pointer to malloc'ed buffer */
-+ uint32_t log_buffer_size; /* Size of circular buffer */
-+
-+ uint32_t *log_enable_mask_minors; /*array of masks for major elements*/
-+
-+ union logger_flags flags;
-+ struct dc_context *ctx;
-+};
-+
-+#endif /* __DAL_LOGGER_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/basics/register_logger.c b/drivers/gpu/drm/amd/dal/dc/basics/register_logger.c
-new file mode 100644
-index 0000000..a3086a0
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/basics/register_logger.c
-@@ -0,0 +1,197 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+#include "include/dal_types.h"
-+#include "include/logger_interface.h"
-+#include "logger.h"
-+
-+/******************************************************************************
-+ * Register Logger.
-+ * A facility to create register R/W logs.
-+ * Currently used for DAL Test.
-+ *****************************************************************************/
-+
-+/******************************************************************************
-+ * Private structures
-+ *****************************************************************************/
-+struct dal_reg_dump_stack_location {
-+ const char *current_caller_func;
-+ long current_pid;
-+ long current_tgid;
-+ uint32_t rw_count;/* register access counter for current function. */
-+};
-+
-+/* This the maximum number of nested calls to the 'reg_dump' facility. */
-+#define DAL_REG_DUMP_STACK_MAX_SIZE 32
-+
-+struct dal_reg_dump_stack {
-+ int32_t stack_pointer;
-+ struct dal_reg_dump_stack_location
-+ stack_locations[DAL_REG_DUMP_STACK_MAX_SIZE];
-+ uint32_t total_rw_count; /* Total count for *all* functions. */
-+};
-+
-+static struct dal_reg_dump_stack reg_dump_stack = {0};
-+
-+/******************************************************************************
-+ * Private functions
-+ *****************************************************************************/
-+
-+/* Check if current process is the one which requested register dump.
-+ * The reason for the check:
-+ * mmCRTC_STATUS_FRAME_COUNT is accessed by dal_controller_get_vblank_counter().
-+ * Which runs all the time when at least one display is connected.
-+ * (Triggered by drm_mode_page_flip_ioctl()). */
-+static bool is_reg_dump_process(void)
-+{
-+ uint32_t i;
-+
-+ /* walk the list of our processes */
-+ for (i = 0; i < reg_dump_stack.stack_pointer; i++) {
-+ struct dal_reg_dump_stack_location *stack_location
-+ = &reg_dump_stack.stack_locations[i];
-+
-+ if (stack_location->current_pid == dal_get_pid()
-+ && stack_location->current_tgid == dal_get_tgid())
-+ return true;
-+ }
-+
-+ return false;
-+}
-+
-+static bool dal_reg_dump_stack_is_empty(void)
-+{
-+ if (reg_dump_stack.stack_pointer <= 0)
-+ return true;
-+ else
-+ return false;
-+}
-+
-+static struct dal_reg_dump_stack_location *dal_reg_dump_stack_push(void)
-+{
-+ struct dal_reg_dump_stack_location *current_location = NULL;
-+
-+ if (reg_dump_stack.stack_pointer >= DAL_REG_DUMP_STACK_MAX_SIZE) {
-+ /* stack is full */
-+ dal_output_to_console("[REG_DUMP]: %s: stack is full!\n",
-+ __func__);
-+ } else {
-+ current_location =
-+ &reg_dump_stack.stack_locations[reg_dump_stack.stack_pointer];
-+ ++reg_dump_stack.stack_pointer;
-+ }
-+
-+ return current_location;
-+}
-+
-+static struct dal_reg_dump_stack_location *dal_reg_dump_stack_pop(void)
-+{
-+ struct dal_reg_dump_stack_location *current_location = NULL;
-+
-+ if (dal_reg_dump_stack_is_empty()) {
-+ /* stack is empty */
-+ dal_output_to_console("[REG_DUMP]: %s: stack is empty!\n",
-+ __func__);
-+ } else {
-+ --reg_dump_stack.stack_pointer;
-+ current_location =
-+ &reg_dump_stack.stack_locations[reg_dump_stack.stack_pointer];
-+ }
-+
-+ return current_location;
-+}
-+
-+/******************************************************************************
-+ * Public functions
-+ *****************************************************************************/
-+
-+void dal_reg_logger_push(const char *caller_func)
-+{
-+ struct dal_reg_dump_stack_location *free_stack_location;
-+
-+ free_stack_location = dal_reg_dump_stack_push();
-+
-+ if (NULL == free_stack_location)
-+ return;
-+
-+ dc_service_memset(free_stack_location, 0, sizeof(*free_stack_location));
-+
-+ free_stack_location->current_caller_func = caller_func;
-+ free_stack_location->current_pid = dal_get_pid();
-+ free_stack_location->current_tgid = dal_get_tgid();
-+
-+ dal_output_to_console("[REG_DUMP]:%s - start (pid:%ld, tgid:%ld)\n",
-+ caller_func,
-+ free_stack_location->current_pid,
-+ free_stack_location->current_tgid);
-+}
-+
-+void dal_reg_logger_pop(void)
-+{
-+ struct dal_reg_dump_stack_location *top_stack_location;
-+
-+ top_stack_location = dal_reg_dump_stack_pop();
-+
-+ if (NULL == top_stack_location) {
-+ dal_output_to_console("[REG_DUMP]:%s - Stack is Empty!\n",
-+ __func__);
-+ return;
-+ }
-+
-+ dal_output_to_console(
-+ "[REG_DUMP]:%s - end."\
-+ " Reg R/W Count: Total=%d Function=%d. (pid:%ld, tgid:%ld)\n",
-+ top_stack_location->current_caller_func,
-+ reg_dump_stack.total_rw_count,
-+ top_stack_location->rw_count,
-+ dal_get_pid(),
-+ dal_get_tgid());
-+
-+ dc_service_memset(top_stack_location, 0, sizeof(*top_stack_location));
-+}
-+
-+void dal_reg_logger_rw_count_increment(void)
-+{
-+ ++reg_dump_stack.total_rw_count;
-+
-+ ++reg_dump_stack.stack_locations
-+ [reg_dump_stack.stack_pointer - 1].rw_count;
-+}
-+
-+bool dal_reg_logger_should_dump_register(void)
-+{
-+ if (true == dal_reg_dump_stack_is_empty())
-+ return false;
-+
-+ if (false == is_reg_dump_process())
-+ return false;
-+
-+ return true;
-+}
-+
-+/******************************************************************************
-+ * End of File.
-+ *****************************************************************************/
-diff --git a/drivers/gpu/drm/amd/dal/dc/basics/signal_types.c b/drivers/gpu/drm/amd/dal/dc/basics/signal_types.c
-new file mode 100644
-index 0000000..f589091
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/basics/signal_types.c
-@@ -0,0 +1,116 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dc_services.h"
-+#include "include/signal_types.h"
-+
-+bool dc_is_hdmi_signal(enum signal_type signal)
-+{
-+ return (signal == SIGNAL_TYPE_HDMI_TYPE_A);
-+}
-+
-+bool dc_is_dp_sst_signal(enum signal_type signal)
-+{
-+ return (signal == SIGNAL_TYPE_DISPLAY_PORT ||
-+ signal == SIGNAL_TYPE_EDP);
-+}
-+
-+bool dc_is_dp_signal(enum signal_type signal)
-+{
-+ return (signal == SIGNAL_TYPE_DISPLAY_PORT ||
-+ signal == SIGNAL_TYPE_EDP ||
-+ signal == SIGNAL_TYPE_DISPLAY_PORT_MST);
-+}
-+
-+bool dc_is_dp_external_signal(enum signal_type signal)
-+{
-+ return (signal == SIGNAL_TYPE_DISPLAY_PORT ||
-+ signal == SIGNAL_TYPE_DISPLAY_PORT_MST);
-+}
-+
-+bool dc_is_analog_signal(enum signal_type signal)
-+{
-+ switch (signal) {
-+ case SIGNAL_TYPE_RGB:
-+ return true;
-+ break;
-+ default:
-+ return false;
-+ }
-+}
-+
-+bool dc_is_embedded_signal(enum signal_type signal)
-+{
-+ return (signal == SIGNAL_TYPE_EDP || signal == SIGNAL_TYPE_LVDS);
-+}
-+
-+bool dc_is_dvi_signal(enum signal_type signal)
-+{
-+ switch (signal) {
-+ case SIGNAL_TYPE_DVI_SINGLE_LINK:
-+ case SIGNAL_TYPE_DVI_DUAL_LINK:
-+ return true;
-+ break;
-+ default:
-+ return false;
-+ }
-+}
-+
-+bool dc_is_dvi_single_link_signal(enum signal_type signal)
-+{
-+ return (signal == SIGNAL_TYPE_DVI_SINGLE_LINK);
-+}
-+
-+bool dc_is_dual_link_signal(enum signal_type signal)
-+{
-+ return (signal == SIGNAL_TYPE_DVI_DUAL_LINK);
-+}
-+
-+bool dc_is_audio_capable_signal(enum signal_type signal)
-+{
-+ return (signal == SIGNAL_TYPE_DISPLAY_PORT ||
-+ signal == SIGNAL_TYPE_DISPLAY_PORT_MST ||
-+ dc_is_hdmi_signal(signal) ||
-+ signal == SIGNAL_TYPE_WIRELESS);
-+}
-+
-+/*
-+ * @brief
-+ * Returns whether the signal is compatible
-+ * with other digital encoder signal types.
-+ * This is true for DVI, LVDS, and HDMI signal types.
-+ */
-+bool dc_is_digital_encoder_compatible_signal(enum signal_type signal)
-+{
-+ switch (signal) {
-+ case SIGNAL_TYPE_DVI_SINGLE_LINK:
-+ case SIGNAL_TYPE_DVI_DUAL_LINK:
-+ case SIGNAL_TYPE_HDMI_TYPE_A:
-+ case SIGNAL_TYPE_LVDS:
-+ return true;
-+ default:
-+ return false;
-+ }
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/basics/vector.c b/drivers/gpu/drm/amd/dal/dc/basics/vector.c
-new file mode 100644
-index 0000000..2f932c0
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/basics/vector.c
-@@ -0,0 +1,309 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+#include "include/vector.h"
-+
-+bool dal_vector_construct(
-+ struct vector *vector,
-+ struct dc_context *ctx,
-+ uint32_t capacity,
-+ uint32_t struct_size)
-+{
-+ vector->container = NULL;
-+
-+ if (!struct_size || !capacity) {
-+ /* Container must be non-zero size*/
-+ BREAK_TO_DEBUGGER();
-+ return false;
-+ }
-+
-+ vector->container = dc_service_alloc(ctx, struct_size * capacity);
-+ if (vector->container == NULL)
-+ return false;
-+ vector->capacity = capacity;
-+ vector->struct_size = struct_size;
-+ vector->count = 0;
-+ vector->ctx = ctx;
-+ return true;
-+}
-+
-+bool dal_vector_presized_costruct(
-+ struct vector *vector,
-+ struct dc_context *ctx,
-+ uint32_t count,
-+ void *initial_value,
-+ uint32_t struct_size)
-+{
-+ uint32_t i;
-+
-+ vector->container = NULL;
-+
-+ if (!struct_size || !count) {
-+ /* Container must be non-zero size*/
-+ BREAK_TO_DEBUGGER();
-+ return false;
-+ }
-+
-+ vector->container = dc_service_alloc(ctx, struct_size * count);
-+
-+ if (vector->container == NULL)
-+ return false;
-+
-+ /* If caller didn't supply initial value then the default
-+ * of all zeros is expected, which is exactly what dal_alloc()
-+ * initialises the memory to. */
-+ if (NULL != initial_value) {
-+ for (i = 0; i < count; ++i)
-+ dc_service_memmove(
-+ vector->container + i * struct_size,
-+ initial_value,
-+ struct_size);
-+ }
-+
-+ vector->capacity = count;
-+ vector->struct_size = struct_size;
-+ vector->count = count;
-+ return true;
-+}
-+
-+struct vector *dal_vector_presized_create(
-+ struct dc_context *ctx,
-+ uint32_t size,
-+ void *initial_value,
-+ uint32_t struct_size)
-+{
-+ struct vector *vector = dc_service_alloc(ctx, sizeof(struct vector));
-+
-+ if (vector == NULL)
-+ return NULL;
-+
-+ if (dal_vector_presized_costruct(
-+ vector, ctx, size, initial_value, struct_size))
-+ return vector;
-+
-+ BREAK_TO_DEBUGGER();
-+ dc_service_free(ctx, vector);
-+ return NULL;
-+}
-+
-+struct vector *dal_vector_create(
-+ struct dc_context *ctx,
-+ uint32_t capacity,
-+ uint32_t struct_size)
-+{
-+ struct vector *vector = dc_service_alloc(ctx, sizeof(struct vector));
-+
-+ if (vector == NULL)
-+ return NULL;
-+
-+ if (dal_vector_construct(vector, ctx, capacity, struct_size))
-+ return vector;
-+
-+
-+ BREAK_TO_DEBUGGER();
-+ dc_service_free(ctx, vector);
-+ return NULL;
-+}
-+
-+void dal_vector_destruct(
-+ struct vector *vector)
-+{
-+ if (vector->container != NULL)
-+ dc_service_free(vector->ctx, vector->container);
-+ vector->count = 0;
-+ vector->capacity = 0;
-+}
-+
-+void dal_vector_destroy(
-+ struct vector **vector)
-+{
-+ if (vector == NULL || *vector == NULL)
-+ return;
-+ dal_vector_destruct(*vector);
-+ dc_service_free((*vector)->ctx, *vector);
-+ *vector = NULL;
-+}
-+
-+uint32_t dal_vector_get_count(
-+ const struct vector *vector)
-+{
-+ return vector->count;
-+}
-+
-+void *dal_vector_at_index(
-+ const struct vector *vector,
-+ uint32_t index)
-+{
-+ if (vector->container == NULL || index >= vector->count)
-+ return NULL;
-+ return vector->container + (index * vector->struct_size);
-+}
-+
-+bool dal_vector_remove_at_index(
-+ struct vector *vector,
-+ uint32_t index)
-+{
-+ if (index >= vector->count)
-+ return false;
-+
-+ if (index != vector->count - 1)
-+ dc_service_memmove(
-+ vector->container + (index * vector->struct_size),
-+ vector->container + ((index + 1) * vector->struct_size),
-+ (vector->count - index - 1) * vector->struct_size);
-+ vector->count -= 1;
-+
-+ return true;
-+}
-+
-+void dal_vector_set_at_index(
-+ const struct vector *vector,
-+ const void *what,
-+ uint32_t index)
-+{
-+ void *where = dal_vector_at_index(vector, index);
-+
-+ if (!where) {
-+ BREAK_TO_DEBUGGER();
-+ return;
-+ }
-+ dc_service_memmove(
-+ where,
-+ what,
-+ vector->struct_size);
-+}
-+
-+static inline uint32_t calc_increased_capacity(
-+ uint32_t old_capacity)
-+{
-+ return old_capacity * 2;
-+}
-+
-+bool dal_vector_insert_at(
-+ struct vector *vector,
-+ const void *what,
-+ uint32_t position)
-+{
-+ uint8_t *insert_address;
-+
-+ if (vector->count == vector->capacity) {
-+ if (!dal_vector_reserve(
-+ vector,
-+ calc_increased_capacity(vector->capacity)))
-+ return false;
-+ }
-+
-+ insert_address = vector->container + (vector->struct_size * position);
-+
-+ if (vector->count && position < vector->count)
-+ dc_service_memmove(
-+ insert_address + vector->struct_size,
-+ insert_address,
-+ vector->struct_size * (vector->count - position));
-+
-+ dc_service_memmove(
-+ insert_address,
-+ what,
-+ vector->struct_size);
-+
-+ vector->count++;
-+
-+ return true;
-+}
-+
-+bool dal_vector_append(
-+ struct vector *vector,
-+ const void *item)
-+{
-+ return dal_vector_insert_at(vector, item, vector->count);
-+}
-+
-+struct vector *dal_vector_clone(
-+ const struct vector *vector)
-+{
-+ struct vector *vec_cloned;
-+ uint32_t count;
-+
-+ /* create new vector */
-+ count = dal_vector_get_count(vector);
-+
-+ if (count == 0)
-+ /* when count is 0 we still want to create clone of the vector
-+ */
-+ vec_cloned = dal_vector_create(
-+ vector->ctx,
-+ vector->capacity,
-+ vector->struct_size);
-+ else
-+ /* Call "presized create" version, independently of how the
-+ * original vector was created.
-+ * The owner of original vector must know how to treat the new
-+ * vector - as "presized" or as "regular".
-+ * But from vector point of view it doesn't matter. */
-+ vec_cloned = dal_vector_presized_create(vector->ctx, count,
-+ NULL,/* no initial value */
-+ vector->struct_size);
-+
-+ if (NULL == vec_cloned) {
-+ BREAK_TO_DEBUGGER();
-+ return NULL;
-+ }
-+
-+ /* copy vector's data */
-+ dc_service_memmove(vec_cloned->container, vector->container,
-+ vec_cloned->struct_size * vec_cloned->capacity);
-+
-+ return vec_cloned;
-+}
-+
-+uint32_t dal_vector_capacity(const struct vector *vector)
-+{
-+ return vector->capacity;
-+}
-+
-+bool dal_vector_reserve(struct vector *vector, uint32_t capacity)
-+{
-+ void *new_container;
-+
-+ if (capacity <= vector->capacity)
-+ return true;
-+
-+ new_container = dc_service_realloc(vector->ctx, vector->container,
-+ capacity * vector->struct_size);
-+
-+ if (new_container) {
-+ vector->container = new_container;
-+ vector->capacity = capacity;
-+ return true;
-+ }
-+
-+ return false;
-+}
-+
-+void dal_vector_clear(struct vector *vector)
-+{
-+ vector->count = 0;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/Makefile b/drivers/gpu/drm/amd/dal/dc/bios/Makefile
-new file mode 100644
-index 0000000..75bb892
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/Makefile
-@@ -0,0 +1,27 @@
-+#
-+# Makefile for the 'bios' sub-component of DAL.
-+# It provides the parsing and executing controls for atom bios image.
-+
-+BIOS = bios_parser.o bios_parser_helper.o command_table.o command_table_helper.o
-+
-+AMD_DAL_BIOS = $(addprefix $(AMDDALPATH)/dc/bios/,$(BIOS))
-+
-+AMD_DAL_FILES += $(AMD_DAL_BIOS)
-+
-+ifndef CONFIG_DRM_AMD_DAL_VBIOS_PRESENT
-+AMD_DAL_FILES := $(filter-out $(AMDDALPATH)/dc/bios/bios_parser_helper.o,$(AMD_DAL_FILES))
-+endif
-+$(warning AMD_DAL_FILES=$(AMD_DAL_FILES))
-+
-+
-+###############################################################################
-+# DCE 11x
-+###############################################################################
-+ifdef CONFIG_DRM_AMD_DAL_DCE11_0
-+
-+ifdef CONFIG_DRM_AMD_DAL_VBIOS_PRESENT
-+AMD_DAL_FILES += $(AMDDALPATH)/dc/bios/dce110/bios_parser_helper_dce110.o
-+endif
-+
-+AMD_DAL_FILES += $(AMDDALPATH)/dc/bios/dce110/command_table_helper_dce110.o
-+endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c
-new file mode 100644
-index 0000000..7a2b247
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c
-@@ -0,0 +1,4758 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+
-+#include "atom.h"
-+
-+#include "include/adapter_service_interface.h"
-+#include "include/grph_object_ctrl_defs.h"
-+#include "include/bios_parser_interface.h"
-+#include "include/i2caux_interface.h"
-+#include "include/logger_interface.h"
-+
-+#include "command_table.h"
-+#if defined(CONFIG_DRM_AMD_DAL_VBIOS_PRESENT)
-+#include "bios_parser_helper.h"
-+#endif
-+#include "command_table_helper.h"
-+#include "bios_parser.h"
-+
-+#define THREE_PERCENT_OF_10000 300
-+
-+#define LAST_RECORD_TYPE 0xff
-+
-+/* GUID to validate external display connection info table (aka OPM module) */
-+static const uint8_t ext_display_connection_guid[NUMBER_OF_UCHAR_FOR_GUID] = {
-+ 0x91, 0x6E, 0x57, 0x09,
-+ 0x3F, 0x6D, 0xD2, 0x11,
-+ 0x39, 0x8E, 0x00, 0xA0,
-+ 0xC9, 0x69, 0x72, 0x3B};
-+
-+#define GET_IMAGE(type, offset) ((type *) get_image(bp, offset, sizeof(type)))
-+#define DATA_TABLES(table) (bp->master_data_tbl->ListOfDataTables.table)
-+
-+static uint8_t *get_image(struct bios_parser *bp, uint32_t offset,
-+ uint32_t size);
-+static uint32_t get_record_size(uint8_t *record);
-+static uint32_t get_edid_size(const ATOM_FAKE_EDID_PATCH_RECORD *edid);
-+static enum object_type object_type_from_bios_object_id(
-+ uint32_t bios_object_id);
-+static struct graphics_object_id object_id_from_bios_object_id(
-+ uint32_t bios_object_id);
-+static enum object_enum_id enum_id_from_bios_object_id(uint32_t bios_object_id);
-+static enum encoder_id encoder_id_from_bios_object_id(uint32_t bios_object_id);
-+static enum connector_id connector_id_from_bios_object_id(
-+ uint32_t bios_object_id);
-+static uint32_t id_from_bios_object_id(enum object_type type,
-+ uint32_t bios_object_id);
-+static uint32_t gpu_id_from_bios_object_id(uint32_t bios_object_id);
-+static enum generic_id generic_id_from_bios_object_id(uint32_t bios_object_id);
-+static void get_atom_data_table_revision(
-+ ATOM_COMMON_TABLE_HEADER *atom_data_tbl,
-+ struct atom_data_revision *tbl_revision);
-+static uint32_t get_dst_number_from_object(struct bios_parser *bp,
-+ ATOM_OBJECT *object);
-+static uint32_t get_src_obj_list(struct bios_parser *bp, ATOM_OBJECT *object,
-+ uint16_t **id_list);
-+static uint32_t get_dest_obj_list(struct bios_parser *bp,
-+ ATOM_OBJECT *object, uint16_t **id_list);
-+static ATOM_OBJECT *get_bios_object(struct bios_parser *bp,
-+ struct graphics_object_id id);
-+static enum bp_result get_gpio_i2c_info(struct bios_parser *bp,
-+ ATOM_I2C_RECORD *record,
-+ struct graphics_object_i2c_info *info);
-+static ATOM_HPD_INT_RECORD *get_hpd_record(struct bios_parser *bp,
-+ ATOM_OBJECT *object);
-+static struct device_id device_type_from_device_id(uint16_t device_id);
-+static uint32_t signal_to_ss_id(enum as_signal_type signal);
-+static uint32_t get_support_mask_for_device_id(struct device_id device_id);
-+static ATOM_ENCODER_CAP_RECORD *get_encoder_cap_record(
-+ struct bios_parser *bp,
-+ ATOM_OBJECT *object);
-+static void process_ext_display_connection_info(struct bios_parser *bp);
-+
-+#define BIOS_IMAGE_SIZE_OFFSET 2
-+#define BIOS_IMAGE_SIZE_UNIT 512
-+
-+static bool bios_parser_construct(
-+ struct bios_parser *bp,
-+ struct bp_init_data *init,
-+ struct adapter_service *as)
-+{
-+ uint16_t *rom_header_offset = NULL;
-+ ATOM_ROM_HEADER *rom_header = NULL;
-+ ATOM_OBJECT_HEADER *object_info_tbl;
-+ enum dce_version dce_version;
-+
-+ if (!as)
-+ return false;
-+
-+ if (!init)
-+ return false;
-+
-+ if (!init->bios)
-+ return false;
-+
-+ dce_version = dal_adapter_service_get_dce_version(as);
-+ bp->ctx = init->ctx;
-+ bp->as = as;
-+ bp->bios = init->bios;
-+ bp->bios_size = bp->bios[BIOS_IMAGE_SIZE_OFFSET] * BIOS_IMAGE_SIZE_UNIT;
-+ bp->bios_local_image = NULL;
-+ bp->lcd_scale = LCD_SCALE_UNKNOWN;
-+
-+ rom_header_offset =
-+ GET_IMAGE(uint16_t, OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER);
-+
-+ if (!rom_header_offset)
-+ return false;
-+
-+ rom_header = GET_IMAGE(ATOM_ROM_HEADER, *rom_header_offset);
-+
-+ if (!rom_header)
-+ return false;
-+
-+ bp->master_data_tbl =
-+ GET_IMAGE(ATOM_MASTER_DATA_TABLE,
-+ rom_header->usMasterDataTableOffset);
-+
-+ if (!bp->master_data_tbl)
-+ return false;
-+
-+ bp->object_info_tbl_offset = DATA_TABLES(Object_Header);
-+
-+ if (!bp->object_info_tbl_offset)
-+ return false;
-+
-+ object_info_tbl =
-+ GET_IMAGE(ATOM_OBJECT_HEADER, bp->object_info_tbl_offset);
-+
-+ if (!object_info_tbl)
-+ return false;
-+
-+ get_atom_data_table_revision(&object_info_tbl->sHeader,
-+ &bp->object_info_tbl.revision);
-+
-+ if (bp->object_info_tbl.revision.major == 1
-+ && bp->object_info_tbl.revision.minor >= 3) {
-+ ATOM_OBJECT_HEADER_V3 *tbl_v3;
-+
-+ tbl_v3 = GET_IMAGE(ATOM_OBJECT_HEADER_V3,
-+ bp->object_info_tbl_offset);
-+ if (!tbl_v3)
-+ return false;
-+
-+ bp->object_info_tbl.v1_3 = tbl_v3;
-+ } else if (bp->object_info_tbl.revision.major == 1
-+ && bp->object_info_tbl.revision.minor >= 1)
-+ bp->object_info_tbl.v1_1 = object_info_tbl;
-+ else
-+ return false;
-+
-+#if defined(CONFIG_DRM_AMD_DAL_VBIOS_PRESENT)
-+ bp->vbios_helper_data.active = 0;
-+ bp->vbios_helper_data.requested = 0;
-+ dal_bios_parser_init_bios_helper(bp, dce_version);
-+#endif
-+ dal_bios_parser_init_cmd_tbl(bp);
-+ dal_bios_parser_init_cmd_tbl_helper(&bp->cmd_helper, dce_version);
-+
-+ return true;
-+}
-+
-+struct bios_parser *dal_bios_parser_create(
-+ struct bp_init_data *init, struct adapter_service *as)
-+{
-+ struct bios_parser *bp = NULL;
-+
-+ bp = dc_service_alloc(init->ctx, sizeof(struct bios_parser));
-+ if (!bp)
-+ return NULL;
-+
-+ if (bios_parser_construct(bp, init, as))
-+ return bp;
-+
-+ dc_service_free(init->ctx, bp);
-+ BREAK_TO_DEBUGGER();
-+ return NULL;
-+}
-+
-+static void destruct(struct bios_parser *bp)
-+{
-+ if (bp->bios_local_image)
-+ dc_service_free(bp->ctx, bp->bios_local_image);
-+}
-+
-+void dal_bios_parser_destroy(struct bios_parser **bp)
-+{
-+ if (!bp || !*bp) {
-+ BREAK_TO_DEBUGGER();
-+ return;
-+ }
-+
-+ destruct(*bp);
-+
-+ dc_service_free((*bp)->ctx, *bp);
-+ *bp = NULL;
-+}
-+
-+void dal_bios_parser_power_down(struct bios_parser *bp)
-+{
-+#if defined(CONFIG_DRM_AMD_DAL_VBIOS_PRESENT)
-+ dal_bios_parser_set_scratch_lcd_scale(bp, bp->lcd_scale);
-+#endif
-+}
-+
-+void dal_bios_parser_power_up(struct bios_parser *bp)
-+{
-+#if defined(CONFIG_DRM_AMD_DAL_VBIOS_PRESENT)
-+ if (bp->lcd_scale == LCD_SCALE_UNKNOWN)
-+ bp->lcd_scale = dal_bios_parser_get_scratch_lcd_scale(bp);
-+#endif
-+}
-+
-+static uint8_t get_number_of_objects(struct bios_parser *bp, uint32_t offset)
-+{
-+ ATOM_OBJECT_TABLE *table;
-+
-+ uint32_t object_table_offset = bp->object_info_tbl_offset + offset;
-+
-+ table = GET_IMAGE(ATOM_OBJECT_TABLE, object_table_offset);
-+
-+ if (!table)
-+ return 0;
-+ else
-+ return table->ucNumberOfObjects;
-+}
-+
-+uint8_t dal_bios_parser_get_encoders_number(struct bios_parser *bp)
-+{
-+ return get_number_of_objects(bp,
-+ le16_to_cpu(bp->object_info_tbl.v1_1->usEncoderObjectTableOffset));
-+}
-+
-+uint8_t dal_bios_parser_get_connectors_number(struct bios_parser *bp)
-+{
-+ return get_number_of_objects(bp,
-+ le16_to_cpu(bp->object_info_tbl.v1_1->usConnectorObjectTableOffset));
-+}
-+
-+uint32_t dal_bios_parser_get_oem_ddc_lines_number(struct bios_parser *bp)
-+{
-+ uint32_t number = 0;
-+
-+ if (DATA_TABLES(OemInfo) != 0) {
-+ ATOM_OEM_INFO *info;
-+
-+ info = GET_IMAGE(ATOM_OEM_INFO,
-+ DATA_TABLES(OemInfo));
-+
-+ if (le16_to_cpu(info->sHeader.usStructureSize)
-+ > sizeof(ATOM_COMMON_TABLE_HEADER)) {
-+
-+ number = (le16_to_cpu(info->sHeader.usStructureSize)
-+ - sizeof(ATOM_COMMON_TABLE_HEADER))
-+ / sizeof(ATOM_I2C_ID_CONFIG_ACCESS);
-+
-+ }
-+ }
-+
-+ return number;
-+}
-+
-+struct graphics_object_id dal_bios_parser_get_encoder_id(struct bios_parser *bp,
-+ uint32_t i)
-+{
-+ struct graphics_object_id object_id = dal_graphics_object_id_init(
-+ 0, ENUM_ID_UNKNOWN, OBJECT_TYPE_UNKNOWN);
-+
-+ uint32_t encoder_table_offset = bp->object_info_tbl_offset
-+ + le16_to_cpu(bp->object_info_tbl.v1_1->usEncoderObjectTableOffset);
-+
-+ ATOM_OBJECT_TABLE *tbl =
-+ GET_IMAGE(ATOM_OBJECT_TABLE, encoder_table_offset);
-+
-+ if (tbl && tbl->ucNumberOfObjects > i) {
-+ const uint16_t id = le16_to_cpu(tbl->asObjects[i].usObjectID);
-+
-+ object_id = object_id_from_bios_object_id(id);
-+ }
-+
-+ return object_id;
-+}
-+
-+struct graphics_object_id dal_bios_parser_get_connector_id(
-+ struct bios_parser *bp,
-+ uint8_t i)
-+{
-+ struct graphics_object_id object_id = dal_graphics_object_id_init(
-+ 0, ENUM_ID_UNKNOWN, OBJECT_TYPE_UNKNOWN);
-+
-+ uint32_t connector_table_offset = bp->object_info_tbl_offset
-+ + le16_to_cpu(bp->object_info_tbl.v1_1->usConnectorObjectTableOffset);
-+
-+ ATOM_OBJECT_TABLE *tbl =
-+ GET_IMAGE(ATOM_OBJECT_TABLE, connector_table_offset);
-+
-+ if (tbl && tbl->ucNumberOfObjects > i) {
-+ const uint16_t id = le16_to_cpu(tbl->asObjects[i].usObjectID);
-+
-+ object_id = object_id_from_bios_object_id(id);
-+ }
-+
-+ return object_id;
-+}
-+
-+uint32_t dal_bios_parser_get_src_number(struct bios_parser *bp,
-+ struct graphics_object_id id)
-+{
-+ uint32_t offset;
-+ uint8_t *number;
-+ ATOM_OBJECT *object;
-+
-+ object = get_bios_object(bp, id);
-+
-+ if (!object) {
-+ BREAK_TO_DEBUGGER(); /* Invalid object id */
-+ return 0;
-+ }
-+
-+ offset = le16_to_cpu(object->usSrcDstTableOffset)
-+ + bp->object_info_tbl_offset;
-+
-+ number = GET_IMAGE(uint8_t, offset);
-+ if (!number)
-+ return 0;
-+
-+ return *number;
-+}
-+
-+uint32_t dal_bios_parser_get_dst_number(struct bios_parser *bp,
-+ struct graphics_object_id id)
-+{
-+ ATOM_OBJECT *object = get_bios_object(bp, id);
-+
-+ return get_dst_number_from_object(bp, object);
-+}
-+
-+enum bp_result dal_bios_parser_get_src_obj(struct bios_parser *bp,
-+ struct graphics_object_id object_id, uint32_t index,
-+ struct graphics_object_id *src_object_id)
-+{
-+ uint32_t number;
-+ uint16_t *id;
-+ ATOM_OBJECT *object;
-+
-+ if (!src_object_id)
-+ return BP_RESULT_BADINPUT;
-+
-+ object = get_bios_object(bp, object_id);
-+
-+ if (!object) {
-+ BREAK_TO_DEBUGGER(); /* Invalid object id */
-+ return BP_RESULT_BADINPUT;
-+ }
-+
-+ number = get_src_obj_list(bp, object, &id);
-+
-+ if (number <= index)
-+ return BP_RESULT_BADINPUT;
-+
-+ *src_object_id = object_id_from_bios_object_id(id[index]);
-+
-+ return BP_RESULT_OK;
-+}
-+
-+enum bp_result dal_bios_parser_get_dst_obj(struct bios_parser *bp,
-+ struct graphics_object_id object_id, uint32_t index,
-+ struct graphics_object_id *dest_object_id)
-+{
-+ uint32_t number;
-+ uint16_t *id;
-+ ATOM_OBJECT *object;
-+
-+ if (!dest_object_id)
-+ return BP_RESULT_BADINPUT;
-+
-+ object = get_bios_object(bp, object_id);
-+
-+ number = get_dest_obj_list(bp, object, &id);
-+
-+ if (number <= index)
-+ return BP_RESULT_BADINPUT;
-+
-+ *dest_object_id = object_id_from_bios_object_id(id[index]);
-+
-+ return BP_RESULT_OK;
-+}
-+
-+enum bp_result dal_bios_parser_get_oem_ddc_info(struct bios_parser *bp,
-+ uint32_t index,
-+ struct graphics_object_i2c_info *info)
-+{
-+
-+ if (!info)
-+ return BP_RESULT_BADINPUT;
-+
-+ if (DATA_TABLES(OemInfo) != 0) {
-+ ATOM_OEM_INFO *tbl;
-+
-+ tbl = GET_IMAGE(ATOM_OEM_INFO, DATA_TABLES(OemInfo));
-+
-+ if (le16_to_cpu(tbl->sHeader.usStructureSize)
-+ > sizeof(ATOM_COMMON_TABLE_HEADER)) {
-+ ATOM_I2C_RECORD record;
-+ ATOM_I2C_ID_CONFIG_ACCESS *config;
-+
-+ dc_service_memset(&record, 0, sizeof(record));
-+
-+ config = &tbl->sucI2cId + index - 1;
-+
-+ record.sucI2cId.bfHW_Capable =
-+ config->sbfAccess.bfHW_Capable;
-+ record.sucI2cId.bfI2C_LineMux =
-+ config->sbfAccess.bfI2C_LineMux;
-+ record.sucI2cId.bfHW_EngineID =
-+ config->sbfAccess.bfHW_EngineID;
-+
-+ return get_gpio_i2c_info(bp, &record, info);
-+ }
-+ }
-+
-+ return BP_RESULT_NORECORD;
-+}
-+
-+enum bp_result dal_bios_parser_get_i2c_info(struct bios_parser *bp,
-+ struct graphics_object_id id,
-+ struct graphics_object_i2c_info *info)
-+{
-+ uint32_t offset;
-+ ATOM_OBJECT *object;
-+ ATOM_COMMON_RECORD_HEADER *header;
-+ ATOM_I2C_RECORD *record;
-+
-+ if (!info)
-+ return BP_RESULT_BADINPUT;
-+
-+ object = get_bios_object(bp, id);
-+
-+ if (!object)
-+ return BP_RESULT_BADINPUT;
-+
-+ offset = le16_to_cpu(object->usRecordOffset)
-+ + bp->object_info_tbl_offset;
-+
-+ for (;;) {
-+ header = GET_IMAGE(ATOM_COMMON_RECORD_HEADER, offset);
-+
-+ if (!header)
-+ return BP_RESULT_BADBIOSTABLE;
-+
-+ if (LAST_RECORD_TYPE == header->ucRecordType ||
-+ !header->ucRecordSize)
-+ break;
-+
-+ if (ATOM_I2C_RECORD_TYPE == header->ucRecordType
-+ && sizeof(ATOM_I2C_RECORD) <= header->ucRecordSize) {
-+ /* get the I2C info */
-+ record = (ATOM_I2C_RECORD *) header;
-+
-+ if (get_gpio_i2c_info(bp, record, info) == BP_RESULT_OK)
-+ return BP_RESULT_OK;
-+ }
-+
-+ offset += header->ucRecordSize;
-+ }
-+
-+ return BP_RESULT_NORECORD;
-+}
-+
-+static enum bp_result get_voltage_ddc_info_v1(uint8_t *i2c_line,
-+ ATOM_COMMON_TABLE_HEADER *header,
-+ uint8_t *address)
-+{
-+ enum bp_result result = BP_RESULT_NORECORD;
-+ ATOM_VOLTAGE_OBJECT_INFO *info =
-+ (ATOM_VOLTAGE_OBJECT_INFO *) address;
-+
-+ uint8_t *voltage_current_object = (uint8_t *) &info->asVoltageObj[0];
-+
-+ while ((address + le16_to_cpu(header->usStructureSize)) > voltage_current_object) {
-+ ATOM_VOLTAGE_OBJECT *object =
-+ (ATOM_VOLTAGE_OBJECT *) voltage_current_object;
-+
-+ if ((object->ucVoltageType == SET_VOLTAGE_INIT_MODE) &&
-+ (object->ucVoltageType &
-+ VOLTAGE_CONTROLLED_BY_I2C_MASK)) {
-+
-+ *i2c_line = object->asControl.ucVoltageControlI2cLine
-+ ^ 0x90;
-+ result = BP_RESULT_OK;
-+ break;
-+ }
-+
-+ voltage_current_object += object->ucSize;
-+ }
-+ return result;
-+}
-+
-+static enum bp_result get_voltage_ddc_info_v3(uint8_t *i2c_line,
-+ uint32_t index,
-+ ATOM_COMMON_TABLE_HEADER *header,
-+ uint8_t *address)
-+{
-+ enum bp_result result = BP_RESULT_NORECORD;
-+ ATOM_VOLTAGE_OBJECT_INFO_V3_1 *info =
-+ (ATOM_VOLTAGE_OBJECT_INFO_V3_1 *) address;
-+
-+ uint8_t *voltage_current_object =
-+ (uint8_t *) (&(info->asVoltageObj[0]));
-+
-+ while ((address + le16_to_cpu(header->usStructureSize)) > voltage_current_object) {
-+ ATOM_I2C_VOLTAGE_OBJECT_V3 *object =
-+ (ATOM_I2C_VOLTAGE_OBJECT_V3 *) voltage_current_object;
-+
-+ if (object->sHeader.ucVoltageMode ==
-+ ATOM_INIT_VOLTAGE_REGULATOR) {
-+ if (object->sHeader.ucVoltageType == index) {
-+ *i2c_line = object->ucVoltageControlI2cLine
-+ ^ 0x90;
-+ result = BP_RESULT_OK;
-+ break;
-+ }
-+ }
-+
-+ voltage_current_object += le16_to_cpu(object->sHeader.usSize);
-+ }
-+ return result;
-+}
-+
-+enum bp_result dal_bios_parser_get_voltage_ddc_info(struct bios_parser *bp,
-+ uint32_t index,
-+ struct graphics_object_i2c_info *info)
-+{
-+ uint8_t i2c_line = 0;
-+ enum bp_result result = BP_RESULT_NORECORD;
-+ uint8_t *voltage_info_address;
-+ ATOM_COMMON_TABLE_HEADER *header;
-+ struct atom_data_revision revision = {0};
-+
-+ if (!DATA_TABLES(VoltageObjectInfo))
-+ return result;
-+
-+ voltage_info_address = get_image(bp,
-+ DATA_TABLES(VoltageObjectInfo),
-+ sizeof(ATOM_COMMON_TABLE_HEADER));
-+
-+ header = (ATOM_COMMON_TABLE_HEADER *) voltage_info_address;
-+
-+ get_atom_data_table_revision(header, &revision);
-+
-+ switch (revision.major) {
-+ case 1:
-+ case 2:
-+ result = get_voltage_ddc_info_v1(&i2c_line, header,
-+ voltage_info_address);
-+ break;
-+ case 3:
-+ if (revision.minor != 1)
-+ break;
-+ result = get_voltage_ddc_info_v3(&i2c_line, index, header,
-+ voltage_info_address);
-+ break;
-+ }
-+
-+ if (result == BP_RESULT_OK)
-+ result = dal_bios_parser_get_thermal_ddc_info(bp,
-+ i2c_line, info);
-+
-+
-+ return result;
-+}
-+
-+enum bp_result dal_bios_parser_get_thermal_ddc_info(
-+ struct bios_parser *bp,
-+ uint32_t i2c_channel_id,
-+ struct graphics_object_i2c_info *info)
-+{
-+ ATOM_I2C_ID_CONFIG_ACCESS *config;
-+ ATOM_I2C_RECORD record;
-+
-+ if (!info)
-+ return BP_RESULT_BADINPUT;
-+
-+ config = (ATOM_I2C_ID_CONFIG_ACCESS *) &i2c_channel_id;
-+
-+ record.sucI2cId.bfHW_Capable = config->sbfAccess.bfHW_Capable;
-+ record.sucI2cId.bfI2C_LineMux = config->sbfAccess.bfI2C_LineMux;
-+ record.sucI2cId.bfHW_EngineID = config->sbfAccess.bfHW_EngineID;
-+
-+ return get_gpio_i2c_info(bp, &record, info);
-+}
-+
-+enum bp_result dal_bios_parser_get_ddc_info_for_i2c_line(struct bios_parser *bp,
-+ uint8_t i2c_line, struct graphics_object_i2c_info *info)
-+{
-+ uint32_t offset;
-+ ATOM_OBJECT *object;
-+ ATOM_OBJECT_TABLE *table;
-+ uint32_t i;
-+
-+ if (!info)
-+ return BP_RESULT_BADINPUT;
-+
-+ offset = le16_to_cpu(bp->object_info_tbl.v1_1->usConnectorObjectTableOffset);
-+
-+ offset += bp->object_info_tbl_offset;
-+
-+ table = GET_IMAGE(ATOM_OBJECT_TABLE, offset);
-+
-+ if (!table)
-+ return BP_RESULT_BADBIOSTABLE;
-+
-+ for (i = 0; i < table->ucNumberOfObjects; i++) {
-+ object = &table->asObjects[i];
-+
-+ if (!object) {
-+ BREAK_TO_DEBUGGER(); /* Invalid object id */
-+ return BP_RESULT_BADINPUT;
-+ }
-+
-+ offset = le16_to_cpu(object->usRecordOffset)
-+ + bp->object_info_tbl_offset;
-+
-+ for (;;) {
-+ ATOM_COMMON_RECORD_HEADER *header =
-+ GET_IMAGE(ATOM_COMMON_RECORD_HEADER, offset);
-+
-+ if (!header)
-+ return BP_RESULT_BADBIOSTABLE;
-+
-+ offset += header->ucRecordSize;
-+
-+ if (LAST_RECORD_TYPE == header->ucRecordType ||
-+ !header->ucRecordSize)
-+ break;
-+
-+ if (ATOM_I2C_RECORD_TYPE == header->ucRecordType
-+ && sizeof(ATOM_I2C_RECORD) <=
-+ header->ucRecordSize) {
-+ ATOM_I2C_RECORD *record =
-+ (ATOM_I2C_RECORD *) header;
-+
-+ if (i2c_line != record->sucI2cId.bfI2C_LineMux)
-+ continue;
-+
-+ /* get the I2C info */
-+ if (get_gpio_i2c_info(bp, record, info) ==
-+ BP_RESULT_OK)
-+ return BP_RESULT_OK;
-+ }
-+ }
-+ }
-+
-+ return BP_RESULT_NORECORD;
-+}
-+
-+enum bp_result dal_bios_parser_get_hpd_info(struct bios_parser *bp,
-+ struct graphics_object_id id,
-+ struct graphics_object_hpd_info *info)
-+{
-+ ATOM_OBJECT *object;
-+ ATOM_HPD_INT_RECORD *record = NULL;
-+
-+ if (!info)
-+ return BP_RESULT_BADINPUT;
-+
-+ object = get_bios_object(bp, id);
-+
-+ if (!object)
-+ return BP_RESULT_BADINPUT;
-+
-+ record = get_hpd_record(bp, object);
-+
-+ if (record != NULL) {
-+ info->hpd_int_gpio_uid = record->ucHPDIntGPIOID;
-+ info->hpd_active = record->ucPlugged_PinState;
-+ return BP_RESULT_OK;
-+ }
-+
-+ return BP_RESULT_NORECORD;
-+}
-+
-+uint32_t dal_bios_parser_get_gpio_record(
-+ struct bios_parser *bp,
-+ struct graphics_object_id id,
-+ struct bp_gpio_cntl_info *gpio_record,
-+ uint32_t record_size)
-+{
-+ ATOM_COMMON_RECORD_HEADER *header = NULL;
-+ ATOM_OBJECT_GPIO_CNTL_RECORD *record = NULL;
-+ ATOM_OBJECT *object = get_bios_object(bp, id);
-+ uint32_t offset;
-+ uint32_t pins_number;
-+ uint32_t i;
-+
-+ if (!object)
-+ return 0;
-+
-+ /* Initialise offset */
-+ offset = le16_to_cpu(object->usRecordOffset)
-+ + bp->object_info_tbl_offset;
-+
-+ for (;;) {
-+ /* Get record header */
-+ header = GET_IMAGE(ATOM_COMMON_RECORD_HEADER, offset);
-+ if (!header || header->ucRecordType == LAST_RECORD_TYPE ||
-+ !header->ucRecordSize)
-+ break;
-+
-+ /* If this is gpio control record - stop. We found the record */
-+ if (header->ucRecordType == ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE
-+ && header->ucRecordSize
-+ >= sizeof(ATOM_OBJECT_GPIO_CNTL_RECORD)) {
-+ record = (ATOM_OBJECT_GPIO_CNTL_RECORD *) header;
-+ break;
-+ }
-+
-+ /* Advance to next record */
-+ offset += header->ucRecordSize;
-+ }
-+
-+ /* If we did not find a record - return */
-+ if (!record)
-+ return 0;
-+
-+ /* Extract gpio IDs from bios record (make sure we do not exceed passed
-+ * array size) */
-+ pins_number = (record->ucNumberOfPins < record_size ?
-+ record->ucNumberOfPins : record_size);
-+ for (i = 0; i < pins_number; i++) {
-+ uint8_t output_state = ((record->asGpio[i].ucGPIO_PinState
-+ & GPIO_PIN_OUTPUT_STATE_MASK)
-+ >> GPIO_PIN_OUTPUT_STATE_SHIFT);
-+ gpio_record[i].id = record->asGpio[i].ucGPIOID;
-+
-+ switch (output_state) {
-+ case GPIO_PIN_STATE_ACTIVE_LOW:
-+ gpio_record[i].state =
-+ GPIO_PIN_OUTPUT_STATE_ACTIVE_LOW;
-+ break;
-+
-+ case GPIO_PIN_STATE_ACTIVE_HIGH:
-+ gpio_record[i].state =
-+ GPIO_PIN_OUTPUT_STATE_ACTIVE_HIGH;
-+ break;
-+
-+ default:
-+ BREAK_TO_DEBUGGER(); /* Invalid Pin Output State */
-+ break;
-+ }
-+ }
-+
-+ return pins_number;
-+}
-+
-+enum bp_result dal_bios_parser_get_device_tag_record(
-+ struct bios_parser *bp,
-+ ATOM_OBJECT *object,
-+ ATOM_CONNECTOR_DEVICE_TAG_RECORD **record)
-+{
-+ ATOM_COMMON_RECORD_HEADER *header;
-+ uint32_t offset;
-+
-+ offset = le16_to_cpu(object->usRecordOffset)
-+ + bp->object_info_tbl_offset;
-+
-+ for (;;) {
-+ header = GET_IMAGE(ATOM_COMMON_RECORD_HEADER, offset);
-+
-+ if (!header)
-+ return BP_RESULT_BADBIOSTABLE;
-+
-+ offset += header->ucRecordSize;
-+
-+ if (LAST_RECORD_TYPE == header->ucRecordType ||
-+ !header->ucRecordSize)
-+ break;
-+
-+ if (ATOM_CONNECTOR_DEVICE_TAG_RECORD_TYPE !=
-+ header->ucRecordType)
-+ continue;
-+
-+ if (sizeof(ATOM_CONNECTOR_DEVICE_TAG) > header->ucRecordSize)
-+ continue;
-+
-+ *record = (ATOM_CONNECTOR_DEVICE_TAG_RECORD *) header;
-+ return BP_RESULT_OK;
-+ }
-+
-+ return BP_RESULT_NORECORD;
-+}
-+
-+enum bp_result dal_bios_parser_get_device_tag(
-+ struct bios_parser *bp,
-+ struct graphics_object_id connector_object_id,
-+ uint32_t device_tag_index,
-+ struct connector_device_tag_info *info)
-+{
-+ ATOM_OBJECT *object;
-+ ATOM_CONNECTOR_DEVICE_TAG_RECORD *record = NULL;
-+ ATOM_CONNECTOR_DEVICE_TAG *device_tag;
-+
-+ if (!info)
-+ return BP_RESULT_BADINPUT;
-+
-+ /* getBiosObject will return MXM object */
-+ object = get_bios_object(bp, connector_object_id);
-+
-+ if (!object) {
-+ BREAK_TO_DEBUGGER(); /* Invalid object id */
-+ return BP_RESULT_BADINPUT;
-+ }
-+
-+ if (dal_bios_parser_get_device_tag_record(bp, object, &record)
-+ != BP_RESULT_OK)
-+ return BP_RESULT_NORECORD;
-+
-+ if (device_tag_index >= record->ucNumberOfDevice)
-+ return BP_RESULT_NORECORD;
-+
-+ device_tag = &record->asDeviceTag[device_tag_index];
-+
-+ info->acpi_device = le32_to_cpu(device_tag->ulACPIDeviceEnum);
-+ info->dev_id =
-+ device_type_from_device_id(le16_to_cpu(device_tag->usDeviceID));
-+
-+ return BP_RESULT_OK;
-+}
-+
-+static enum bp_result get_firmware_info_v1_4(
-+ struct bios_parser *bp,
-+ struct firmware_info *info);
-+static enum bp_result get_firmware_info_v2_1(
-+ struct bios_parser *bp,
-+ struct firmware_info *info);
-+static enum bp_result get_firmware_info_v2_2(
-+ struct bios_parser *bp,
-+ struct firmware_info *info);
-+
-+enum bp_result dal_bios_parser_get_firmware_info(
-+ struct bios_parser *bp,
-+ struct firmware_info *info)
-+{
-+ enum bp_result result = BP_RESULT_BADBIOSTABLE;
-+ ATOM_COMMON_TABLE_HEADER *header;
-+ struct atom_data_revision revision;
-+
-+ if (info && DATA_TABLES(FirmwareInfo)) {
-+ header = GET_IMAGE(ATOM_COMMON_TABLE_HEADER,
-+ DATA_TABLES(FirmwareInfo));
-+ get_atom_data_table_revision(header, &revision);
-+ switch (revision.major) {
-+ case 1:
-+ switch (revision.minor) {
-+ case 4:
-+ result = get_firmware_info_v1_4(bp, info);
-+ break;
-+ default:
-+ break;
-+ }
-+ break;
-+
-+ case 2:
-+ switch (revision.minor) {
-+ case 1:
-+ result = get_firmware_info_v2_1(bp, info);
-+ break;
-+ case 2:
-+ result = get_firmware_info_v2_2(bp, info);
-+ break;
-+ default:
-+ break;
-+ }
-+ break;
-+ default:
-+ break;
-+ }
-+ }
-+
-+ return result;
-+}
-+
-+static enum bp_result get_firmware_info_v1_4(
-+ struct bios_parser *bp,
-+ struct firmware_info *info)
-+{
-+ ATOM_FIRMWARE_INFO_V1_4 *firmware_info =
-+ GET_IMAGE(ATOM_FIRMWARE_INFO_V1_4,
-+ DATA_TABLES(FirmwareInfo));
-+
-+ if (!info)
-+ return BP_RESULT_BADINPUT;
-+
-+ if (!firmware_info)
-+ return BP_RESULT_BADBIOSTABLE;
-+
-+ dc_service_memset(info, 0, sizeof(*info));
-+
-+ /* Pixel clock pll information. We need to convert from 10KHz units into
-+ * KHz units */
-+ info->pll_info.crystal_frequency =
-+ le16_to_cpu(firmware_info->usReferenceClock) * 10;
-+ info->pll_info.min_input_pxl_clk_pll_frequency =
-+ le16_to_cpu(firmware_info->usMinPixelClockPLL_Input) * 10;
-+ info->pll_info.max_input_pxl_clk_pll_frequency =
-+ le16_to_cpu(firmware_info->usMaxPixelClockPLL_Input) * 10;
-+ info->pll_info.min_output_pxl_clk_pll_frequency =
-+ le32_to_cpu(firmware_info->ulMinPixelClockPLL_Output) * 10;
-+ info->pll_info.max_output_pxl_clk_pll_frequency =
-+ le32_to_cpu(firmware_info->ulMaxPixelClockPLL_Output) * 10;
-+
-+ if (firmware_info->usFirmwareCapability.sbfAccess.MemoryClockSS_Support)
-+ /* Since there is no information on the SS, report conservative
-+ * value 3% for bandwidth calculation */
-+ /* unit of 0.01% */
-+ info->feature.memory_clk_ss_percentage = THREE_PERCENT_OF_10000;
-+
-+ if (firmware_info->usFirmwareCapability.sbfAccess.EngineClockSS_Support)
-+ /* Since there is no information on the SS,report conservative
-+ * value 3% for bandwidth calculation */
-+ /* unit of 0.01% */
-+ info->feature.engine_clk_ss_percentage = THREE_PERCENT_OF_10000;
-+
-+ return BP_RESULT_OK;
-+}
-+
-+static enum bp_result get_ss_info_v3_1(
-+ struct bios_parser *bp,
-+ uint32_t id,
-+ uint32_t index,
-+ struct spread_spectrum_info *ss_info);
-+
-+static enum bp_result get_firmware_info_v2_1(
-+ struct bios_parser *bp,
-+ struct firmware_info *info)
-+{
-+ ATOM_FIRMWARE_INFO_V2_1 *firmwareInfo =
-+ GET_IMAGE(ATOM_FIRMWARE_INFO_V2_1, DATA_TABLES(FirmwareInfo));
-+ struct spread_spectrum_info internalSS;
-+ uint32_t index;
-+
-+ if (!info)
-+ return BP_RESULT_BADINPUT;
-+
-+ if (!firmwareInfo)
-+ return BP_RESULT_BADBIOSTABLE;
-+
-+ dc_service_memset(info, 0, sizeof(*info));
-+
-+ /* Pixel clock pll information. We need to convert from 10KHz units into
-+ * KHz units */
-+ info->pll_info.crystal_frequency =
-+ le16_to_cpu(firmwareInfo->usCoreReferenceClock) * 10;
-+ info->pll_info.min_input_pxl_clk_pll_frequency =
-+ le16_to_cpu(firmwareInfo->usMinPixelClockPLL_Input) * 10;
-+ info->pll_info.max_input_pxl_clk_pll_frequency =
-+ le16_to_cpu(firmwareInfo->usMaxPixelClockPLL_Input) * 10;
-+ info->pll_info.min_output_pxl_clk_pll_frequency =
-+ le32_to_cpu(firmwareInfo->ulMinPixelClockPLL_Output) * 10;
-+ info->pll_info.max_output_pxl_clk_pll_frequency =
-+ le32_to_cpu(firmwareInfo->ulMaxPixelClockPLL_Output) * 10;
-+ info->default_display_engine_pll_frequency =
-+ le32_to_cpu(firmwareInfo->ulDefaultDispEngineClkFreq) * 10;
-+ info->external_clock_source_frequency_for_dp =
-+ le16_to_cpu(firmwareInfo->usUniphyDPModeExtClkFreq) * 10;
-+ info->min_allowed_bl_level = firmwareInfo->ucMinAllowedBL_Level;
-+
-+ /* There should be only one entry in the SS info table for Memory Clock
-+ */
-+ index = 0;
-+ if (firmwareInfo->usFirmwareCapability.sbfAccess.MemoryClockSS_Support)
-+ /* Since there is no information for external SS, report
-+ * conservative value 3% for bandwidth calculation */
-+ /* unit of 0.01% */
-+ info->feature.memory_clk_ss_percentage = THREE_PERCENT_OF_10000;
-+ else if (get_ss_info_v3_1(bp,
-+ ASIC_INTERNAL_MEMORY_SS, index, &internalSS) == BP_RESULT_OK) {
-+ if (internalSS.spread_spectrum_percentage) {
-+ info->feature.memory_clk_ss_percentage =
-+ internalSS.spread_spectrum_percentage;
-+ if (internalSS.type.CENTER_MODE) {
-+ /* if it is centermode, the exact SS Percentage
-+ * will be round up of half of the percentage
-+ * reported in the SS table */
-+ ++info->feature.memory_clk_ss_percentage;
-+ info->feature.memory_clk_ss_percentage /= 2;
-+ }
-+ }
-+ }
-+
-+ /* There should be only one entry in the SS info table for Engine Clock
-+ */
-+ index = 1;
-+ if (firmwareInfo->usFirmwareCapability.sbfAccess.EngineClockSS_Support)
-+ /* Since there is no information for external SS, report
-+ * conservative value 3% for bandwidth calculation */
-+ /* unit of 0.01% */
-+ info->feature.engine_clk_ss_percentage = THREE_PERCENT_OF_10000;
-+ else if (get_ss_info_v3_1(bp,
-+ ASIC_INTERNAL_ENGINE_SS, index, &internalSS) == BP_RESULT_OK) {
-+ if (internalSS.spread_spectrum_percentage) {
-+ info->feature.engine_clk_ss_percentage =
-+ internalSS.spread_spectrum_percentage;
-+ if (internalSS.type.CENTER_MODE) {
-+ /* if it is centermode, the exact SS Percentage
-+ * will be round up of half of the percentage
-+ * reported in the SS table */
-+ ++info->feature.engine_clk_ss_percentage;
-+ info->feature.engine_clk_ss_percentage /= 2;
-+ }
-+ }
-+ }
-+
-+ return BP_RESULT_OK;
-+}
-+
-+static enum bp_result get_firmware_info_v2_2(
-+ struct bios_parser *bp,
-+ struct firmware_info *info)
-+{
-+ ATOM_FIRMWARE_INFO_V2_2 *firmware_info;
-+ struct spread_spectrum_info internal_ss;
-+ uint32_t index;
-+
-+ if (!info)
-+ return BP_RESULT_BADINPUT;
-+
-+ firmware_info = GET_IMAGE(ATOM_FIRMWARE_INFO_V2_2,
-+ DATA_TABLES(FirmwareInfo));
-+
-+ if (!firmware_info)
-+ return BP_RESULT_BADBIOSTABLE;
-+
-+ dc_service_memset(info, 0, sizeof(*info));
-+
-+ /* Pixel clock pll information. We need to convert from 10KHz units into
-+ * KHz units */
-+ info->pll_info.crystal_frequency =
-+ le16_to_cpu(firmware_info->usCoreReferenceClock) * 10;
-+ info->pll_info.min_input_pxl_clk_pll_frequency =
-+ le16_to_cpu(firmware_info->usMinPixelClockPLL_Input) * 10;
-+ info->pll_info.max_input_pxl_clk_pll_frequency =
-+ le16_to_cpu(firmware_info->usMaxPixelClockPLL_Input) * 10;
-+ info->pll_info.min_output_pxl_clk_pll_frequency =
-+ le32_to_cpu(firmware_info->ulMinPixelClockPLL_Output) * 10;
-+ info->pll_info.max_output_pxl_clk_pll_frequency =
-+ le32_to_cpu(firmware_info->ulMaxPixelClockPLL_Output) * 10;
-+ info->default_display_engine_pll_frequency =
-+ le32_to_cpu(firmware_info->ulDefaultDispEngineClkFreq) * 10;
-+ info->external_clock_source_frequency_for_dp =
-+ le16_to_cpu(firmware_info->usUniphyDPModeExtClkFreq) * 10;
-+
-+ /* There should be only one entry in the SS info table for Memory Clock
-+ */
-+ index = 0;
-+ if (firmware_info->usFirmwareCapability.sbfAccess.MemoryClockSS_Support)
-+ /* Since there is no information for external SS, report
-+ * conservative value 3% for bandwidth calculation */
-+ /* unit of 0.01% */
-+ info->feature.memory_clk_ss_percentage = THREE_PERCENT_OF_10000;
-+ else if (get_ss_info_v3_1(bp,
-+ ASIC_INTERNAL_MEMORY_SS, index, &internal_ss) == BP_RESULT_OK) {
-+ if (internal_ss.spread_spectrum_percentage) {
-+ info->feature.memory_clk_ss_percentage =
-+ internal_ss.spread_spectrum_percentage;
-+ if (internal_ss.type.CENTER_MODE) {
-+ /* if it is centermode, the exact SS Percentage
-+ * will be round up of half of the percentage
-+ * reported in the SS table */
-+ ++info->feature.memory_clk_ss_percentage;
-+ info->feature.memory_clk_ss_percentage /= 2;
-+ }
-+ }
-+ }
-+
-+ /* There should be only one entry in the SS info table for Engine Clock
-+ */
-+ index = 1;
-+ if (firmware_info->usFirmwareCapability.sbfAccess.EngineClockSS_Support)
-+ /* Since there is no information for external SS, report
-+ * conservative value 3% for bandwidth calculation */
-+ /* unit of 0.01% */
-+ info->feature.engine_clk_ss_percentage = THREE_PERCENT_OF_10000;
-+ else if (get_ss_info_v3_1(bp,
-+ ASIC_INTERNAL_ENGINE_SS, index, &internal_ss) == BP_RESULT_OK) {
-+ if (internal_ss.spread_spectrum_percentage) {
-+ info->feature.engine_clk_ss_percentage =
-+ internal_ss.spread_spectrum_percentage;
-+ if (internal_ss.type.CENTER_MODE) {
-+ /* if it is centermode, the exact SS Percentage
-+ * will be round up of half of the percentage
-+ * reported in the SS table */
-+ ++info->feature.engine_clk_ss_percentage;
-+ info->feature.engine_clk_ss_percentage /= 2;
-+ }
-+ }
-+ }
-+
-+ /* Remote Display */
-+ info->remote_display_config = firmware_info->ucRemoteDisplayConfig;
-+
-+ /* Is allowed minimum BL level */
-+ info->min_allowed_bl_level = firmware_info->ucMinAllowedBL_Level;
-+ /* Used starting from CI */
-+ info->smu_gpu_pll_output_freq =
-+ (uint32_t) (le32_to_cpu(firmware_info->ulGPUPLL_OutputFreq) * 10);
-+
-+ return BP_RESULT_OK;
-+}
-+
-+static enum bp_result get_ss_info_v3_1(
-+ struct bios_parser *bp,
-+ uint32_t id,
-+ uint32_t index,
-+ struct spread_spectrum_info *ss_info)
-+{
-+ ATOM_ASIC_INTERNAL_SS_INFO_V3 *ss_table_header_include;
-+ ATOM_ASIC_SS_ASSIGNMENT_V3 *tbl;
-+ uint32_t table_size;
-+ uint32_t i;
-+ uint32_t table_index = 0;
-+
-+ if (!ss_info)
-+ return BP_RESULT_BADINPUT;
-+
-+ if (!DATA_TABLES(ASIC_InternalSS_Info))
-+ return BP_RESULT_UNSUPPORTED;
-+
-+ ss_table_header_include = GET_IMAGE(ATOM_ASIC_INTERNAL_SS_INFO_V3,
-+ DATA_TABLES(ASIC_InternalSS_Info));
-+ table_size =
-+ (le16_to_cpu(ss_table_header_include->sHeader.usStructureSize)
-+ - sizeof(ATOM_COMMON_TABLE_HEADER))
-+ / sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
-+
-+ tbl = (ATOM_ASIC_SS_ASSIGNMENT_V3 *)
-+ &ss_table_header_include->asSpreadSpectrum[0];
-+
-+ dc_service_memset(ss_info, 0, sizeof(struct spread_spectrum_info));
-+
-+ for (i = 0; i < table_size; i++) {
-+ if (tbl[i].ucClockIndication != (uint8_t) id)
-+ continue;
-+
-+ if (table_index != index) {
-+ table_index++;
-+ continue;
-+ }
-+ /* VBIOS introduced new defines for Version 3, same values as
-+ * before, so now use these new ones for Version 3.
-+ * Shouldn't affect field VBIOS's V3 as define values are still
-+ * same.
-+ * #define SS_MODE_V3_CENTRE_SPREAD_MASK 0x01
-+ * #define SS_MODE_V3_EXTERNAL_SS_MASK 0x02
-+
-+ * Old VBIOS defines:
-+ * #define ATOM_SS_CENTRE_SPREAD_MODE_MASK 0x00000001
-+ * #define ATOM_EXTERNAL_SS_MASK 0x00000002
-+ */
-+
-+ if (SS_MODE_V3_EXTERNAL_SS_MASK & tbl[i].ucSpreadSpectrumMode)
-+ ss_info->type.EXTERNAL = true;
-+
-+ if (SS_MODE_V3_CENTRE_SPREAD_MASK & tbl[i].ucSpreadSpectrumMode)
-+ ss_info->type.CENTER_MODE = true;
-+
-+ /* Older VBIOS (in field) always provides SS percentage in 0.01%
-+ * units set Divider to 100 */
-+ ss_info->spread_percentage_divider = 100;
-+
-+ /* #define SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK 0x10 */
-+ if (SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK
-+ & tbl[i].ucSpreadSpectrumMode)
-+ ss_info->spread_percentage_divider = 1000;
-+
-+ ss_info->type.STEP_AND_DELAY_INFO = false;
-+ /* convert [10KHz] into [KHz] */
-+ ss_info->target_clock_range =
-+ le32_to_cpu(tbl[i].ulTargetClockRange) * 10;
-+ ss_info->spread_spectrum_percentage =
-+ (uint32_t)le16_to_cpu(tbl[i].usSpreadSpectrumPercentage);
-+ ss_info->spread_spectrum_range =
-+ (uint32_t)(le16_to_cpu(tbl[i].usSpreadRateIn10Hz) * 10);
-+
-+ return BP_RESULT_OK;
-+ }
-+ return BP_RESULT_NORECORD;
-+}
-+
-+enum bp_result dal_bios_parser_transmitter_control(
-+ struct bios_parser *bp,
-+ struct bp_transmitter_control *cntl)
-+{
-+ if (!bp->cmd_tbl.transmitter_control)
-+ return BP_RESULT_FAILURE;
-+
-+ return bp->cmd_tbl.transmitter_control(bp, cntl);
-+}
-+
-+enum bp_result dal_bios_parser_encoder_control(
-+ struct bios_parser *bp,
-+ struct bp_encoder_control *cntl)
-+{
-+ if (!bp->cmd_tbl.dig_encoder_control)
-+ return BP_RESULT_FAILURE;
-+
-+ return bp->cmd_tbl.dig_encoder_control(bp, cntl);
-+}
-+
-+enum bp_result dal_bios_parser_adjust_pixel_clock(
-+ struct bios_parser *bp,
-+ struct bp_adjust_pixel_clock_parameters *bp_params)
-+{
-+ if (!bp->cmd_tbl.adjust_display_pll)
-+ return BP_RESULT_FAILURE;
-+
-+ return bp->cmd_tbl.adjust_display_pll(bp, bp_params);
-+}
-+
-+enum bp_result dal_bios_parser_set_pixel_clock(
-+ struct bios_parser *bp,
-+ struct bp_pixel_clock_parameters *bp_params)
-+{
-+ if (!bp->cmd_tbl.set_pixel_clock)
-+ return BP_RESULT_FAILURE;
-+
-+ return bp->cmd_tbl.set_pixel_clock(bp, bp_params);
-+}
-+
-+enum bp_result dal_bios_parser_enable_spread_spectrum_on_ppll(
-+ struct bios_parser *bp,
-+ struct bp_spread_spectrum_parameters *bp_params,
-+ bool enable)
-+{
-+ if (!bp->cmd_tbl.enable_spread_spectrum_on_ppll)
-+ return BP_RESULT_FAILURE;
-+
-+ return bp->cmd_tbl.enable_spread_spectrum_on_ppll(
-+ bp, bp_params, enable);
-+
-+}
-+
-+enum bp_result dal_bios_parser_program_crtc_timing(
-+ struct bios_parser *bp,
-+ struct bp_hw_crtc_timing_parameters *bp_params)
-+{
-+ if (!bp->cmd_tbl.set_crtc_timing)
-+ return BP_RESULT_FAILURE;
-+
-+ return bp->cmd_tbl.set_crtc_timing(bp, bp_params);
-+}
-+
-+enum bp_result dal_bios_parser_program_display_engine_pll(
-+ struct bios_parser *bp,
-+ struct bp_pixel_clock_parameters *bp_params)
-+{
-+
-+ if (!bp->cmd_tbl.program_clock)
-+ return BP_RESULT_FAILURE;
-+
-+ return bp->cmd_tbl.program_clock(bp, bp_params);
-+
-+}
-+
-+enum signal_type dal_bios_parser_dac_load_detect(
-+ struct bios_parser *bp,
-+ struct graphics_object_id encoder,
-+ struct graphics_object_id connector,
-+ enum signal_type display_signal)
-+{
-+ if (!bp->cmd_tbl.dac_load_detection)
-+ return SIGNAL_TYPE_NONE;
-+
-+ return bp->cmd_tbl.dac_load_detection(bp, encoder, connector,
-+ display_signal);
-+}
-+
-+enum bp_result dal_bios_parser_get_divider_for_target_display_clock(
-+ struct bios_parser *bp,
-+ struct bp_display_clock_parameters *bp_params)
-+{
-+ if (!bp->cmd_tbl.compute_memore_engine_pll)
-+ return BP_RESULT_FAILURE;
-+
-+ return bp->cmd_tbl.compute_memore_engine_pll(bp, bp_params);
-+}
-+
-+enum bp_result dal_bios_parser_dvo_encoder_control(
-+ struct bios_parser *bp,
-+ struct bp_dvo_encoder_control *cntl)
-+{
-+ if (!bp->cmd_tbl.dvo_encoder_control)
-+ return BP_RESULT_FAILURE;
-+
-+ return bp->cmd_tbl.dvo_encoder_control(bp, cntl);
-+}
-+
-+enum bp_result dal_bios_parser_enable_crtc(
-+ struct bios_parser *bp,
-+ enum controller_id id,
-+ bool enable)
-+{
-+ if (!bp->cmd_tbl.enable_crtc)
-+ return BP_RESULT_FAILURE;
-+
-+ return bp->cmd_tbl.enable_crtc(bp, id, enable);
-+}
-+
-+enum bp_result dal_bios_parser_blank_crtc(
-+ struct bios_parser *bp,
-+ struct bp_blank_crtc_parameters *bp_params,
-+ bool blank)
-+{
-+ if (!bp->cmd_tbl.blank_crtc)
-+ return BP_RESULT_FAILURE;
-+
-+ return bp->cmd_tbl.blank_crtc(bp, bp_params, blank);
-+}
-+
-+enum bp_result dal_bios_parser_crtc_source_select(
-+ struct bios_parser *bp,
-+ struct bp_crtc_source_select *bp_params)
-+{
-+ if (!bp->cmd_tbl.select_crtc_source)
-+ return BP_RESULT_FAILURE;
-+
-+ return bp->cmd_tbl.select_crtc_source(bp, bp_params);
-+}
-+
-+enum bp_result dal_bios_parser_set_overscan(
-+ struct bios_parser *bp,
-+ struct bp_hw_crtc_overscan_parameters *bp_params)
-+{
-+
-+ if (!bp->cmd_tbl.set_crtc_overscan)
-+ return BP_RESULT_FAILURE;
-+
-+ return bp->cmd_tbl.set_crtc_overscan(bp, bp_params);
-+}
-+
-+enum bp_result dal_bios_parser_enable_memory_requests(
-+ struct bios_parser *bp,
-+ enum controller_id controller_id,
-+ bool enable)
-+{
-+ if (!bp->cmd_tbl.enable_crtc_mem_req)
-+ return BP_RESULT_FAILURE;
-+
-+ return bp->cmd_tbl.enable_crtc_mem_req(bp, controller_id, enable);
-+}
-+
-+enum bp_result dal_bios_parser_external_encoder_control(
-+ struct bios_parser *bp,
-+ struct bp_external_encoder_control *cntl)
-+{
-+ if (!bp->cmd_tbl.external_encoder_control)
-+ return BP_RESULT_FAILURE;
-+
-+ return bp->cmd_tbl.external_encoder_control(bp, cntl);
-+}
-+
-+enum bp_result dal_bios_parser_enable_disp_power_gating(
-+ struct bios_parser *bp,
-+ enum controller_id controller_id,
-+ enum bp_pipe_control_action action)
-+{
-+ if (!bp->cmd_tbl.enable_disp_power_gating)
-+ return BP_RESULT_FAILURE;
-+
-+ return bp->cmd_tbl.enable_disp_power_gating(bp, controller_id,
-+ action);
-+}
-+
-+bool dal_bios_parser_is_device_id_supported(
-+ struct bios_parser *bp,
-+ struct device_id id)
-+{
-+ uint32_t mask = get_support_mask_for_device_id(id);
-+
-+ return (le16_to_cpu(bp->object_info_tbl.v1_1->usDeviceSupport) & mask) != 0;
-+}
-+
-+enum bp_result dal_bios_parser_crt_control(
-+ struct bios_parser *bp,
-+ enum engine_id engine_id,
-+ bool enable,
-+ uint32_t pixel_clock)
-+{
-+ uint8_t standard;
-+
-+ if (!bp->cmd_tbl.dac1_encoder_control &&
-+ engine_id == ENGINE_ID_DACA)
-+ return BP_RESULT_FAILURE;
-+ if (!bp->cmd_tbl.dac2_encoder_control &&
-+ engine_id == ENGINE_ID_DACB)
-+ return BP_RESULT_FAILURE;
-+ /* validate params */
-+ switch (engine_id) {
-+ case ENGINE_ID_DACA:
-+ case ENGINE_ID_DACB:
-+ break;
-+ default:
-+ /* unsupported engine */
-+ return BP_RESULT_FAILURE;
-+ }
-+
-+ standard = ATOM_DAC1_PS2; /* == ATOM_DAC2_PS2 */
-+
-+ if (enable) {
-+ if (engine_id == ENGINE_ID_DACA) {
-+ bp->cmd_tbl.dac1_encoder_control(bp, enable,
-+ pixel_clock, standard);
-+ if (bp->cmd_tbl.dac1_output_control != NULL)
-+ bp->cmd_tbl.dac1_output_control(bp, enable);
-+ } else {
-+ bp->cmd_tbl.dac2_encoder_control(bp, enable,
-+ pixel_clock, standard);
-+ if (bp->cmd_tbl.dac2_output_control != NULL)
-+ bp->cmd_tbl.dac2_output_control(bp, enable);
-+ }
-+ } else {
-+ if (engine_id == ENGINE_ID_DACA) {
-+ if (bp->cmd_tbl.dac1_output_control != NULL)
-+ bp->cmd_tbl.dac1_output_control(bp, enable);
-+ bp->cmd_tbl.dac1_encoder_control(bp, enable,
-+ pixel_clock, standard);
-+ } else {
-+ if (bp->cmd_tbl.dac2_output_control != NULL)
-+ bp->cmd_tbl.dac2_output_control(bp, enable);
-+ bp->cmd_tbl.dac2_encoder_control(bp, enable,
-+ pixel_clock, standard);
-+ }
-+ }
-+
-+ return BP_RESULT_OK;
-+}
-+
-+static ATOM_HPD_INT_RECORD *get_hpd_record(struct bios_parser *bp,
-+ ATOM_OBJECT *object)
-+{
-+ ATOM_COMMON_RECORD_HEADER *header;
-+ uint32_t offset;
-+
-+ if (!object) {
-+ BREAK_TO_DEBUGGER(); /* Invalid object */
-+ return NULL;
-+ }
-+
-+ offset = le16_to_cpu(object->usRecordOffset)
-+ + bp->object_info_tbl_offset;
-+
-+ for (;;) {
-+ header = GET_IMAGE(ATOM_COMMON_RECORD_HEADER, offset);
-+
-+ if (!header)
-+ return NULL;
-+
-+ if (LAST_RECORD_TYPE == header->ucRecordType ||
-+ !header->ucRecordSize)
-+ break;
-+
-+ if (ATOM_HPD_INT_RECORD_TYPE == header->ucRecordType
-+ && sizeof(ATOM_HPD_INT_RECORD) <= header->ucRecordSize)
-+ return (ATOM_HPD_INT_RECORD *) header;
-+
-+ offset += header->ucRecordSize;
-+ }
-+
-+ return NULL;
-+}
-+
-+/**
-+ * Get I2C information of input object id
-+ *
-+ * search all records to find the ATOM_I2C_RECORD_TYPE record IR
-+ */
-+static ATOM_I2C_RECORD *get_i2c_record(
-+ struct bios_parser *bp,
-+ ATOM_OBJECT *object)
-+{
-+ uint32_t offset;
-+ ATOM_COMMON_RECORD_HEADER *record_header;
-+
-+ if (!object) {
-+ BREAK_TO_DEBUGGER();
-+ /* Invalid object */
-+ return NULL;
-+ }
-+
-+ offset = le16_to_cpu(object->usRecordOffset)
-+ + bp->object_info_tbl_offset;
-+
-+ for (;;) {
-+ record_header = GET_IMAGE(ATOM_COMMON_RECORD_HEADER, offset);
-+
-+ if (!record_header)
-+ return NULL;
-+
-+ if (LAST_RECORD_TYPE == record_header->ucRecordType ||
-+ 0 == record_header->ucRecordSize)
-+ break;
-+
-+ if (ATOM_I2C_RECORD_TYPE == record_header->ucRecordType &&
-+ sizeof(ATOM_I2C_RECORD) <=
-+ record_header->ucRecordSize) {
-+ return (ATOM_I2C_RECORD *)record_header;
-+ }
-+
-+ offset += record_header->ucRecordSize;
-+ }
-+
-+ return NULL;
-+}
-+
-+
-+static enum bp_result get_ss_info_from_ss_info_table(
-+ struct bios_parser *bp,
-+ uint32_t id,
-+ struct spread_spectrum_info *ss_info);
-+static enum bp_result get_ss_info_from_tbl(
-+ struct bios_parser *bp,
-+ uint32_t id,
-+ struct spread_spectrum_info *ss_info);
-+/**
-+ * dal_bios_parser_get_spread_spectrum_info
-+ * Get spread spectrum information from the ASIC_InternalSS_Info(ver 2.1 or
-+ * ver 3.1) or SS_Info table from the VBIOS. Currently ASIC_InternalSS_Info
-+ * ver 2.1 can co-exist with SS_Info table. Expect ASIC_InternalSS_Info ver 3.1,
-+ * there is only one entry for each signal /ss id. However, there is
-+ * no planning of supporting multiple spread Sprectum entry for EverGreen
-+ * @param [in] this
-+ * @param [in] signal, ASSignalType to be converted to info index
-+ * @param [in] index, number of entries that match the converted info index
-+ * @param [out] ss_info, sprectrum information structure,
-+ * @return Bios parser result code
-+ */
-+enum bp_result dal_bios_parser_get_spread_spectrum_info(
-+ struct bios_parser *bp,
-+ enum as_signal_type signal,
-+ uint32_t index,
-+ struct spread_spectrum_info *ss_info)
-+{
-+ enum bp_result result = BP_RESULT_UNSUPPORTED;
-+ uint32_t clk_id_ss = 0;
-+ ATOM_COMMON_TABLE_HEADER *header;
-+ struct atom_data_revision tbl_revision;
-+
-+ if (!ss_info) /* check for bad input */
-+ return BP_RESULT_BADINPUT;
-+ /* signal translation */
-+ clk_id_ss = signal_to_ss_id(signal);
-+
-+ if (!DATA_TABLES(ASIC_InternalSS_Info))
-+ if (!index)
-+ return get_ss_info_from_ss_info_table(bp, clk_id_ss,
-+ ss_info);
-+
-+ header = GET_IMAGE(ATOM_COMMON_TABLE_HEADER,
-+ DATA_TABLES(ASIC_InternalSS_Info));
-+ get_atom_data_table_revision(header, &tbl_revision);
-+
-+ switch (tbl_revision.major) {
-+ case 2:
-+ switch (tbl_revision.minor) {
-+ case 1:
-+ /* there can not be more then one entry for Internal
-+ * SS Info table version 2.1 */
-+ if (!index)
-+ return get_ss_info_from_tbl(bp, clk_id_ss,
-+ ss_info);
-+ break;
-+ default:
-+ break;
-+ }
-+ break;
-+
-+ case 3:
-+ switch (tbl_revision.minor) {
-+ case 1:
-+ return get_ss_info_v3_1(bp, clk_id_ss, index, ss_info);
-+ default:
-+ break;
-+ }
-+ break;
-+ default:
-+ break;
-+ }
-+ /* there can not be more then one entry for SS Info table */
-+ return result;
-+}
-+
-+static enum bp_result get_ss_info_from_internal_ss_info_tbl_V2_1(
-+ struct bios_parser *bp,
-+ uint32_t id,
-+ struct spread_spectrum_info *info);
-+
-+/**
-+ * get_ss_info_from_table
-+ * Get spread sprectrum information from the ASIC_InternalSS_Info Ver 2.1 or
-+ * SS_Info table from the VBIOS
-+ * There can not be more than 1 entry for ASIC_InternalSS_Info Ver 2.1 or
-+ * SS_Info.
-+ *
-+ * @param this
-+ * @param id, spread sprectrum info index
-+ * @param pSSinfo, sprectrum information structure,
-+ * @return Bios parser result code
-+ */
-+static enum bp_result get_ss_info_from_tbl(
-+ struct bios_parser *bp,
-+ uint32_t id,
-+ struct spread_spectrum_info *ss_info)
-+{
-+ if (!ss_info) /* check for bad input, if ss_info is not NULL */
-+ return BP_RESULT_BADINPUT;
-+ /* for SS_Info table only support DP and LVDS */
-+ if (id == ASIC_INTERNAL_SS_ON_DP || id == ASIC_INTERNAL_SS_ON_LVDS)
-+ return get_ss_info_from_ss_info_table(bp, id, ss_info);
-+ else
-+ return get_ss_info_from_internal_ss_info_tbl_V2_1(bp, id,
-+ ss_info);
-+}
-+
-+/**
-+ * get_ss_info_from_internal_ss_info_tbl_V2_1
-+ * Get spread sprectrum information from the ASIC_InternalSS_Info table Ver 2.1
-+ * from the VBIOS
-+ * There will not be multiple entry for Ver 2.1
-+ *
-+ * @param id, spread sprectrum info index
-+ * @param pSSinfo, sprectrum information structure,
-+ * @return Bios parser result code
-+ */
-+static enum bp_result get_ss_info_from_internal_ss_info_tbl_V2_1(
-+ struct bios_parser *bp,
-+ uint32_t id,
-+ struct spread_spectrum_info *info)
-+{
-+ enum bp_result result = BP_RESULT_UNSUPPORTED;
-+ ATOM_ASIC_INTERNAL_SS_INFO_V2 *header;
-+ ATOM_ASIC_SS_ASSIGNMENT_V2 *tbl;
-+ uint32_t tbl_size, i;
-+
-+ if (!DATA_TABLES(ASIC_InternalSS_Info))
-+ return result;
-+
-+ header = GET_IMAGE(ATOM_ASIC_INTERNAL_SS_INFO_V2,
-+ DATA_TABLES(ASIC_InternalSS_Info));
-+
-+ dc_service_memset(info, 0, sizeof(struct spread_spectrum_info));
-+
-+ tbl_size = (le16_to_cpu(header->sHeader.usStructureSize)
-+ - sizeof(ATOM_COMMON_TABLE_HEADER))
-+ / sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
-+
-+ tbl = (ATOM_ASIC_SS_ASSIGNMENT_V2 *)
-+ &(header->asSpreadSpectrum[0]);
-+ for (i = 0; i < tbl_size; i++) {
-+ result = BP_RESULT_NORECORD;
-+
-+ if (tbl[i].ucClockIndication != (uint8_t)id)
-+ continue;
-+
-+ if (ATOM_EXTERNAL_SS_MASK
-+ & tbl[i].ucSpreadSpectrumMode) {
-+ info->type.EXTERNAL = true;
-+ }
-+ if (ATOM_SS_CENTRE_SPREAD_MODE_MASK
-+ & tbl[i].ucSpreadSpectrumMode) {
-+ info->type.CENTER_MODE = true;
-+ }
-+ info->type.STEP_AND_DELAY_INFO = false;
-+ /* convert [10KHz] into [KHz] */
-+ info->target_clock_range =
-+ le32_to_cpu(tbl[i].ulTargetClockRange) * 10;
-+ info->spread_spectrum_percentage =
-+ (uint32_t)le16_to_cpu(tbl[i].usSpreadSpectrumPercentage);
-+ info->spread_spectrum_range =
-+ (uint32_t)(le16_to_cpu(tbl[i].usSpreadRateIn10Hz) * 10);
-+ result = BP_RESULT_OK;
-+ break;
-+ }
-+
-+ return result;
-+
-+}
-+
-+/**
-+ * get_ss_info_from_ss_info_table
-+ * Get spread sprectrum information from the SS_Info table from the VBIOS
-+ * if the pointer to info is NULL, indicate the caller what to know the number
-+ * of entries that matches the id
-+ * for, the SS_Info table, there should not be more than 1 entry match.
-+ *
-+ * @param [in] id, spread sprectrum id
-+ * @param [out] pSSinfo, sprectrum information structure,
-+ * @return Bios parser result code
-+ */
-+static enum bp_result get_ss_info_from_ss_info_table(
-+ struct bios_parser *bp,
-+ uint32_t id,
-+ struct spread_spectrum_info *ss_info)
-+{
-+ enum bp_result result = BP_RESULT_UNSUPPORTED;
-+ ATOM_SPREAD_SPECTRUM_INFO *tbl;
-+ ATOM_COMMON_TABLE_HEADER *header;
-+ uint32_t table_size;
-+ uint32_t i;
-+ uint32_t id_local = SS_ID_UNKNOWN;
-+ struct atom_data_revision revision;
-+
-+ /* exist of the SS_Info table */
-+ /* check for bad input, pSSinfo can not be NULL */
-+ if (!DATA_TABLES(SS_Info) || !ss_info)
-+ return result;
-+
-+ header = GET_IMAGE(ATOM_COMMON_TABLE_HEADER, DATA_TABLES(SS_Info));
-+ get_atom_data_table_revision(header, &revision);
-+
-+ tbl = GET_IMAGE(ATOM_SPREAD_SPECTRUM_INFO, DATA_TABLES(SS_Info));
-+
-+ if (1 != revision.major || 2 > revision.minor)
-+ return result;
-+
-+ /* have to convert from Internal_SS format to SS_Info format */
-+ switch (id) {
-+ case ASIC_INTERNAL_SS_ON_DP:
-+ id_local = SS_ID_DP1;
-+ break;
-+ case ASIC_INTERNAL_SS_ON_LVDS:
-+ {
-+ struct embedded_panel_info panel_info;
-+
-+ if (dal_bios_parser_get_embedded_panel_info(bp, &panel_info)
-+ == BP_RESULT_OK)
-+ id_local = panel_info.ss_id;
-+ break;
-+ }
-+ default:
-+ break;
-+ }
-+
-+ if (id_local == SS_ID_UNKNOWN)
-+ return result;
-+
-+ table_size = (le16_to_cpu(tbl->sHeader.usStructureSize) -
-+ sizeof(ATOM_COMMON_TABLE_HEADER)) /
-+ sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT);
-+
-+ for (i = 0; i < table_size; i++) {
-+ if (id_local != (uint32_t)tbl->asSS_Info[i].ucSS_Id)
-+ continue;
-+
-+ dc_service_memset(ss_info, 0, sizeof(struct spread_spectrum_info));
-+
-+ if (ATOM_EXTERNAL_SS_MASK &
-+ tbl->asSS_Info[i].ucSpreadSpectrumType)
-+ ss_info->type.EXTERNAL = true;
-+
-+ if (ATOM_SS_CENTRE_SPREAD_MODE_MASK &
-+ tbl->asSS_Info[i].ucSpreadSpectrumType)
-+ ss_info->type.CENTER_MODE = true;
-+
-+ ss_info->type.STEP_AND_DELAY_INFO = true;
-+ ss_info->spread_spectrum_percentage =
-+ (uint32_t)le16_to_cpu(tbl->asSS_Info[i].usSpreadSpectrumPercentage);
-+ ss_info->step_and_delay_info.step = tbl->asSS_Info[i].ucSS_Step;
-+ ss_info->step_and_delay_info.delay =
-+ tbl->asSS_Info[i].ucSS_Delay;
-+ ss_info->step_and_delay_info.recommended_ref_div =
-+ tbl->asSS_Info[i].ucRecommendedRef_Div;
-+ ss_info->spread_spectrum_range =
-+ (uint32_t)tbl->asSS_Info[i].ucSS_Range * 10000;
-+
-+ /* there will be only one entry for each display type in SS_info
-+ * table */
-+ result = BP_RESULT_OK;
-+ break;
-+ }
-+
-+ return result;
-+}
-+static enum bp_result get_embedded_panel_info_v1_2(
-+ struct bios_parser *bp,
-+ struct embedded_panel_info *info);
-+static enum bp_result get_embedded_panel_info_v1_3(
-+ struct bios_parser *bp,
-+ struct embedded_panel_info *info);
-+
-+enum bp_result dal_bios_parser_get_embedded_panel_info(
-+ struct bios_parser *bp,
-+ struct embedded_panel_info *info)
-+{
-+ ATOM_COMMON_TABLE_HEADER *hdr;
-+
-+ if (!DATA_TABLES(LCD_Info))
-+ return BP_RESULT_FAILURE;
-+
-+ hdr = GET_IMAGE(ATOM_COMMON_TABLE_HEADER, DATA_TABLES(LCD_Info));
-+
-+ if (!hdr)
-+ return BP_RESULT_BADBIOSTABLE;
-+
-+ switch (hdr->ucTableFormatRevision) {
-+ case 1:
-+ switch (hdr->ucTableContentRevision) {
-+ case 0:
-+ case 1:
-+ case 2:
-+ return get_embedded_panel_info_v1_2(bp, info);
-+ case 3:
-+ return get_embedded_panel_info_v1_3(bp, info);
-+ default:
-+ break;
-+ }
-+ default:
-+ break;
-+ }
-+
-+ return BP_RESULT_FAILURE;
-+}
-+
-+static enum bp_result get_embedded_panel_info_v1_2(
-+ struct bios_parser *bp,
-+ struct embedded_panel_info *info)
-+{
-+ ATOM_LVDS_INFO_V12 *lvds;
-+
-+ if (!info)
-+ return BP_RESULT_BADINPUT;
-+
-+ if (!DATA_TABLES(LVDS_Info))
-+ return BP_RESULT_UNSUPPORTED;
-+
-+ lvds =
-+ GET_IMAGE(ATOM_LVDS_INFO_V12, DATA_TABLES(LVDS_Info));
-+
-+ if (!lvds)
-+ return BP_RESULT_BADBIOSTABLE;
-+
-+ if (1 != lvds->sHeader.ucTableFormatRevision
-+ || 2 > lvds->sHeader.ucTableContentRevision)
-+ return BP_RESULT_UNSUPPORTED;
-+
-+ dc_service_memset(info, 0, sizeof(struct embedded_panel_info));
-+
-+ /* We need to convert from 10KHz units into KHz units*/
-+ info->lcd_timing.pixel_clk =
-+ le16_to_cpu(lvds->sLCDTiming.usPixClk) * 10;
-+ /* usHActive does not include borders, according to VBIOS team*/
-+ info->lcd_timing.horizontal_addressable =
-+ le16_to_cpu(lvds->sLCDTiming.usHActive);
-+ /* usHBlanking_Time includes borders, so we should really be subtracting
-+ * borders duing this translation, but LVDS generally*/
-+ /* doesn't have borders, so we should be okay leaving this as is for
-+ * now. May need to revisit if we ever have LVDS with borders*/
-+ info->lcd_timing.horizontal_blanking_time =
-+ le16_to_cpu(lvds->sLCDTiming.usHBlanking_Time);
-+ /* usVActive does not include borders, according to VBIOS team*/
-+ info->lcd_timing.vertical_addressable =
-+ le16_to_cpu(lvds->sLCDTiming.usVActive);
-+ /* usVBlanking_Time includes borders, so we should really be subtracting
-+ * borders duing this translation, but LVDS generally*/
-+ /* doesn't have borders, so we should be okay leaving this as is for
-+ * now. May need to revisit if we ever have LVDS with borders*/
-+ info->lcd_timing.vertical_blanking_time =
-+ le16_to_cpu(lvds->sLCDTiming.usVBlanking_Time);
-+ info->lcd_timing.horizontal_sync_offset =
-+ le16_to_cpu(lvds->sLCDTiming.usHSyncOffset);
-+ info->lcd_timing.horizontal_sync_width =
-+ le16_to_cpu(lvds->sLCDTiming.usHSyncWidth);
-+ info->lcd_timing.vertical_sync_offset =
-+ le16_to_cpu(lvds->sLCDTiming.usVSyncOffset);
-+ info->lcd_timing.vertical_sync_width =
-+ le16_to_cpu(lvds->sLCDTiming.usVSyncWidth);
-+ info->lcd_timing.horizontal_border = lvds->sLCDTiming.ucHBorder;
-+ info->lcd_timing.vertical_border = lvds->sLCDTiming.ucVBorder;
-+ info->lcd_timing.misc_info.HORIZONTAL_CUT_OFF =
-+ lvds->sLCDTiming.susModeMiscInfo.sbfAccess.HorizontalCutOff;
-+ info->lcd_timing.misc_info.H_SYNC_POLARITY =
-+ ~(uint32_t)
-+ lvds->sLCDTiming.susModeMiscInfo.sbfAccess.HSyncPolarity;
-+ info->lcd_timing.misc_info.V_SYNC_POLARITY =
-+ ~(uint32_t)
-+ lvds->sLCDTiming.susModeMiscInfo.sbfAccess.VSyncPolarity;
-+ info->lcd_timing.misc_info.VERTICAL_CUT_OFF =
-+ lvds->sLCDTiming.susModeMiscInfo.sbfAccess.VerticalCutOff;
-+ info->lcd_timing.misc_info.H_REPLICATION_BY2 =
-+ lvds->sLCDTiming.susModeMiscInfo.sbfAccess.H_ReplicationBy2;
-+ info->lcd_timing.misc_info.V_REPLICATION_BY2 =
-+ lvds->sLCDTiming.susModeMiscInfo.sbfAccess.V_ReplicationBy2;
-+ info->lcd_timing.misc_info.COMPOSITE_SYNC =
-+ lvds->sLCDTiming.susModeMiscInfo.sbfAccess.CompositeSync;
-+ info->lcd_timing.misc_info.INTERLACE =
-+ lvds->sLCDTiming.susModeMiscInfo.sbfAccess.Interlace;
-+ info->lcd_timing.misc_info.DOUBLE_CLOCK =
-+ lvds->sLCDTiming.susModeMiscInfo.sbfAccess.DoubleClock;
-+ info->ss_id = lvds->ucSS_Id;
-+
-+ {
-+ uint8_t rr = le16_to_cpu(lvds->usSupportedRefreshRate);
-+ /* Get minimum supported refresh rate*/
-+ if (SUPPORTED_LCD_REFRESHRATE_30Hz & rr)
-+ info->supported_rr.REFRESH_RATE_30HZ = 1;
-+ else if (SUPPORTED_LCD_REFRESHRATE_40Hz & rr)
-+ info->supported_rr.REFRESH_RATE_40HZ = 1;
-+ else if (SUPPORTED_LCD_REFRESHRATE_48Hz & rr)
-+ info->supported_rr.REFRESH_RATE_48HZ = 1;
-+ else if (SUPPORTED_LCD_REFRESHRATE_50Hz & rr)
-+ info->supported_rr.REFRESH_RATE_50HZ = 1;
-+ else if (SUPPORTED_LCD_REFRESHRATE_60Hz & rr)
-+ info->supported_rr.REFRESH_RATE_60HZ = 1;
-+ }
-+
-+ /*Drr panel support can be reported by VBIOS*/
-+ if (LCDPANEL_CAP_DRR_SUPPORTED
-+ & lvds->ucLCDPanel_SpecialHandlingCap)
-+ info->drr_enabled = 1;
-+
-+ if (ATOM_PANEL_MISC_DUAL & lvds->ucLVDS_Misc)
-+ info->lcd_timing.misc_info.DOUBLE_CLOCK = true;
-+
-+ if (ATOM_PANEL_MISC_888RGB & lvds->ucLVDS_Misc)
-+ info->lcd_timing.misc_info.RGB888 = true;
-+
-+ info->lcd_timing.misc_info.GREY_LEVEL =
-+ (uint32_t) (ATOM_PANEL_MISC_GREY_LEVEL &
-+ lvds->ucLVDS_Misc) >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT;
-+
-+ if (ATOM_PANEL_MISC_SPATIAL & lvds->ucLVDS_Misc)
-+ info->lcd_timing.misc_info.SPATIAL = true;
-+
-+ if (ATOM_PANEL_MISC_TEMPORAL & lvds->ucLVDS_Misc)
-+ info->lcd_timing.misc_info.TEMPORAL = true;
-+
-+ if (ATOM_PANEL_MISC_API_ENABLED & lvds->ucLVDS_Misc)
-+ info->lcd_timing.misc_info.API_ENABLED = true;
-+
-+ return BP_RESULT_OK;
-+}
-+
-+static enum bp_result get_embedded_panel_info_v1_3(
-+ struct bios_parser *bp,
-+ struct embedded_panel_info *info)
-+{
-+ ATOM_LCD_INFO_V13 *lvds;
-+
-+ if (!info)
-+ return BP_RESULT_BADINPUT;
-+
-+ if (!DATA_TABLES(LCD_Info))
-+ return BP_RESULT_UNSUPPORTED;
-+
-+ lvds = GET_IMAGE(ATOM_LCD_INFO_V13, DATA_TABLES(LCD_Info));
-+
-+ if (!lvds)
-+ return BP_RESULT_BADBIOSTABLE;
-+
-+ if (!((1 == lvds->sHeader.ucTableFormatRevision)
-+ && (3 <= lvds->sHeader.ucTableContentRevision)))
-+ return BP_RESULT_UNSUPPORTED;
-+
-+ dc_service_memset(info, 0, sizeof(struct embedded_panel_info));
-+
-+ /* We need to convert from 10KHz units into KHz units */
-+ info->lcd_timing.pixel_clk =
-+ le16_to_cpu(lvds->sLCDTiming.usPixClk) * 10;
-+ /* usHActive does not include borders, according to VBIOS team */
-+ info->lcd_timing.horizontal_addressable =
-+ le16_to_cpu(lvds->sLCDTiming.usHActive);
-+ /* usHBlanking_Time includes borders, so we should really be subtracting
-+ * borders duing this translation, but LVDS generally*/
-+ /* doesn't have borders, so we should be okay leaving this as is for
-+ * now. May need to revisit if we ever have LVDS with borders*/
-+ info->lcd_timing.horizontal_blanking_time =
-+ le16_to_cpu(lvds->sLCDTiming.usHBlanking_Time);
-+ /* usVActive does not include borders, according to VBIOS team*/
-+ info->lcd_timing.vertical_addressable =
-+ le16_to_cpu(lvds->sLCDTiming.usVActive);
-+ /* usVBlanking_Time includes borders, so we should really be subtracting
-+ * borders duing this translation, but LVDS generally*/
-+ /* doesn't have borders, so we should be okay leaving this as is for
-+ * now. May need to revisit if we ever have LVDS with borders*/
-+ info->lcd_timing.vertical_blanking_time =
-+ le16_to_cpu(lvds->sLCDTiming.usVBlanking_Time);
-+ info->lcd_timing.horizontal_sync_offset =
-+ le16_to_cpu(lvds->sLCDTiming.usHSyncOffset);
-+ info->lcd_timing.horizontal_sync_width =
-+ le16_to_cpu(lvds->sLCDTiming.usHSyncWidth);
-+ info->lcd_timing.vertical_sync_offset =
-+ le16_to_cpu(lvds->sLCDTiming.usVSyncOffset);
-+ info->lcd_timing.vertical_sync_width =
-+ le16_to_cpu(lvds->sLCDTiming.usVSyncWidth);
-+ info->lcd_timing.horizontal_border = lvds->sLCDTiming.ucHBorder;
-+ info->lcd_timing.vertical_border = lvds->sLCDTiming.ucVBorder;
-+ info->lcd_timing.misc_info.HORIZONTAL_CUT_OFF =
-+ lvds->sLCDTiming.susModeMiscInfo.sbfAccess.HorizontalCutOff;
-+ info->lcd_timing.misc_info.H_SYNC_POLARITY =
-+ ~(uint32_t)
-+ lvds->sLCDTiming.susModeMiscInfo.sbfAccess.HSyncPolarity;
-+ info->lcd_timing.misc_info.V_SYNC_POLARITY =
-+ ~(uint32_t)
-+ lvds->sLCDTiming.susModeMiscInfo.sbfAccess.VSyncPolarity;
-+ info->lcd_timing.misc_info.VERTICAL_CUT_OFF =
-+ lvds->sLCDTiming.susModeMiscInfo.sbfAccess.VerticalCutOff;
-+ info->lcd_timing.misc_info.H_REPLICATION_BY2 =
-+ lvds->sLCDTiming.susModeMiscInfo.sbfAccess.H_ReplicationBy2;
-+ info->lcd_timing.misc_info.V_REPLICATION_BY2 =
-+ lvds->sLCDTiming.susModeMiscInfo.sbfAccess.V_ReplicationBy2;
-+ info->lcd_timing.misc_info.COMPOSITE_SYNC =
-+ lvds->sLCDTiming.susModeMiscInfo.sbfAccess.CompositeSync;
-+ info->lcd_timing.misc_info.INTERLACE =
-+ lvds->sLCDTiming.susModeMiscInfo.sbfAccess.Interlace;
-+ info->lcd_timing.misc_info.DOUBLE_CLOCK =
-+ lvds->sLCDTiming.susModeMiscInfo.sbfAccess.DoubleClock;
-+ info->ss_id = lvds->ucSS_Id;
-+
-+ /* Drr panel support can be reported by VBIOS*/
-+ if (LCDPANEL_CAP_V13_DRR_SUPPORTED
-+ & lvds->ucLCDPanel_SpecialHandlingCap)
-+ info->drr_enabled = 1;
-+
-+ /* Get supported refresh rate*/
-+ if (info->drr_enabled == 1) {
-+ uint8_t min_rr =
-+ lvds->sRefreshRateSupport.ucMinRefreshRateForDRR;
-+ uint8_t rr = lvds->sRefreshRateSupport.ucSupportedRefreshRate;
-+
-+ if (min_rr != 0) {
-+ if (SUPPORTED_LCD_REFRESHRATE_30Hz & min_rr)
-+ info->supported_rr.REFRESH_RATE_30HZ = 1;
-+ else if (SUPPORTED_LCD_REFRESHRATE_40Hz & min_rr)
-+ info->supported_rr.REFRESH_RATE_40HZ = 1;
-+ else if (SUPPORTED_LCD_REFRESHRATE_48Hz & min_rr)
-+ info->supported_rr.REFRESH_RATE_48HZ = 1;
-+ else if (SUPPORTED_LCD_REFRESHRATE_50Hz & min_rr)
-+ info->supported_rr.REFRESH_RATE_50HZ = 1;
-+ else if (SUPPORTED_LCD_REFRESHRATE_60Hz & min_rr)
-+ info->supported_rr.REFRESH_RATE_60HZ = 1;
-+ } else {
-+ if (SUPPORTED_LCD_REFRESHRATE_30Hz & rr)
-+ info->supported_rr.REFRESH_RATE_30HZ = 1;
-+ else if (SUPPORTED_LCD_REFRESHRATE_40Hz & rr)
-+ info->supported_rr.REFRESH_RATE_40HZ = 1;
-+ else if (SUPPORTED_LCD_REFRESHRATE_48Hz & rr)
-+ info->supported_rr.REFRESH_RATE_48HZ = 1;
-+ else if (SUPPORTED_LCD_REFRESHRATE_50Hz & rr)
-+ info->supported_rr.REFRESH_RATE_50HZ = 1;
-+ else if (SUPPORTED_LCD_REFRESHRATE_60Hz & rr)
-+ info->supported_rr.REFRESH_RATE_60HZ = 1;
-+ }
-+ }
-+
-+ if (ATOM_PANEL_MISC_V13_DUAL & lvds->ucLCD_Misc)
-+ info->lcd_timing.misc_info.DOUBLE_CLOCK = true;
-+
-+ if (ATOM_PANEL_MISC_V13_8BIT_PER_COLOR & lvds->ucLCD_Misc)
-+ info->lcd_timing.misc_info.RGB888 = true;
-+
-+ info->lcd_timing.misc_info.GREY_LEVEL =
-+ (uint32_t) (ATOM_PANEL_MISC_V13_GREY_LEVEL &
-+ lvds->ucLCD_Misc) >> ATOM_PANEL_MISC_V13_GREY_LEVEL_SHIFT;
-+
-+ return BP_RESULT_OK;
-+}
-+
-+/**
-+ * dal_bios_parser_get_encoder_cap_info
-+ *
-+ * @brief
-+ * Get encoder capability information of input object id
-+ *
-+ * @param object_id, Object id
-+ * @param object_id, encoder cap information structure
-+ *
-+ * @return Bios parser result code
-+ *
-+ */
-+enum bp_result dal_bios_parser_get_encoder_cap_info(
-+ struct bios_parser *bp,
-+ struct graphics_object_id object_id,
-+ struct bp_encoder_cap_info *info)
-+{
-+ ATOM_OBJECT *object;
-+ ATOM_ENCODER_CAP_RECORD *record = NULL;
-+
-+ if (!info)
-+ return BP_RESULT_BADINPUT;
-+
-+ object = get_bios_object(bp, object_id);
-+
-+ if (!object)
-+ return BP_RESULT_BADINPUT;
-+
-+ record = get_encoder_cap_record(bp, object);
-+ if (!record)
-+ return BP_RESULT_NORECORD;
-+
-+ info->DP_HBR2_CAP = record->usHBR2Cap;
-+ info->DP_HBR2_EN = record->usHBR2En;
-+ return BP_RESULT_OK;
-+}
-+
-+/**
-+ * get_encoder_cap_record
-+ *
-+ * @brief
-+ * Get encoder cap record for the object
-+ *
-+ * @param object, ATOM object
-+ *
-+ * @return atom encoder cap record
-+ *
-+ * @note
-+ * search all records to find the ATOM_ENCODER_CAP_RECORD record
-+ */
-+static ATOM_ENCODER_CAP_RECORD *get_encoder_cap_record(
-+ struct bios_parser *bp,
-+ ATOM_OBJECT *object)
-+{
-+ ATOM_COMMON_RECORD_HEADER *header;
-+ uint32_t offset;
-+
-+ if (!object) {
-+ BREAK_TO_DEBUGGER(); /* Invalid object */
-+ return NULL;
-+ }
-+
-+ offset = le16_to_cpu(object->usRecordOffset)
-+ + bp->object_info_tbl_offset;
-+
-+ for (;;) {
-+ header = GET_IMAGE(ATOM_COMMON_RECORD_HEADER, offset);
-+
-+ if (!header)
-+ return NULL;
-+
-+ offset += header->ucRecordSize;
-+
-+ if (LAST_RECORD_TYPE == header->ucRecordType ||
-+ !header->ucRecordSize)
-+ break;
-+
-+ if (ATOM_ENCODER_CAP_RECORD_TYPE != header->ucRecordType)
-+ continue;
-+
-+ if (sizeof(ATOM_ENCODER_CAP_RECORD) <= header->ucRecordSize)
-+ return (ATOM_ENCODER_CAP_RECORD *)header;
-+ }
-+
-+ return NULL;
-+}
-+
-+/**
-+ * dal_bios_parser_get_din_connector_info
-+ * @brief
-+ * Get GPIO record for the DIN connector, this GPIO tells whether there is a
-+ * CV dumb dongle
-+ * attached to the DIN connector to perform load detection for the the
-+ * appropriate signal
-+ *
-+ * @param id - DIN connector object id
-+ * @param info - GPIO record infor
-+ * @return Bios parser result code
-+ */
-+enum bp_result dal_bios_parser_get_din_connector_info(
-+ struct bios_parser *bp,
-+ struct graphics_object_id id,
-+ struct din_connector_info *info)
-+{
-+ ATOM_COMMON_RECORD_HEADER *header;
-+ ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD *record = NULL;
-+ ATOM_OBJECT *object;
-+ uint32_t offset;
-+ enum bp_result result = BP_RESULT_NORECORD;
-+
-+ /* no output buffer provided */
-+ if (!info) {
-+ BREAK_TO_DEBUGGER(); /* Invalid output buffer */
-+ return BP_RESULT_BADINPUT;
-+ }
-+
-+ object = get_bios_object(bp, id);
-+ if (!object) {
-+ BREAK_TO_DEBUGGER(); /* Invalid object id */;
-+ return BP_RESULT_BADINPUT;
-+ }
-+
-+ offset = le16_to_cpu(object->usRecordOffset)
-+ + bp->object_info_tbl_offset;
-+
-+ for (;;) {
-+ header = GET_IMAGE(ATOM_COMMON_RECORD_HEADER, offset);
-+
-+ if (!header) {
-+ result = BP_RESULT_BADBIOSTABLE;
-+ break;
-+ }
-+
-+ offset += header->ucRecordSize;
-+
-+ /* get out of the loop if no more records */
-+ if (LAST_RECORD_TYPE == header->ucRecordType ||
-+ !header->ucRecordSize)
-+ break;
-+
-+ if (ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD_TYPE !=
-+ header->ucRecordType)
-+ continue;
-+
-+ if (sizeof(ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD)
-+ > header->ucRecordSize)
-+ continue;
-+
-+ record = (ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD *)header;
-+ result = BP_RESULT_OK;
-+ break;
-+ }
-+
-+ /* return if the record not found */
-+ if (result != BP_RESULT_OK)
-+ return result;
-+
-+ info->gpio_id = record->ucGPIOID;
-+ info->gpio_tv_active_state = (record->ucTVActiveState != 0);
-+
-+ return result;
-+}
-+
-+static uint32_t get_ss_entry_number(
-+ struct bios_parser *bp,
-+ uint32_t id);
-+static uint32_t get_ss_entry_number_from_internal_ss_info_tbl_v2_1(
-+ struct bios_parser *bp,
-+ uint32_t id);
-+static uint32_t get_ss_entry_number_from_internal_ss_info_tbl_V3_1(
-+ struct bios_parser *bp,
-+ uint32_t id);
-+static uint32_t get_ss_entry_number_from_ss_info_tbl(
-+ struct bios_parser *bp,
-+ uint32_t id);
-+
-+/**
-+ * BiosParserObject::GetNumberofSpreadSpectrumEntry
-+ * Get Number of SpreadSpectrum Entry from the ASIC_InternalSS_Info table from
-+ * the VBIOS that match the SSid (to be converted from signal)
-+ *
-+ * @param[in] signal, ASSignalType to be converted to SSid
-+ * @return number of SS Entry that match the signal
-+ */
-+uint32_t dal_bios_parser_get_ss_entry_number(
-+ struct bios_parser *bp,
-+ enum as_signal_type signal)
-+{
-+ uint32_t ss_id = 0;
-+ ATOM_COMMON_TABLE_HEADER *header;
-+ struct atom_data_revision revision;
-+
-+ ss_id = signal_to_ss_id(signal);
-+
-+ if (!DATA_TABLES(ASIC_InternalSS_Info))
-+ return get_ss_entry_number_from_ss_info_tbl(bp, ss_id);
-+
-+ header = GET_IMAGE(ATOM_COMMON_TABLE_HEADER,
-+ DATA_TABLES(ASIC_InternalSS_Info));
-+ get_atom_data_table_revision(header, &revision);
-+
-+ switch (revision.major) {
-+ case 2:
-+ switch (revision.minor) {
-+ case 1:
-+ return get_ss_entry_number(bp, ss_id);
-+ default:
-+ break;
-+ }
-+ break;
-+ case 3:
-+ switch (revision.minor) {
-+ case 1:
-+ return
-+ get_ss_entry_number_from_internal_ss_info_tbl_V3_1(
-+ bp, ss_id);
-+ default:
-+ break;
-+ }
-+ break;
-+ default:
-+ break;
-+ }
-+
-+ return 0;
-+}
-+
-+
-+/**
-+ * get_ss_entry_number_from_ss_info_tbl
-+ * Get Number of spread spectrum entry from the SS_Info table from the VBIOS.
-+ *
-+ * @note There can only be one entry for each id for SS_Info Table
-+ *
-+ * @param [in] id, spread spectrum id
-+ * @return number of SS Entry that match the id
-+ */
-+static uint32_t get_ss_entry_number_from_ss_info_tbl(
-+ struct bios_parser *bp,
-+ uint32_t id)
-+{
-+ ATOM_SPREAD_SPECTRUM_INFO *tbl;
-+ ATOM_COMMON_TABLE_HEADER *header;
-+ uint32_t table_size;
-+ uint32_t i;
-+ uint32_t number = 0;
-+ uint32_t id_local = SS_ID_UNKNOWN;
-+ struct atom_data_revision revision;
-+
-+ /* SS_Info table exist */
-+ if (!DATA_TABLES(SS_Info))
-+ return number;
-+
-+ header = GET_IMAGE(ATOM_COMMON_TABLE_HEADER,
-+ DATA_TABLES(SS_Info));
-+ get_atom_data_table_revision(header, &revision);
-+
-+ tbl = GET_IMAGE(ATOM_SPREAD_SPECTRUM_INFO,
-+ DATA_TABLES(SS_Info));
-+
-+ if (1 != revision.major || 2 > revision.minor)
-+ return number;
-+
-+ /* have to convert from Internal_SS format to SS_Info format */
-+ switch (id) {
-+ case ASIC_INTERNAL_SS_ON_DP:
-+ id_local = SS_ID_DP1;
-+ break;
-+ case ASIC_INTERNAL_SS_ON_LVDS: {
-+ struct embedded_panel_info panel_info;
-+
-+ if (dal_bios_parser_get_embedded_panel_info(bp, &panel_info)
-+ == BP_RESULT_OK)
-+ id_local = panel_info.ss_id;
-+ break;
-+ }
-+ default:
-+ break;
-+ }
-+
-+ if (id_local == SS_ID_UNKNOWN)
-+ return number;
-+
-+ table_size = (le16_to_cpu(tbl->sHeader.usStructureSize) -
-+ sizeof(ATOM_COMMON_TABLE_HEADER)) /
-+ sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT);
-+
-+ for (i = 0; i < table_size; i++)
-+ if (id_local == (uint32_t)tbl->asSS_Info[i].ucSS_Id) {
-+ number = 1;
-+ break;
-+ }
-+
-+ return number;
-+}
-+
-+
-+/**
-+ * get_ss_entry_number
-+ * Get spread sprectrum information from the ASIC_InternalSS_Info Ver 2.1 or
-+ * SS_Info table from the VBIOS
-+ * There can not be more than 1 entry for ASIC_InternalSS_Info Ver 2.1 or
-+ * SS_Info.
-+ *
-+ * @param id, spread sprectrum info index
-+ * @return Bios parser result code
-+ */
-+static uint32_t get_ss_entry_number(struct bios_parser *bp, uint32_t id)
-+{
-+ if (id == ASIC_INTERNAL_SS_ON_DP || id == ASIC_INTERNAL_SS_ON_LVDS)
-+ return get_ss_entry_number_from_ss_info_tbl(bp, id);
-+
-+ return get_ss_entry_number_from_internal_ss_info_tbl_v2_1(bp, id);
-+}
-+
-+/**
-+ * get_ss_entry_number_from_internal_ss_info_tbl_v2_1
-+ * Get NUmber of spread sprectrum entry from the ASIC_InternalSS_Info table
-+ * Ver 2.1 from the VBIOS
-+ * There will not be multiple entry for Ver 2.1
-+ *
-+ * @param id, spread sprectrum info index
-+ * @return number of SS Entry that match the id
-+ */
-+static uint32_t get_ss_entry_number_from_internal_ss_info_tbl_v2_1(
-+ struct bios_parser *bp,
-+ uint32_t id)
-+{
-+ ATOM_ASIC_INTERNAL_SS_INFO_V2 *header_include;
-+ ATOM_ASIC_SS_ASSIGNMENT_V2 *tbl;
-+ uint32_t size;
-+ uint32_t i;
-+
-+ if (!DATA_TABLES(ASIC_InternalSS_Info))
-+ return 0;
-+
-+ header_include = GET_IMAGE(ATOM_ASIC_INTERNAL_SS_INFO_V2,
-+ DATA_TABLES(ASIC_InternalSS_Info));
-+
-+ size = (le16_to_cpu(header_include->sHeader.usStructureSize)
-+ - sizeof(ATOM_COMMON_TABLE_HEADER))
-+ / sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
-+
-+ tbl = (ATOM_ASIC_SS_ASSIGNMENT_V2 *)
-+ &header_include->asSpreadSpectrum[0];
-+ for (i = 0; i < size; i++)
-+ if (tbl[i].ucClockIndication == (uint8_t)id)
-+ return 1;
-+
-+ return 0;
-+}
-+/**
-+ * get_ss_entry_number_from_internal_ss_info_table_V3_1
-+ * Get Number of SpreadSpectrum Entry from the ASIC_InternalSS_Info table of
-+ * the VBIOS that matches id
-+ *
-+ * @param[in] id, spread sprectrum id
-+ * @return number of SS Entry that match the id
-+ */
-+static uint32_t get_ss_entry_number_from_internal_ss_info_tbl_V3_1(
-+ struct bios_parser *bp,
-+ uint32_t id)
-+{
-+ uint32_t number = 0;
-+ ATOM_ASIC_INTERNAL_SS_INFO_V3 *header_include;
-+ ATOM_ASIC_SS_ASSIGNMENT_V3 *tbl;
-+ uint32_t size;
-+ uint32_t i;
-+
-+ if (!DATA_TABLES(ASIC_InternalSS_Info))
-+ return number;
-+
-+ header_include = GET_IMAGE(ATOM_ASIC_INTERNAL_SS_INFO_V3,
-+ DATA_TABLES(ASIC_InternalSS_Info));
-+ size = (le16_to_cpu(header_include->sHeader.usStructureSize) -
-+ sizeof(ATOM_COMMON_TABLE_HEADER)) /
-+ sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
-+
-+ tbl = (ATOM_ASIC_SS_ASSIGNMENT_V3 *)
-+ &header_include->asSpreadSpectrum[0];
-+
-+ for (i = 0; i < size; i++)
-+ if (tbl[i].ucClockIndication == (uint8_t)id)
-+ number++;
-+
-+ return number;
-+}
-+
-+static ATOM_FAKE_EDID_PATCH_RECORD *get_faked_edid_record(
-+ struct bios_parser *bp)
-+{
-+ uint32_t size;
-+ uint8_t *record;
-+ ATOM_LVDS_INFO_V12 *info;
-+
-+ if (!DATA_TABLES(LVDS_Info))
-+ return NULL;
-+
-+ info = GET_IMAGE(ATOM_LVDS_INFO_V12, DATA_TABLES(LVDS_Info));
-+
-+ if (!info)
-+ return NULL;
-+
-+ if (1 != info->sHeader.ucTableFormatRevision
-+ || 2 > info->sHeader.ucTableContentRevision)
-+ return NULL;
-+
-+ if (!le16_to_cpu(info->usExtInfoTableOffset))
-+ return NULL;
-+
-+ record = GET_IMAGE(uint8_t, DATA_TABLES(LVDS_Info)
-+ + le16_to_cpu(info->usExtInfoTableOffset));
-+
-+ if (!record)
-+ return NULL;
-+
-+ for (;;) {
-+ if (ATOM_RECORD_END_TYPE == *record)
-+ return NULL;
-+
-+ if (LCD_FAKE_EDID_PATCH_RECORD_TYPE == *record)
-+ break;
-+
-+ size = get_record_size(record);
-+
-+ if (!size)
-+ return NULL;
-+
-+ record += size;
-+ }
-+
-+ return (ATOM_FAKE_EDID_PATCH_RECORD *)record;
-+}
-+
-+enum bp_result dal_bios_parser_get_faked_edid_len(
-+ struct bios_parser *bp,
-+ uint32_t *len)
-+{
-+ ATOM_FAKE_EDID_PATCH_RECORD *edid_record = get_faked_edid_record(bp);
-+
-+ if (!edid_record)
-+ return BP_RESULT_NORECORD;
-+
-+ *len = get_edid_size(edid_record);
-+
-+ return BP_RESULT_OK;
-+}
-+
-+enum bp_result dal_bios_parser_get_faked_edid_buf(
-+ struct bios_parser *bp,
-+ uint8_t *buff,
-+ uint32_t len)
-+{
-+ ATOM_FAKE_EDID_PATCH_RECORD *edid_record = get_faked_edid_record(bp);
-+ uint32_t edid_size;
-+
-+ if (!edid_record)
-+ return BP_RESULT_NORECORD;
-+
-+ edid_size = get_edid_size(edid_record);
-+
-+ if (len < edid_size)
-+ return BP_RESULT_BADINPUT; /* buffer not big enough to fill */
-+
-+ dc_service_memmove(buff, &edid_record->ucFakeEDIDString, edid_size);
-+
-+ return BP_RESULT_OK;
-+}
-+
-+/**
-+ * dal_bios_parser_get_gpio_pin_info
-+ * Get GpioPin information of input gpio id
-+ *
-+ * @param gpio_id, GPIO ID
-+ * @param info, GpioPin information structure
-+ * @return Bios parser result code
-+ * @note
-+ * to get the GPIO PIN INFO, we need:
-+ * 1. get the GPIO_ID from other object table, see GetHPDInfo()
-+ * 2. in DATA_TABLE.GPIO_Pin_LUT, search all records, to get the registerA
-+ * offset/mask
-+ */
-+enum bp_result dal_bios_parser_get_gpio_pin_info(
-+ struct bios_parser *bp,
-+ uint32_t gpio_id,
-+ struct gpio_pin_info *info)
-+{
-+ ATOM_GPIO_PIN_LUT *header;
-+ uint32_t count = 0;
-+ uint32_t i = 0;
-+
-+ if (!DATA_TABLES(GPIO_Pin_LUT))
-+ return BP_RESULT_BADBIOSTABLE;
-+
-+ header = GET_IMAGE(ATOM_GPIO_PIN_LUT, DATA_TABLES(GPIO_Pin_LUT));
-+ if (!header)
-+ return BP_RESULT_BADBIOSTABLE;
-+
-+ if (sizeof(ATOM_COMMON_TABLE_HEADER) + sizeof(ATOM_GPIO_PIN_LUT)
-+ > le16_to_cpu(header->sHeader.usStructureSize))
-+ return BP_RESULT_BADBIOSTABLE;
-+
-+ if (1 != header->sHeader.ucTableContentRevision)
-+ return BP_RESULT_UNSUPPORTED;
-+
-+ count = (le16_to_cpu(header->sHeader.usStructureSize)
-+ - sizeof(ATOM_COMMON_TABLE_HEADER))
-+ / sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
-+ for (i = 0; i < count; ++i) {
-+ if (header->asGPIO_Pin[i].ucGPIO_ID != gpio_id)
-+ continue;
-+
-+ info->offset =
-+ (uint32_t) le16_to_cpu(header->asGPIO_Pin[i].usGpioPin_AIndex);
-+ info->offset_y = info->offset + 2;
-+ info->offset_en = info->offset + 1;
-+ info->offset_mask = info->offset - 1;
-+
-+ info->mask = (uint32_t) (1 <<
-+ header->asGPIO_Pin[i].ucGpioPinBitShift);
-+ info->mask_y = info->mask + 2;
-+ info->mask_en = info->mask + 1;
-+ info->mask_mask = info->mask - 1;
-+
-+ return BP_RESULT_OK;
-+ }
-+
-+ return BP_RESULT_NORECORD;
-+}
-+
-+/**
-+ * BiosParserObject::EnumEmbeddedPanelPatchMode
-+ * Get embedded panel patch mode
-+ *
-+ * @param index, mode index
-+ * @param info, embedded panel patch mode structure
-+ * @return Bios parser result code
-+ */
-+enum bp_result dal_bios_parser_enum_embedded_panel_patch_mode(
-+ struct bios_parser *bp,
-+ uint32_t index,
-+ struct embedded_panel_patch_mode *mode)
-+{
-+ uint32_t record_size;
-+ uint32_t record_index;
-+ uint8_t *record;
-+ ATOM_LVDS_INFO_V12 *info;
-+ ATOM_PATCH_RECORD_MODE *mode_record;
-+ ATOM_MASTER_LIST_OF_DATA_TABLES *list_of_tables;
-+
-+ if (!mode)
-+ return BP_RESULT_BADINPUT;
-+
-+ list_of_tables = &bp->master_data_tbl->ListOfDataTables;
-+ if (!list_of_tables->LVDS_Info)
-+ return BP_RESULT_UNSUPPORTED;
-+
-+ info = GET_IMAGE(ATOM_LVDS_INFO_V12, list_of_tables->LVDS_Info);
-+
-+ if (!info)
-+ return BP_RESULT_BADBIOSTABLE;
-+
-+ if (1 != info->sHeader.ucTableFormatRevision
-+ || 2 > info->sHeader.ucTableContentRevision)
-+ return BP_RESULT_UNSUPPORTED;
-+
-+ if (!le16_to_cpu(info->usExtInfoTableOffset))
-+ return BP_RESULT_UNSUPPORTED;
-+
-+ record = GET_IMAGE(uint8_t, list_of_tables->LVDS_Info +
-+ le16_to_cpu(info->usExtInfoTableOffset));
-+
-+ if (!record)
-+ return BP_RESULT_BADBIOSTABLE;
-+
-+ for (record_index = 0;;) {
-+ if (ATOM_RECORD_END_TYPE == *record)
-+ return BP_RESULT_NORECORD;
-+
-+ if (LCD_MODE_PATCH_RECORD_MODE_TYPE == *record) {
-+ if (record_index == index)
-+ break;
-+ record_index++;
-+ }
-+
-+ record_size = get_record_size(record);
-+
-+ if (!record_size)
-+ return BP_RESULT_NORECORD;
-+
-+ record += record_size;
-+ }
-+
-+ mode_record = (ATOM_PATCH_RECORD_MODE *) record;
-+
-+ mode->width = le16_to_cpu(mode_record->usHDisp);
-+ mode->height = le16_to_cpu(mode_record->usVDisp);
-+
-+ return BP_RESULT_OK;
-+}
-+
-+static enum bp_result get_gpio_i2c_info(struct bios_parser *bp,
-+ ATOM_I2C_RECORD *record,
-+ struct graphics_object_i2c_info *info)
-+{
-+ ATOM_GPIO_I2C_INFO *header;
-+ uint32_t count = 0;
-+
-+ if (!info)
-+ return BP_RESULT_BADINPUT;
-+
-+ /* get the GPIO_I2C info */
-+ if (!DATA_TABLES(GPIO_I2C_Info))
-+ return BP_RESULT_BADBIOSTABLE;
-+
-+ header = GET_IMAGE(ATOM_GPIO_I2C_INFO, DATA_TABLES(GPIO_I2C_Info));
-+ if (!header)
-+ return BP_RESULT_BADBIOSTABLE;
-+
-+ if (sizeof(ATOM_COMMON_TABLE_HEADER) + sizeof(ATOM_GPIO_I2C_ASSIGMENT)
-+ > le16_to_cpu(header->sHeader.usStructureSize))
-+ return BP_RESULT_BADBIOSTABLE;
-+
-+ if (1 != header->sHeader.ucTableContentRevision)
-+ return BP_RESULT_UNSUPPORTED;
-+
-+ /* get data count */
-+ count = (le16_to_cpu(header->sHeader.usStructureSize)
-+ - sizeof(ATOM_COMMON_TABLE_HEADER))
-+ / sizeof(ATOM_GPIO_I2C_ASSIGMENT);
-+ if (count < record->sucI2cId.bfI2C_LineMux)
-+ return BP_RESULT_BADBIOSTABLE;
-+
-+ /* get the GPIO_I2C_INFO */
-+ info->i2c_hw_assist = record->sucI2cId.bfHW_Capable;
-+ info->i2c_line = record->sucI2cId.bfI2C_LineMux;
-+ info->i2c_engine_id = record->sucI2cId.bfHW_EngineID;
-+ info->i2c_slave_address = record->ucI2CAddr;
-+
-+ info->gpio_info.clk_mask_register_index =
-+ le16_to_cpu(header->asGPIO_Info[info->i2c_line].usClkMaskRegisterIndex);
-+ info->gpio_info.clk_en_register_index =
-+ le16_to_cpu(header->asGPIO_Info[info->i2c_line].usClkEnRegisterIndex);
-+ info->gpio_info.clk_y_register_index =
-+ le16_to_cpu(header->asGPIO_Info[info->i2c_line].usClkY_RegisterIndex);
-+ info->gpio_info.clk_a_register_index =
-+ le16_to_cpu(header->asGPIO_Info[info->i2c_line].usClkA_RegisterIndex);
-+ info->gpio_info.data_mask_register_index =
-+ le16_to_cpu(header->asGPIO_Info[info->i2c_line].usDataMaskRegisterIndex);
-+ info->gpio_info.data_en_register_index =
-+ le16_to_cpu(header->asGPIO_Info[info->i2c_line].usDataEnRegisterIndex);
-+ info->gpio_info.data_y_register_index =
-+ le16_to_cpu(header->asGPIO_Info[info->i2c_line].usDataY_RegisterIndex);
-+ info->gpio_info.data_a_register_index =
-+ le16_to_cpu(header->asGPIO_Info[info->i2c_line].usDataA_RegisterIndex);
-+
-+ info->gpio_info.clk_mask_shift =
-+ header->asGPIO_Info[info->i2c_line].ucClkMaskShift;
-+ info->gpio_info.clk_en_shift =
-+ header->asGPIO_Info[info->i2c_line].ucClkEnShift;
-+ info->gpio_info.clk_y_shift =
-+ header->asGPIO_Info[info->i2c_line].ucClkY_Shift;
-+ info->gpio_info.clk_a_shift =
-+ header->asGPIO_Info[info->i2c_line].ucClkA_Shift;
-+ info->gpio_info.data_mask_shift =
-+ header->asGPIO_Info[info->i2c_line].ucDataMaskShift;
-+ info->gpio_info.data_en_shift =
-+ header->asGPIO_Info[info->i2c_line].ucDataEnShift;
-+ info->gpio_info.data_y_shift =
-+ header->asGPIO_Info[info->i2c_line].ucDataY_Shift;
-+ info->gpio_info.data_a_shift =
-+ header->asGPIO_Info[info->i2c_line].ucDataA_Shift;
-+
-+ return BP_RESULT_OK;
-+}
-+
-+static ATOM_OBJECT *get_bios_object(struct bios_parser *bp,
-+ struct graphics_object_id id)
-+{
-+ uint32_t offset;
-+ ATOM_OBJECT_TABLE *tbl;
-+ uint32_t i;
-+
-+ switch (id.type) {
-+ case OBJECT_TYPE_ENCODER:
-+ offset = le16_to_cpu(bp->object_info_tbl.v1_1->usEncoderObjectTableOffset);
-+ break;
-+
-+ case OBJECT_TYPE_CONNECTOR:
-+ offset = le16_to_cpu(bp->object_info_tbl.v1_1->usConnectorObjectTableOffset);
-+ break;
-+
-+ case OBJECT_TYPE_ROUTER:
-+ offset = le16_to_cpu(bp->object_info_tbl.v1_1->usRouterObjectTableOffset);
-+ break;
-+
-+ case OBJECT_TYPE_GENERIC:
-+ if (bp->object_info_tbl.revision.minor < 3)
-+ return NULL;
-+ offset = le16_to_cpu(bp->object_info_tbl.v1_3->usMiscObjectTableOffset);
-+ break;
-+
-+ default:
-+ return NULL;
-+ }
-+
-+ offset += bp->object_info_tbl_offset;
-+
-+ tbl = GET_IMAGE(ATOM_OBJECT_TABLE, offset);
-+ if (!tbl)
-+ return NULL;
-+
-+ for (i = 0; i < tbl->ucNumberOfObjects; i++)
-+ if (dal_graphics_object_id_is_equal(id,
-+ object_id_from_bios_object_id(
-+ le16_to_cpu(tbl->asObjects[i].usObjectID))))
-+ return &tbl->asObjects[i];
-+
-+ return NULL;
-+}
-+
-+static uint32_t get_dest_obj_list(struct bios_parser *bp,
-+ ATOM_OBJECT *object, uint16_t **id_list)
-+{
-+ uint32_t offset;
-+ uint8_t *number;
-+
-+ if (!object) {
-+ BREAK_TO_DEBUGGER(); /* Invalid object id */
-+ return 0;
-+ }
-+
-+ offset = le16_to_cpu(object->usSrcDstTableOffset)
-+ + bp->object_info_tbl_offset;
-+
-+ number = GET_IMAGE(uint8_t, offset);
-+ if (!number)
-+ return 0;
-+
-+ offset += sizeof(uint8_t);
-+ offset += sizeof(uint16_t) * (*number);
-+
-+ number = GET_IMAGE(uint8_t, offset);
-+ if ((!number) || (!*number))
-+ return 0;
-+
-+ offset += sizeof(uint8_t);
-+ *id_list = (uint16_t *)get_image(bp, offset,
-+ *number * sizeof(uint16_t));
-+
-+ if (!*id_list)
-+ return 0;
-+
-+ return *number;
-+}
-+
-+static uint32_t get_src_obj_list(struct bios_parser *bp, ATOM_OBJECT *object,
-+ uint16_t **id_list)
-+{
-+ uint32_t offset;
-+ uint8_t *number;
-+
-+ if (!object) {
-+ BREAK_TO_DEBUGGER(); /* Invalid object id */
-+ return 0;
-+ }
-+
-+ offset = le16_to_cpu(object->usSrcDstTableOffset)
-+ + bp->object_info_tbl_offset;
-+
-+ number = GET_IMAGE(uint8_t, offset);
-+ if (!number)
-+ return 0;
-+
-+ offset += sizeof(uint8_t);
-+ *id_list = (uint16_t *)get_image(bp, offset,
-+ *number * sizeof(uint16_t));
-+
-+ if (!*id_list)
-+ return 0;
-+
-+ return *number;
-+}
-+
-+static uint32_t get_dst_number_from_object(struct bios_parser *bp,
-+ ATOM_OBJECT *object)
-+{
-+ uint32_t offset;
-+ uint8_t *number;
-+
-+ if (!object) {
-+ BREAK_TO_DEBUGGER(); /* Invalid encoder object id*/
-+ return 0;
-+ }
-+
-+ offset = le16_to_cpu(object->usSrcDstTableOffset)
-+ + bp->object_info_tbl_offset;
-+
-+ number = GET_IMAGE(uint8_t, offset);
-+ if (!number)
-+ return 0;
-+
-+ offset += sizeof(uint8_t);
-+ offset += sizeof(uint16_t) * (*number);
-+
-+ number = GET_IMAGE(uint8_t, offset);
-+
-+ if (!number)
-+ return 0;
-+
-+ return *number;
-+}
-+
-+static uint8_t *get_image(struct bios_parser *bp,
-+ uint32_t offset,
-+ uint32_t size)
-+{
-+ if (bp->bios && offset + size < bp->bios_size)
-+ return bp->bios + offset;
-+ else
-+ return NULL;
-+}
-+
-+static uint32_t get_record_size(uint8_t *record)
-+{
-+ switch (*record) {
-+ case LCD_MODE_PATCH_RECORD_MODE_TYPE:
-+ return sizeof(ATOM_PATCH_RECORD_MODE);
-+
-+ case LCD_RTS_RECORD_TYPE:
-+ return sizeof(ATOM_LCD_RTS_RECORD);
-+
-+ case LCD_CAP_RECORD_TYPE:
-+ return sizeof(ATOM_LCD_MODE_CONTROL_CAP);
-+
-+ case LCD_FAKE_EDID_PATCH_RECORD_TYPE: {
-+ ATOM_FAKE_EDID_PATCH_RECORD *fake_record =
-+ (ATOM_FAKE_EDID_PATCH_RECORD *) record;
-+ uint32_t edid_size = get_edid_size(fake_record);
-+
-+ return sizeof(ATOM_FAKE_EDID_PATCH_RECORD) + edid_size
-+ - sizeof(fake_record->ucFakeEDIDString);
-+ }
-+
-+ case LCD_PANEL_RESOLUTION_RECORD_TYPE:
-+ return sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD);
-+
-+ default:
-+ return 0;
-+ }
-+}
-+
-+static uint32_t get_edid_size(const ATOM_FAKE_EDID_PATCH_RECORD *edid)
-+{
-+ uint32_t length = edid->ucFakeEDIDLength;
-+
-+ if (length < 128)
-+ length = length * 128;
-+
-+ return length;
-+}
-+
-+static struct graphics_object_id object_id_from_bios_object_id(
-+ uint32_t bios_object_id)
-+{
-+ enum object_type type;
-+ enum object_enum_id enum_id;
-+ struct graphics_object_id go_id = { 0 };
-+
-+ type = object_type_from_bios_object_id(bios_object_id);
-+
-+ if (OBJECT_TYPE_UNKNOWN == type)
-+ return go_id;
-+
-+ enum_id = enum_id_from_bios_object_id(bios_object_id);
-+
-+ if (ENUM_ID_UNKNOWN == enum_id)
-+ return go_id;
-+
-+ go_id = dal_graphics_object_id_init(
-+ id_from_bios_object_id(type, bios_object_id), enum_id, type);
-+
-+ return go_id;
-+}
-+
-+static enum object_type object_type_from_bios_object_id(uint32_t bios_object_id)
-+{
-+ uint32_t bios_object_type = (bios_object_id & OBJECT_TYPE_MASK)
-+ >> OBJECT_TYPE_SHIFT;
-+ enum object_type object_type;
-+
-+ switch (bios_object_type) {
-+ case GRAPH_OBJECT_TYPE_GPU:
-+ object_type = OBJECT_TYPE_GPU;
-+ break;
-+ case GRAPH_OBJECT_TYPE_ENCODER:
-+ object_type = OBJECT_TYPE_ENCODER;
-+ break;
-+ case GRAPH_OBJECT_TYPE_CONNECTOR:
-+ object_type = OBJECT_TYPE_CONNECTOR;
-+ break;
-+ case GRAPH_OBJECT_TYPE_ROUTER:
-+ object_type = OBJECT_TYPE_ROUTER;
-+ break;
-+ case GRAPH_OBJECT_TYPE_GENERIC:
-+ object_type = OBJECT_TYPE_GENERIC;
-+ break;
-+ default:
-+ object_type = OBJECT_TYPE_UNKNOWN;
-+ break;
-+ }
-+
-+ return object_type;
-+}
-+
-+static enum object_enum_id enum_id_from_bios_object_id(uint32_t bios_object_id)
-+{
-+ uint32_t bios_enum_id =
-+ (bios_object_id & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
-+ enum object_enum_id id;
-+
-+ switch (bios_enum_id) {
-+ case GRAPH_OBJECT_ENUM_ID1:
-+ id = ENUM_ID_1;
-+ break;
-+ case GRAPH_OBJECT_ENUM_ID2:
-+ id = ENUM_ID_2;
-+ break;
-+ case GRAPH_OBJECT_ENUM_ID3:
-+ id = ENUM_ID_3;
-+ break;
-+ case GRAPH_OBJECT_ENUM_ID4:
-+ id = ENUM_ID_4;
-+ break;
-+ case GRAPH_OBJECT_ENUM_ID5:
-+ id = ENUM_ID_5;
-+ break;
-+ case GRAPH_OBJECT_ENUM_ID6:
-+ id = ENUM_ID_6;
-+ break;
-+ case GRAPH_OBJECT_ENUM_ID7:
-+ id = ENUM_ID_7;
-+ break;
-+ default:
-+ id = ENUM_ID_UNKNOWN;
-+ break;
-+ }
-+
-+ return id;
-+}
-+
-+static uint32_t id_from_bios_object_id(enum object_type type,
-+ uint32_t bios_object_id)
-+{
-+ switch (type) {
-+ case OBJECT_TYPE_GPU:
-+ return gpu_id_from_bios_object_id(bios_object_id);
-+ case OBJECT_TYPE_ENCODER:
-+ return (uint32_t)encoder_id_from_bios_object_id(bios_object_id);
-+ case OBJECT_TYPE_CONNECTOR:
-+ return (uint32_t)connector_id_from_bios_object_id(
-+ bios_object_id);
-+ case OBJECT_TYPE_GENERIC:
-+ return generic_id_from_bios_object_id(bios_object_id);
-+ default:
-+ return 0;
-+ }
-+}
-+
-+static enum connector_id connector_id_from_bios_object_id(
-+ uint32_t bios_object_id)
-+{
-+ uint32_t bios_connector_id = gpu_id_from_bios_object_id(bios_object_id);
-+
-+ enum connector_id id;
-+
-+ switch (bios_connector_id) {
-+ case CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I:
-+ id = CONNECTOR_ID_SINGLE_LINK_DVII;
-+ break;
-+ case CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I:
-+ id = CONNECTOR_ID_DUAL_LINK_DVII;
-+ break;
-+ case CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D:
-+ id = CONNECTOR_ID_SINGLE_LINK_DVID;
-+ break;
-+ case CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D:
-+ id = CONNECTOR_ID_DUAL_LINK_DVID;
-+ break;
-+ case CONNECTOR_OBJECT_ID_VGA:
-+ id = CONNECTOR_ID_VGA;
-+ break;
-+ case CONNECTOR_OBJECT_ID_HDMI_TYPE_A:
-+ id = CONNECTOR_ID_HDMI_TYPE_A;
-+ break;
-+ case CONNECTOR_OBJECT_ID_LVDS:
-+ id = CONNECTOR_ID_LVDS;
-+ break;
-+ case CONNECTOR_OBJECT_ID_PCIE_CONNECTOR:
-+ id = CONNECTOR_ID_PCIE;
-+ break;
-+ case CONNECTOR_OBJECT_ID_HARDCODE_DVI:
-+ id = CONNECTOR_ID_HARDCODE_DVI;
-+ break;
-+ case CONNECTOR_OBJECT_ID_DISPLAYPORT:
-+ id = CONNECTOR_ID_DISPLAY_PORT;
-+ break;
-+ case CONNECTOR_OBJECT_ID_eDP:
-+ id = CONNECTOR_ID_EDP;
-+ break;
-+ case CONNECTOR_OBJECT_ID_MXM:
-+ id = CONNECTOR_ID_MXM;
-+ break;
-+ default:
-+ id = CONNECTOR_ID_UNKNOWN;
-+ break;
-+ }
-+
-+ return id;
-+}
-+
-+static enum encoder_id encoder_id_from_bios_object_id(uint32_t bios_object_id)
-+{
-+ uint32_t bios_encoder_id = gpu_id_from_bios_object_id(bios_object_id);
-+ enum encoder_id id;
-+
-+ switch (bios_encoder_id) {
-+ case ENCODER_OBJECT_ID_INTERNAL_LVDS:
-+ id = ENCODER_ID_INTERNAL_LVDS;
-+ break;
-+ case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
-+ id = ENCODER_ID_INTERNAL_TMDS1;
-+ break;
-+ case ENCODER_OBJECT_ID_INTERNAL_TMDS2:
-+ id = ENCODER_ID_INTERNAL_TMDS2;
-+ break;
-+ case ENCODER_OBJECT_ID_INTERNAL_DAC1:
-+ id = ENCODER_ID_INTERNAL_DAC1;
-+ break;
-+ case ENCODER_OBJECT_ID_INTERNAL_DAC2:
-+ id = ENCODER_ID_INTERNAL_DAC2;
-+ break;
-+ case ENCODER_OBJECT_ID_INTERNAL_SDVOA:
-+ id = ENCODER_ID_INTERNAL_SDVOA;
-+ break;
-+ case ENCODER_OBJECT_ID_INTERNAL_SDVOB:
-+ id = ENCODER_ID_INTERNAL_SDVOB;
-+ break;
-+ case ENCODER_OBJECT_ID_SI170B:
-+ id = ENCODER_ID_EXTERNAL_SI170B;
-+ break;
-+ case ENCODER_OBJECT_ID_CH7303:
-+ id = ENCODER_ID_EXTERNAL_CH7303;
-+ break;
-+ case ENCODER_OBJECT_ID_CH7301:
-+ id = ENCODER_ID_EXTERNAL_CH7301;
-+ break;
-+ case ENCODER_OBJECT_ID_INTERNAL_DVO1:
-+ id = ENCODER_ID_INTERNAL_DVO1;
-+ break;
-+ case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
-+ id = ENCODER_ID_EXTERNAL_SDVOA;
-+ break;
-+ case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
-+ id = ENCODER_ID_EXTERNAL_SDVOB;
-+ break;
-+ case ENCODER_OBJECT_ID_TITFP513:
-+ id = ENCODER_ID_EXTERNAL_TITFP513;
-+ break;
-+ case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
-+ id = ENCODER_ID_INTERNAL_LVTM1;
-+ break;
-+ case ENCODER_OBJECT_ID_VT1623:
-+ id = ENCODER_ID_EXTERNAL_VT1623;
-+ break;
-+ case ENCODER_OBJECT_ID_HDMI_SI1930:
-+ id = ENCODER_ID_EXTERNAL_SI1930;
-+ break;
-+ case ENCODER_OBJECT_ID_HDMI_INTERNAL:
-+ id = ENCODER_ID_INTERNAL_HDMI;
-+ break;
-+ case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
-+ id = ENCODER_ID_INTERNAL_KLDSCP_TMDS1;
-+ break;
-+ case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
-+ id = ENCODER_ID_INTERNAL_KLDSCP_DVO1;
-+ break;
-+ case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
-+ id = ENCODER_ID_INTERNAL_KLDSCP_DAC1;
-+ break;
-+ case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
-+ id = ENCODER_ID_INTERNAL_KLDSCP_DAC2;
-+ break;
-+ case ENCODER_OBJECT_ID_SI178:
-+ id = ENCODER_ID_EXTERNAL_SI178;
-+ break;
-+ case ENCODER_OBJECT_ID_MVPU_FPGA:
-+ id = ENCODER_ID_EXTERNAL_MVPU_FPGA;
-+ break;
-+ case ENCODER_OBJECT_ID_INTERNAL_DDI:
-+ id = ENCODER_ID_INTERNAL_DDI;
-+ break;
-+ case ENCODER_OBJECT_ID_VT1625:
-+ id = ENCODER_ID_EXTERNAL_VT1625;
-+ break;
-+ case ENCODER_OBJECT_ID_HDMI_SI1932:
-+ id = ENCODER_ID_EXTERNAL_SI1932;
-+ break;
-+ case ENCODER_OBJECT_ID_DP_AN9801:
-+ id = ENCODER_ID_EXTERNAL_AN9801;
-+ break;
-+ case ENCODER_OBJECT_ID_DP_DP501:
-+ id = ENCODER_ID_EXTERNAL_DP501;
-+ break;
-+ case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
-+ id = ENCODER_ID_INTERNAL_UNIPHY;
-+ break;
-+ case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
-+ id = ENCODER_ID_INTERNAL_KLDSCP_LVTMA;
-+ break;
-+ case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
-+ id = ENCODER_ID_INTERNAL_UNIPHY1;
-+ break;
-+ case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
-+ id = ENCODER_ID_INTERNAL_UNIPHY2;
-+ break;
-+ case ENCODER_OBJECT_ID_GENERAL_EXTERNAL_DVO:
-+ id = ENCODER_ID_EXTERNAL_GENERIC_DVO;
-+ break;
-+ case ENCODER_OBJECT_ID_ALMOND: /* ENCODER_OBJECT_ID_NUTMEG */
-+ id = ENCODER_ID_EXTERNAL_NUTMEG;
-+ break;
-+ case ENCODER_OBJECT_ID_TRAVIS:
-+ id = ENCODER_ID_EXTERNAL_TRAVIS;
-+ break;
-+ case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
-+ id = ENCODER_ID_INTERNAL_UNIPHY3;
-+ break;
-+ default:
-+ id = ENCODER_ID_UNKNOWN;
-+ break;
-+ }
-+
-+ return id;
-+}
-+
-+uint32_t gpu_id_from_bios_object_id(uint32_t bios_object_id)
-+{
-+ return (bios_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
-+}
-+
-+enum generic_id generic_id_from_bios_object_id(uint32_t bios_object_id)
-+{
-+ uint32_t bios_generic_id = gpu_id_from_bios_object_id(bios_object_id);
-+
-+ enum generic_id id;
-+
-+ switch (bios_generic_id) {
-+ case GENERIC_OBJECT_ID_MXM_OPM:
-+ id = GENERIC_ID_MXM_OPM;
-+ break;
-+ case GENERIC_OBJECT_ID_GLSYNC:
-+ id = GENERIC_ID_GLSYNC;
-+ break;
-+ case GENERIC_OBJECT_ID_STEREO_PIN:
-+ id = GENERIC_ID_STEREO;
-+ break;
-+ default:
-+ id = GENERIC_ID_UNKNOWN;
-+ break;
-+ }
-+
-+ return id;
-+}
-+
-+static struct device_id device_type_from_device_id(uint16_t device_id)
-+{
-+
-+ struct device_id result_device_id;
-+
-+ switch (device_id) {
-+ case ATOM_DEVICE_LCD1_SUPPORT:
-+ result_device_id.device_type = DEVICE_TYPE_LCD;
-+ result_device_id.enum_id = 1;
-+ break;
-+
-+ case ATOM_DEVICE_LCD2_SUPPORT:
-+ result_device_id.device_type = DEVICE_TYPE_LCD;
-+ result_device_id.enum_id = 2;
-+ break;
-+
-+ case ATOM_DEVICE_CRT1_SUPPORT:
-+ result_device_id.device_type = DEVICE_TYPE_CRT;
-+ result_device_id.enum_id = 1;
-+ break;
-+
-+ case ATOM_DEVICE_CRT2_SUPPORT:
-+ result_device_id.device_type = DEVICE_TYPE_CRT;
-+ result_device_id.enum_id = 2;
-+ break;
-+
-+ case ATOM_DEVICE_DFP1_SUPPORT:
-+ result_device_id.device_type = DEVICE_TYPE_DFP;
-+ result_device_id.enum_id = 1;
-+ break;
-+
-+ case ATOM_DEVICE_DFP2_SUPPORT:
-+ result_device_id.device_type = DEVICE_TYPE_DFP;
-+ result_device_id.enum_id = 2;
-+ break;
-+
-+ case ATOM_DEVICE_DFP3_SUPPORT:
-+ result_device_id.device_type = DEVICE_TYPE_DFP;
-+ result_device_id.enum_id = 3;
-+ break;
-+
-+ case ATOM_DEVICE_DFP4_SUPPORT:
-+ result_device_id.device_type = DEVICE_TYPE_DFP;
-+ result_device_id.enum_id = 4;
-+ break;
-+
-+ case ATOM_DEVICE_DFP5_SUPPORT:
-+ result_device_id.device_type = DEVICE_TYPE_DFP;
-+ result_device_id.enum_id = 5;
-+ break;
-+
-+ case ATOM_DEVICE_DFP6_SUPPORT:
-+ result_device_id.device_type = DEVICE_TYPE_DFP;
-+ result_device_id.enum_id = 6;
-+ break;
-+
-+ default:
-+ BREAK_TO_DEBUGGER(); /* Invalid device Id */
-+ result_device_id.device_type = DEVICE_TYPE_UNKNOWN;
-+ result_device_id.enum_id = 0;
-+ }
-+ return result_device_id;
-+}
-+
-+static void get_atom_data_table_revision(
-+ ATOM_COMMON_TABLE_HEADER *atom_data_tbl,
-+ struct atom_data_revision *tbl_revision)
-+{
-+ if (!tbl_revision)
-+ return;
-+
-+ /* initialize the revision to 0 which is invalid revision */
-+ tbl_revision->major = 0;
-+ tbl_revision->minor = 0;
-+
-+ if (!atom_data_tbl)
-+ return;
-+
-+ tbl_revision->major =
-+ (uint32_t) GET_DATA_TABLE_MAJOR_REVISION(atom_data_tbl);
-+ tbl_revision->minor =
-+ (uint32_t) GET_DATA_TABLE_MINOR_REVISION(atom_data_tbl);
-+}
-+
-+static uint32_t signal_to_ss_id(enum as_signal_type signal)
-+{
-+ uint32_t clk_id_ss = 0;
-+
-+ switch (signal) {
-+ case AS_SIGNAL_TYPE_DVI:
-+ clk_id_ss = ASIC_INTERNAL_SS_ON_TMDS;
-+ break;
-+ case AS_SIGNAL_TYPE_HDMI:
-+ clk_id_ss = ASIC_INTERNAL_SS_ON_HDMI;
-+ break;
-+ case AS_SIGNAL_TYPE_LVDS:
-+ clk_id_ss = ASIC_INTERNAL_SS_ON_LVDS;
-+ break;
-+ case AS_SIGNAL_TYPE_DISPLAY_PORT:
-+ clk_id_ss = ASIC_INTERNAL_SS_ON_DP;
-+ break;
-+ case AS_SIGNAL_TYPE_GPU_PLL:
-+ clk_id_ss = ASIC_INTERNAL_GPUPLL_SS;
-+ break;
-+ default:
-+ break;
-+ }
-+ return clk_id_ss;
-+}
-+
-+static uint32_t get_support_mask_for_device_id(struct device_id device_id)
-+{
-+ enum dal_device_type device_type = device_id.device_type;
-+ uint32_t enum_id = device_id.enum_id;
-+
-+ switch (device_type) {
-+ case DEVICE_TYPE_LCD:
-+ switch (enum_id) {
-+ case 1:
-+ return ATOM_DEVICE_LCD1_SUPPORT;
-+ case 2:
-+ return ATOM_DEVICE_LCD2_SUPPORT;
-+ default:
-+ break;
-+ }
-+ break;
-+ case DEVICE_TYPE_CRT:
-+ switch (enum_id) {
-+ case 1:
-+ return ATOM_DEVICE_CRT1_SUPPORT;
-+ case 2:
-+ return ATOM_DEVICE_CRT2_SUPPORT;
-+ default:
-+ break;
-+ }
-+ break;
-+ case DEVICE_TYPE_DFP:
-+ switch (enum_id) {
-+ case 1:
-+ return ATOM_DEVICE_DFP1_SUPPORT;
-+ case 2:
-+ return ATOM_DEVICE_DFP2_SUPPORT;
-+ case 3:
-+ return ATOM_DEVICE_DFP3_SUPPORT;
-+ case 4:
-+ return ATOM_DEVICE_DFP4_SUPPORT;
-+ case 5:
-+ return ATOM_DEVICE_DFP5_SUPPORT;
-+ case 6:
-+ return ATOM_DEVICE_DFP6_SUPPORT;
-+ default:
-+ break;
-+ }
-+ break;
-+ case DEVICE_TYPE_CV:
-+ switch (enum_id) {
-+ case 1:
-+ return ATOM_DEVICE_CV_SUPPORT;
-+ default:
-+ break;
-+ }
-+ break;
-+ case DEVICE_TYPE_TV:
-+ switch (enum_id) {
-+ case 1:
-+ return ATOM_DEVICE_TV1_SUPPORT;
-+ default:
-+ break;
-+ }
-+ break;
-+ default:
-+ break;
-+ };
-+
-+ /* Unidentified device ID, return empty support mask. */
-+ return 0;
-+}
-+
-+/**
-+* HwContext interface for writing MM registers
-+*/
-+
-+static bool i2c_read(
-+ struct bios_parser *bp,
-+ struct graphics_object_i2c_info *i2c_info,
-+ uint8_t *buffer,
-+ uint32_t length)
-+{
-+ struct ddc *ddc;
-+ uint8_t offset[2] = { 0, 0 };
-+ bool result = false;
-+ struct i2c_command cmd;
-+
-+ ddc = dal_adapter_service_obtain_ddc_from_i2c_info(bp->as, i2c_info);
-+
-+ if (!ddc)
-+ return result;
-+
-+ /*Using SW engine */
-+ cmd.engine = I2C_COMMAND_ENGINE_SW;
-+ cmd.speed = dal_adapter_service_get_sw_i2c_speed(bp->as);
-+
-+ {
-+ struct i2c_payload payloads[] = {
-+ {
-+ .address = i2c_info->i2c_slave_address >> 1,
-+ .data = offset,
-+ .length = sizeof(offset),
-+ .write = true
-+ },
-+ {
-+ .address = i2c_info->i2c_slave_address >> 1,
-+ .data = buffer,
-+ .length = length,
-+ .write = false
-+ }
-+ };
-+
-+ cmd.payloads = payloads;
-+ cmd.number_of_payloads = ARRAY_SIZE(payloads);
-+
-+ result = dal_i2caux_submit_i2c_command(
-+ dal_adapter_service_get_i2caux(bp->as),
-+ ddc,
-+ &cmd);
-+ }
-+
-+ dal_adapter_service_release_ddc(bp->as, ddc);
-+
-+ return result;
-+}
-+
-+/**
-+ * Read external display connection info table through i2c.
-+ * validate the GUID and checksum.
-+ *
-+ * @return enum bp_result whether all data was sucessfully read
-+ */
-+static enum bp_result get_ext_display_connection_info(
-+ struct bios_parser *bp,
-+ ATOM_OBJECT *opm_object,
-+ ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO *ext_display_connection_info_tbl)
-+{
-+ bool config_tbl_present = false;
-+ ATOM_I2C_RECORD *i2c_record = NULL;
-+ uint32_t i = 0;
-+
-+ if (opm_object == NULL)
-+ return BP_RESULT_BADINPUT;
-+
-+ i2c_record = get_i2c_record(bp, opm_object);
-+
-+ if (i2c_record != NULL) {
-+ ATOM_GPIO_I2C_INFO *gpio_i2c_header;
-+ struct graphics_object_i2c_info i2c_info;
-+
-+ gpio_i2c_header = GET_IMAGE(ATOM_GPIO_I2C_INFO,
-+ bp->master_data_tbl->ListOfDataTables.GPIO_I2C_Info);
-+
-+ if (NULL == gpio_i2c_header)
-+ return BP_RESULT_BADBIOSTABLE;
-+
-+ if (get_gpio_i2c_info(bp, i2c_record, &i2c_info) !=
-+ BP_RESULT_OK)
-+ return BP_RESULT_BADBIOSTABLE;
-+
-+ if (i2c_read(
-+ bp,
-+ &i2c_info,
-+ (uint8_t *)ext_display_connection_info_tbl,
-+ sizeof(ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO))) {
-+ config_tbl_present = true;
-+ }
-+ }
-+
-+ /* Validate GUID */
-+ if (config_tbl_present)
-+ for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; i++) {
-+ if (ext_display_connection_info_tbl->ucGuid[i]
-+ != ext_display_connection_guid[i]) {
-+ config_tbl_present = false;
-+ break;
-+ }
-+ }
-+
-+ /* Validate checksum */
-+ if (config_tbl_present) {
-+ uint8_t check_sum = 0;
-+ uint8_t *buf =
-+ (uint8_t *)ext_display_connection_info_tbl;
-+
-+ for (i = 0; i < sizeof(ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO);
-+ i++) {
-+ check_sum += buf[i];
-+ }
-+
-+ if (check_sum != 0)
-+ config_tbl_present = false;
-+ }
-+
-+ if (config_tbl_present)
-+ return BP_RESULT_OK;
-+ else
-+ return BP_RESULT_FAILURE;
-+}
-+
-+/*
-+ * Gets the first device ID in the same group as the given ID for enumerating.
-+ * For instance, if any DFP device ID is passed, returns the device ID for DFP1.
-+ *
-+ * The first device ID in the same group as the passed device ID, or 0 if no
-+ * matching device group found.
-+ */
-+static uint32_t enum_first_device_id(uint32_t dev_id)
-+{
-+ /* Return the first in the group that this ID belongs to. */
-+ if (dev_id & ATOM_DEVICE_CRT_SUPPORT)
-+ return ATOM_DEVICE_CRT1_SUPPORT;
-+ else if (dev_id & ATOM_DEVICE_DFP_SUPPORT)
-+ return ATOM_DEVICE_DFP1_SUPPORT;
-+ else if (dev_id & ATOM_DEVICE_LCD_SUPPORT)
-+ return ATOM_DEVICE_LCD1_SUPPORT;
-+ else if (dev_id & ATOM_DEVICE_TV_SUPPORT)
-+ return ATOM_DEVICE_TV1_SUPPORT;
-+ else if (dev_id & ATOM_DEVICE_CV_SUPPORT)
-+ return ATOM_DEVICE_CV_SUPPORT;
-+
-+ /* No group found for this device ID. */
-+
-+ dal_error("%s: incorrect input %d\n", __func__, dev_id);
-+ /* No matching support flag for given device ID */
-+ return 0;
-+}
-+
-+/*
-+ * Gets the next device ID in the group for a given device ID.
-+ *
-+ * The current device ID being enumerated on.
-+ *
-+ * The next device ID in the group, or 0 if no device exists.
-+ */
-+static uint32_t enum_next_dev_id(uint32_t dev_id)
-+{
-+ /* Get next device ID in the group. */
-+ switch (dev_id) {
-+ case ATOM_DEVICE_CRT1_SUPPORT:
-+ return ATOM_DEVICE_CRT2_SUPPORT;
-+ case ATOM_DEVICE_LCD1_SUPPORT:
-+ return ATOM_DEVICE_LCD2_SUPPORT;
-+ case ATOM_DEVICE_DFP1_SUPPORT:
-+ return ATOM_DEVICE_DFP2_SUPPORT;
-+ case ATOM_DEVICE_DFP2_SUPPORT:
-+ return ATOM_DEVICE_DFP3_SUPPORT;
-+ case ATOM_DEVICE_DFP3_SUPPORT:
-+ return ATOM_DEVICE_DFP4_SUPPORT;
-+ case ATOM_DEVICE_DFP4_SUPPORT:
-+ return ATOM_DEVICE_DFP5_SUPPORT;
-+ case ATOM_DEVICE_DFP5_SUPPORT:
-+ return ATOM_DEVICE_DFP6_SUPPORT;
-+ }
-+
-+ /* Done enumerating through devices. */
-+ return 0;
-+}
-+
-+/*
-+ * Returns the new device tag record for patched BIOS object.
-+ *
-+ * [IN] pExtDisplayPath - External display path to copy device tag from.
-+ * [IN] deviceSupport - Bit vector for device ID support flags.
-+ * [OUT] pDeviceTag - Device tag structure to fill with patched data.
-+ *
-+ * True if a compatible device ID was found, false otherwise.
-+ */
-+static bool get_patched_device_tag(
-+ struct bios_parser *bp,
-+ EXT_DISPLAY_PATH *ext_display_path,
-+ uint32_t device_support,
-+ ATOM_CONNECTOR_DEVICE_TAG *device_tag)
-+{
-+ uint32_t dev_id;
-+ /* Use fallback behaviour if not supported. */
-+ if (!bp->remap_device_tags) {
-+ device_tag->ulACPIDeviceEnum =
-+ cpu_to_le32((uint32_t) le16_to_cpu(ext_display_path->usDeviceACPIEnum));
-+ device_tag->usDeviceID =
-+ cpu_to_le16(le16_to_cpu(ext_display_path->usDeviceTag));
-+ return true;
-+ }
-+
-+ /* Find the first unused in the same group. */
-+ dev_id = enum_first_device_id(le16_to_cpu(ext_display_path->usDeviceTag));
-+ while (dev_id != 0) {
-+ /* Assign this device ID if supported. */
-+ if ((device_support & dev_id) != 0) {
-+ device_tag->ulACPIDeviceEnum =
-+ cpu_to_le32((uint32_t) le16_to_cpu(ext_display_path->usDeviceACPIEnum));
-+ device_tag->usDeviceID = cpu_to_le16((USHORT) dev_id);
-+ return true;
-+ }
-+
-+ dev_id = enum_next_dev_id(dev_id);
-+ }
-+
-+ /* No compatible device ID found. */
-+ return false;
-+}
-+
-+/*
-+ * Adds a device tag to a BIOS object's device tag record if there is
-+ * matching device ID supported.
-+ *
-+ * pObject - Pointer to the BIOS object to add the device tag to.
-+ * pExtDisplayPath - Display path to retrieve base device ID from.
-+ * pDeviceSupport - Pointer to bit vector for supported device IDs.
-+ */
-+static void add_device_tag_from_ext_display_path(
-+ struct bios_parser *bp,
-+ ATOM_OBJECT *object,
-+ EXT_DISPLAY_PATH *ext_display_path,
-+ uint32_t *device_support)
-+{
-+ /* Get device tag record for object. */
-+ ATOM_CONNECTOR_DEVICE_TAG *device_tag = NULL;
-+ ATOM_CONNECTOR_DEVICE_TAG_RECORD *device_tag_record = NULL;
-+ enum bp_result result =
-+ dal_bios_parser_get_device_tag_record(
-+ bp, object, &device_tag_record);
-+
-+ if ((le16_to_cpu(ext_display_path->usDeviceTag) != CONNECTOR_OBJECT_ID_NONE)
-+ && (result == BP_RESULT_OK)) {
-+ uint8_t index;
-+
-+ if ((device_tag_record->ucNumberOfDevice == 1) &&
-+ (le16_to_cpu(device_tag_record->asDeviceTag[0].usDeviceID) == 0)) {
-+ /*Workaround bug in current VBIOS releases where
-+ * ucNumberOfDevice = 1 but there is no actual device
-+ * tag data. This w/a is temporary until the updated
-+ * VBIOS is distributed. */
-+ device_tag_record->ucNumberOfDevice =
-+ device_tag_record->ucNumberOfDevice - 1;
-+ }
-+
-+ /* Attempt to find a matching device ID. */
-+ index = device_tag_record->ucNumberOfDevice;
-+ device_tag = &device_tag_record->asDeviceTag[index];
-+ if (get_patched_device_tag(
-+ bp,
-+ ext_display_path,
-+ *device_support,
-+ device_tag)) {
-+ /* Update cached device support to remove assigned ID.
-+ */
-+ *device_support &= ~le16_to_cpu(device_tag->usDeviceID);
-+ device_tag_record->ucNumberOfDevice++;
-+ }
-+ }
-+}
-+
-+/*
-+ * Read out a single EXT_DISPLAY_PATH from the external display connection info
-+ * table. The specific entry in the table is determined by the enum_id passed
-+ * in.
-+ *
-+ * EXT_DISPLAY_PATH describing a single Configuration table entry
-+ */
-+
-+#define INVALID_CONNECTOR 0xffff
-+
-+static EXT_DISPLAY_PATH *get_ext_display_path_entry(
-+ ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO *config_table,
-+ uint32_t bios_object_id)
-+{
-+ EXT_DISPLAY_PATH *ext_display_path;
-+ uint32_t ext_display_path_index =
-+ ((bios_object_id & ENUM_ID_MASK) >> ENUM_ID_SHIFT) - 1;
-+
-+ if (ext_display_path_index >= MAX_NUMBER_OF_EXT_DISPLAY_PATH)
-+ return NULL;
-+
-+ ext_display_path = &config_table->sPath[ext_display_path_index];
-+
-+ if (le16_to_cpu(ext_display_path->usDeviceConnector) == INVALID_CONNECTOR)
-+ ext_display_path->usDeviceConnector = cpu_to_le16(0);
-+
-+ return ext_display_path;
-+}
-+
-+/*
-+ * Get AUX/DDC information of input object id
-+ *
-+ * search all records to find the ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE record
-+ * IR
-+ */
-+static ATOM_CONNECTOR_AUXDDC_LUT_RECORD *get_ext_connector_aux_ddc_lut_record(
-+ struct bios_parser *bp,
-+ ATOM_OBJECT *object)
-+{
-+ uint32_t offset;
-+ ATOM_COMMON_RECORD_HEADER *header;
-+
-+ if (!object) {
-+ BREAK_TO_DEBUGGER();
-+ /* Invalid object */
-+ return NULL;
-+ }
-+
-+ offset = le16_to_cpu(object->usRecordOffset)
-+ + bp->object_info_tbl_offset;
-+
-+ for (;;) {
-+ header = GET_IMAGE(ATOM_COMMON_RECORD_HEADER, offset);
-+
-+ if (!header)
-+ return NULL;
-+
-+ if (LAST_RECORD_TYPE == header->ucRecordType ||
-+ 0 == header->ucRecordSize)
-+ break;
-+
-+ if (ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE ==
-+ header->ucRecordType &&
-+ sizeof(ATOM_CONNECTOR_AUXDDC_LUT_RECORD) <=
-+ header->ucRecordSize)
-+ return (ATOM_CONNECTOR_AUXDDC_LUT_RECORD *)(header);
-+
-+ offset += header->ucRecordSize;
-+ }
-+
-+ return NULL;
-+}
-+
-+/*
-+ * Get AUX/DDC information of input object id
-+ *
-+ * search all records to find the ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE record
-+ * IR
-+ */
-+static ATOM_CONNECTOR_HPDPIN_LUT_RECORD *get_ext_connector_hpd_pin_lut_record(
-+ struct bios_parser *bp,
-+ ATOM_OBJECT *object)
-+{
-+ uint32_t offset;
-+ ATOM_COMMON_RECORD_HEADER *header;
-+
-+ if (!object) {
-+ BREAK_TO_DEBUGGER();
-+ /* Invalid object */
-+ return NULL;
-+ }
-+
-+ offset = le16_to_cpu(object->usRecordOffset)
-+ + bp->object_info_tbl_offset;
-+
-+ for (;;) {
-+ header = GET_IMAGE(ATOM_COMMON_RECORD_HEADER, offset);
-+
-+ if (!header)
-+ return NULL;
-+
-+ if (LAST_RECORD_TYPE == header->ucRecordType ||
-+ 0 == header->ucRecordSize)
-+ break;
-+
-+ if (ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE ==
-+ header->ucRecordType &&
-+ sizeof(ATOM_CONNECTOR_HPDPIN_LUT_RECORD) <=
-+ header->ucRecordSize)
-+ return (ATOM_CONNECTOR_HPDPIN_LUT_RECORD *)header;
-+
-+ offset += header->ucRecordSize;
-+ }
-+
-+ return NULL;
-+}
-+
-+/*
-+ * Check whether we need to patch the VBIOS connector info table with
-+ * data from an external display connection info table. This is
-+ * necessary to support MXM boards with an OPM (output personality
-+ * module). With these designs, the VBIOS connector info table
-+ * specifies an MXM_CONNECTOR with a unique ID. The driver retrieves
-+ * the external connection info table through i2c and then looks up the
-+ * connector ID to find the real connector type (e.g. DFP1).
-+ *
-+ */
-+static enum bp_result patch_bios_image_from_ext_display_connection_info(
-+ struct bios_parser *bp)
-+{
-+ ATOM_OBJECT_TABLE *connector_tbl;
-+ uint32_t connector_tbl_offset;
-+ struct graphics_object_id object_id;
-+ ATOM_OBJECT *object;
-+ ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO ext_display_connection_info_tbl;
-+ EXT_DISPLAY_PATH *ext_display_path;
-+ ATOM_CONNECTOR_AUXDDC_LUT_RECORD *aux_ddc_lut_record = NULL;
-+ ATOM_I2C_RECORD *i2c_record = NULL;
-+ ATOM_CONNECTOR_HPDPIN_LUT_RECORD *hpd_pin_lut_record = NULL;
-+ ATOM_HPD_INT_RECORD *hpd_record = NULL;
-+ ATOM_OBJECT_TABLE *encoder_table;
-+ uint32_t encoder_table_offset;
-+ ATOM_OBJECT *opm_object = NULL;
-+ uint32_t i = 0;
-+ struct graphics_object_id opm_object_id =
-+ dal_graphics_object_id_init(
-+ GENERIC_ID_MXM_OPM,
-+ ENUM_ID_1,
-+ OBJECT_TYPE_GENERIC);
-+ ATOM_CONNECTOR_DEVICE_TAG_RECORD *dev_tag_record;
-+ uint32_t cached_device_support =
-+ le16_to_cpu(bp->object_info_tbl.v1_1->usDeviceSupport);
-+
-+ uint32_t dst_number;
-+ uint16_t *dst_object_id_list;
-+
-+ opm_object = get_bios_object(bp, opm_object_id);
-+ if (!opm_object)
-+ return BP_RESULT_UNSUPPORTED;
-+
-+ dc_service_memset(&ext_display_connection_info_tbl, 0,
-+ sizeof(ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO));
-+
-+ connector_tbl_offset = bp->object_info_tbl_offset
-+ + le16_to_cpu(bp->object_info_tbl.v1_1->usConnectorObjectTableOffset);
-+ connector_tbl = GET_IMAGE(ATOM_OBJECT_TABLE, connector_tbl_offset);
-+
-+ /* Read Connector info table from EEPROM through i2c */
-+ if (get_ext_display_connection_info(
-+ bp,
-+ opm_object,
-+ &ext_display_connection_info_tbl) != BP_RESULT_OK) {
-+ if (bp->headless_no_opm) {
-+ /* Failed to read OPM, remove all non-CF connectors. */
-+ for (i = 0; i < connector_tbl->ucNumberOfObjects; ++i) {
-+ object = &connector_tbl->asObjects[i];
-+ object_id = object_id_from_bios_object_id(
-+ le16_to_cpu(object->usObjectID));
-+ if (OBJECT_TYPE_CONNECTOR == object_id.type)
-+ object->usObjectID = cpu_to_le16(0);
-+ }
-+
-+ return BP_RESULT_OK;
-+ }
-+
-+ dal_logger_write(bp->ctx->logger,
-+ LOG_MAJOR_BIOS,
-+ LOG_MINOR_BIOS_CMD_TABLE,
-+ "%s: Failed to read Connection Info Table", __func__);
-+ return BP_RESULT_UNSUPPORTED;
-+ }
-+
-+ /* Get pointer to AUX/DDC and HPD LUTs */
-+ aux_ddc_lut_record =
-+ get_ext_connector_aux_ddc_lut_record(bp, opm_object);
-+ hpd_pin_lut_record =
-+ get_ext_connector_hpd_pin_lut_record(bp, opm_object);
-+
-+ if ((aux_ddc_lut_record == NULL) || (hpd_pin_lut_record == NULL))
-+ return BP_RESULT_UNSUPPORTED;
-+
-+ /* Cache support bits for currently unmapped device types. */
-+ if (bp->remap_device_tags) {
-+ for (i = 0; i < connector_tbl->ucNumberOfObjects; ++i) {
-+ uint32_t j;
-+ /* Remove support for all non-MXM connectors. */
-+ object = &connector_tbl->asObjects[i];
-+ object_id = object_id_from_bios_object_id(
-+ le16_to_cpu(object->usObjectID));
-+ if ((OBJECT_TYPE_CONNECTOR != object_id.type) ||
-+ (CONNECTOR_ID_MXM == object_id.id))
-+ continue;
-+
-+ /* Remove support for all device tags. */
-+ if (dal_bios_parser_get_device_tag_record(
-+ bp, object, &dev_tag_record) != BP_RESULT_OK)
-+ continue;
-+
-+ for (j = 0; j < dev_tag_record->ucNumberOfDevice; ++j) {
-+ ATOM_CONNECTOR_DEVICE_TAG *device_tag =
-+ &dev_tag_record->asDeviceTag[j];
-+ cached_device_support &=
-+ ~le16_to_cpu(device_tag->usDeviceID);
-+ }
-+ }
-+ }
-+
-+ /* Find all MXM connector objects and patch them with connector info
-+ * from the external display connection info table. */
-+ for (i = 0; i < connector_tbl->ucNumberOfObjects; i++) {
-+ uint32_t j;
-+
-+ object = &connector_tbl->asObjects[i];
-+ object_id = object_id_from_bios_object_id(le16_to_cpu(object->usObjectID));
-+ if ((OBJECT_TYPE_CONNECTOR != object_id.type) ||
-+ (CONNECTOR_ID_MXM != object_id.id))
-+ continue;
-+
-+ /* Get the correct connection info table entry based on the enum
-+ * id. */
-+ ext_display_path = get_ext_display_path_entry(
-+ &ext_display_connection_info_tbl,
-+ le16_to_cpu(object->usObjectID));
-+ if (!ext_display_path)
-+ return BP_RESULT_FAILURE;
-+
-+ /* Patch device connector ID */
-+ object->usObjectID =
-+ cpu_to_le16(le16_to_cpu(ext_display_path->usDeviceConnector));
-+
-+ /* Patch device tag, ulACPIDeviceEnum. */
-+ add_device_tag_from_ext_display_path(
-+ bp,
-+ object,
-+ ext_display_path,
-+ &cached_device_support);
-+
-+ /* Patch HPD info */
-+ if (ext_display_path->ucExtHPDPINLutIndex <
-+ MAX_NUMBER_OF_EXT_HPDPIN_LUT_ENTRIES) {
-+ hpd_record = get_hpd_record(bp, object);
-+ if (hpd_record) {
-+ uint8_t index =
-+ ext_display_path->ucExtHPDPINLutIndex;
-+ hpd_record->ucHPDIntGPIOID =
-+ hpd_pin_lut_record->ucHPDPINMap[index];
-+ } else {
-+ BREAK_TO_DEBUGGER();
-+ /* Invalid hpd record */
-+ return BP_RESULT_FAILURE;
-+ }
-+ }
-+
-+ /* Patch I2C/AUX info */
-+ if (ext_display_path->ucExtHPDPINLutIndex <
-+ MAX_NUMBER_OF_EXT_AUXDDC_LUT_ENTRIES) {
-+ i2c_record = get_i2c_record(bp, object);
-+ if (i2c_record) {
-+ uint8_t index =
-+ ext_display_path->ucExtAUXDDCLutIndex;
-+ i2c_record->sucI2cId =
-+ aux_ddc_lut_record->ucAUXDDCMap[index];
-+ } else {
-+ BREAK_TO_DEBUGGER();
-+ /* Invalid I2C record */
-+ return BP_RESULT_FAILURE;
-+ }
-+ }
-+
-+ /* Merge with other MXM connectors that map to the same physical
-+ * connector. */
-+ for (j = i + 1;
-+ j < connector_tbl->ucNumberOfObjects; j++) {
-+ ATOM_OBJECT *next_object;
-+ struct graphics_object_id next_object_id;
-+ EXT_DISPLAY_PATH *next_ext_display_path;
-+
-+ next_object = &connector_tbl->asObjects[j];
-+ next_object_id = object_id_from_bios_object_id(
-+ le16_to_cpu(next_object->usObjectID));
-+
-+ if ((OBJECT_TYPE_CONNECTOR != next_object_id.type) &&
-+ (CONNECTOR_ID_MXM == next_object_id.id))
-+ continue;
-+
-+ next_ext_display_path = get_ext_display_path_entry(
-+ &ext_display_connection_info_tbl,
-+ le16_to_cpu(next_object->usObjectID));
-+
-+ if (next_ext_display_path == NULL)
-+ return BP_RESULT_FAILURE;
-+
-+ /* Merge if using same connector. */
-+ if ((le16_to_cpu(next_ext_display_path->usDeviceConnector) ==
-+ le16_to_cpu(ext_display_path->usDeviceConnector)) &&
-+ (le16_to_cpu(ext_display_path->usDeviceConnector) != 0)) {
-+ /* Clear duplicate connector from table. */
-+ next_object->usObjectID = cpu_to_le16(0);
-+ add_device_tag_from_ext_display_path(
-+ bp,
-+ object,
-+ ext_display_path,
-+ &cached_device_support);
-+ }
-+ }
-+ }
-+
-+ /* Find all encoders which have an MXM object as their destination.
-+ * Replace the MXM object with the real connector Id from the external
-+ * display connection info table */
-+
-+ encoder_table_offset = bp->object_info_tbl_offset
-+ + le16_to_cpu(bp->object_info_tbl.v1_1->usEncoderObjectTableOffset);
-+ encoder_table = GET_IMAGE(ATOM_OBJECT_TABLE, encoder_table_offset);
-+
-+ for (i = 0; i < encoder_table->ucNumberOfObjects; i++) {
-+ uint32_t j;
-+
-+ object = &encoder_table->asObjects[i];
-+
-+ dst_number = get_dest_obj_list(bp, object, &dst_object_id_list);
-+
-+ for (j = 0; j < dst_number; j++) {
-+ object_id = object_id_from_bios_object_id(
-+ dst_object_id_list[j]);
-+
-+ if ((OBJECT_TYPE_CONNECTOR != object_id.type) ||
-+ (CONNECTOR_ID_MXM != object_id.id))
-+ continue;
-+
-+ /* Get the correct connection info table entry based on
-+ * the enum id. */
-+ ext_display_path =
-+ get_ext_display_path_entry(
-+ &ext_display_connection_info_tbl,
-+ dst_object_id_list[j]);
-+
-+ if (ext_display_path == NULL)
-+ return BP_RESULT_FAILURE;
-+
-+ dst_object_id_list[j] =
-+ le16_to_cpu(ext_display_path->usDeviceConnector);
-+ }
-+ }
-+
-+ return BP_RESULT_OK;
-+}
-+
-+/*
-+ * Check whether we need to patch the VBIOS connector info table with
-+ * data from an external display connection info table. This is
-+ * necessary to support MXM boards with an OPM (output personality
-+ * module). With these designs, the VBIOS connector info table
-+ * specifies an MXM_CONNECTOR with a unique ID. The driver retrieves
-+ * the external connection info table through i2c and then looks up the
-+ * connector ID to find the real connector type (e.g. DFP1).
-+ *
-+ */
-+
-+static void process_ext_display_connection_info(struct bios_parser *bp)
-+{
-+ ATOM_OBJECT_TABLE *connector_tbl;
-+ uint32_t connector_tbl_offset;
-+ struct graphics_object_id object_id;
-+ ATOM_OBJECT *object;
-+ bool mxm_connector_found = false;
-+ bool null_entry_found = false;
-+ uint32_t i = 0;
-+
-+ connector_tbl_offset = bp->object_info_tbl_offset +
-+ le16_to_cpu(bp->object_info_tbl.v1_1->usConnectorObjectTableOffset);
-+ connector_tbl = GET_IMAGE(ATOM_OBJECT_TABLE, connector_tbl_offset);
-+
-+ /* Look for MXM connectors to determine whether we need patch the VBIOS
-+ * connector info table. Look for null entries to determine whether we
-+ * need to compact connector table. */
-+ for (i = 0; i < connector_tbl->ucNumberOfObjects; i++) {
-+ object = &connector_tbl->asObjects[i];
-+ object_id = object_id_from_bios_object_id(le16_to_cpu(object->usObjectID));
-+
-+ if ((OBJECT_TYPE_CONNECTOR == object_id.type) &&
-+ (CONNECTOR_ID_MXM == object_id.id)) {
-+ /* Once we found MXM connector - we can break */
-+ mxm_connector_found = true;
-+ break;
-+ } else if (OBJECT_TYPE_CONNECTOR != object_id.type) {
-+ /* We need to continue looping - to check if MXM
-+ * connector present */
-+ null_entry_found = true;
-+ }
-+ }
-+
-+ /* Patch BIOS image */
-+ if (mxm_connector_found || null_entry_found) {
-+ uint32_t connectors_num = 0;
-+ uint8_t *original_bios;
-+ /* Step 1: Replace bios image with the new copy which will be
-+ * patched */
-+ bp->bios_local_image = dc_service_alloc(bp->ctx, bp->bios_size);
-+ if (bp->bios_local_image == NULL) {
-+ BREAK_TO_DEBUGGER();
-+ /* Failed to alloc bp->bios_local_image */
-+ return;
-+ }
-+
-+ dc_service_memmove(bp->bios_local_image, bp->bios, bp->bios_size);
-+ original_bios = bp->bios;
-+ bp->bios = bp->bios_local_image;
-+ connector_tbl =
-+ GET_IMAGE(ATOM_OBJECT_TABLE, connector_tbl_offset);
-+
-+ /* Step 2: (only if MXM connector found) Patch BIOS image with
-+ * info from external module */
-+ if (mxm_connector_found &&
-+ patch_bios_image_from_ext_display_connection_info(bp) !=
-+ BP_RESULT_OK) {
-+ /* Patching the bios image has failed. We will copy
-+ * again original image provided and afterwards
-+ * only remove null entries */
-+ dc_service_memmove(
-+ bp->bios_local_image,
-+ original_bios,
-+ bp->bios_size);
-+ }
-+
-+ /* Step 3: Compact connector table (remove null entries, valid
-+ * entries moved to beginning) */
-+ for (i = 0; i < connector_tbl->ucNumberOfObjects; i++) {
-+ object = &connector_tbl->asObjects[i];
-+ object_id = object_id_from_bios_object_id(
-+ le16_to_cpu(object->usObjectID));
-+
-+ if (OBJECT_TYPE_CONNECTOR != object_id.type)
-+ continue;
-+
-+ if (i != connectors_num) {
-+ dc_service_memmove(
-+ &connector_tbl->
-+ asObjects[connectors_num],
-+ object,
-+ sizeof(ATOM_OBJECT));
-+ }
-+ ++connectors_num;
-+ }
-+ connector_tbl->ucNumberOfObjects = (uint8_t)connectors_num;
-+ }
-+}
-+
-+void dal_bios_parser_post_init(struct bios_parser *bp)
-+{
-+ process_ext_display_connection_info(bp);
-+}
-+
-+bool dal_bios_parser_is_accelerated_mode(
-+ struct bios_parser *bp)
-+{
-+#ifdef CONFIG_DRM_AMD_DAL_VBIOS_PRESENT
-+ return bp->bios_helper->is_accelerated_mode(
-+ bp->ctx);
-+#else
-+ dal_logger_write(bp->ctx->logger,
-+ LOG_MAJOR_BIOS,
-+ LOG_MINOR_BIOS_CMD_TABLE,
-+ "%s: VBIOS is not supported", __func__);
-+ return false;
-+#endif
-+}
-+
-+/**
-+* dal_bios_parser_set_scratch_connected
-+*
-+* @brief
-+* update VBIOS scratch register about connected displays
-+*
-+* @param
-+* bool - update scratch register or just prepare info to be updated
-+* bool - connection state
-+* const ConnectorDeviceTagInfo* - pointer to device type and enum ID
-+*/
-+void dal_bios_parser_set_scratch_connected(
-+ struct bios_parser *bp,
-+ struct graphics_object_id connector_id,
-+ bool connected,
-+ const struct connector_device_tag_info *device_tag)
-+{
-+#ifdef CONFIG_DRM_AMD_DAL_VBIOS_PRESENT
-+ bp->bios_helper->set_scratch_connected(
-+ bp->ctx,
-+ connector_id, connected, device_tag);
-+#else
-+ dal_logger_write(bp->ctx->logger,
-+ LOG_MAJOR_BIOS,
-+ LOG_MINOR_BIOS_CMD_TABLE,
-+ "%s: VBIOS is not supported", __func__);
-+#endif
-+}
-+
-+/**
-+* dal_bios_parser_set_scratch_critical_state
-+*
-+* @brief
-+* update critical state bit in VBIOS scratch register
-+*
-+* @param
-+* bool - to set or reset state
-+*/
-+void dal_bios_parser_set_scratch_critical_state(
-+ struct bios_parser *bp,
-+ bool state)
-+{
-+#ifdef CONFIG_DRM_AMD_DAL_VBIOS_PRESENT
-+ bp->bios_helper->set_scratch_critical_state(
-+ bp->ctx, state);
-+#else
-+ dal_logger_write(bp->ctx->logger,
-+ LOG_MAJOR_BIOS,
-+ LOG_MINOR_BIOS_CMD_TABLE,
-+ "%s: VBIOS is not supported", __func__);
-+#endif
-+}
-+
-+void dal_bios_parser_set_scratch_acc_mode_change(
-+ struct bios_parser *bp)
-+{
-+#ifdef CONFIG_DRM_AMD_DAL_VBIOS_PRESENT
-+ bp->bios_helper->set_scratch_acc_mode_change(
-+ bp->ctx);
-+#else
-+ dal_logger_write(bp->ctx->logger,
-+ LOG_MAJOR_BIOS,
-+ LOG_MINOR_BIOS_CMD_TABLE,
-+ "%s: VBIOS is not supported", __func__);
-+#endif
-+}
-+
-+/**
-+* dal_bios_parser_prepare_scratch_active_and_requested
-+*
-+* @brief
-+* update VBIOS scratch registers about active and requested displays
-+*
-+* @param
-+* enum controller_id - controller Id
-+* enum signal_type signal - signal type used on display
-+* const struct connector_device_tag_info * - pointer to display type and
-+* enum Id
-+*/
-+void dal_bios_parser_prepare_scratch_active_and_requested(
-+ struct bios_parser *bp,
-+ enum controller_id controller_id,
-+ enum signal_type signal,
-+ const struct connector_device_tag_info *device_tag)
-+{
-+#ifdef CONFIG_DRM_AMD_DAL_VBIOS_PRESENT
-+ bp->bios_helper->prepare_scratch_active_and_requested(
-+ bp->ctx,
-+ &bp->vbios_helper_data,
-+ controller_id,
-+ signal,
-+ device_tag);
-+#else
-+ dal_logger_write(bp->ctx->logger,
-+ LOG_MAJOR_BIOS,
-+ LOG_MINOR_BIOS_CMD_TABLE,
-+ "%s: VBIOS is not supported", __func__);
-+#endif
-+}
-+
-+void dal_bios_parser_set_scratch_active_and_requested(
-+ struct bios_parser *bp)
-+{
-+#ifdef CONFIG_DRM_AMD_DAL_VBIOS_PRESENT
-+ bp->bios_helper->set_scratch_active_and_requested(
-+ bp->ctx,
-+ &bp->vbios_helper_data);
-+#else
-+ dal_logger_write(bp->ctx->logger,
-+ LOG_MAJOR_BIOS,
-+ LOG_MINOR_BIOS_CMD_TABLE,
-+ "%s: VBIOS is not supported", __func__);
-+#endif
-+}
-+
-+/*
-+ * get_integrated_info_v8
-+ *
-+ * @brief
-+ * Get V8 integrated BIOS information
-+ *
-+ * @param
-+ * bios_parser *bp - [in]BIOS parser handler to get master data table
-+ * integrated_info *info - [out] store and output integrated info
-+ *
-+ * @return
-+ * enum bp_result - BP_RESULT_OK if information is available,
-+ * BP_RESULT_BADBIOSTABLE otherwise.
-+ */
-+static enum bp_result get_integrated_info_v8(
-+ struct bios_parser *bp,
-+ struct integrated_info *info)
-+{
-+ enum bp_result result = BP_RESULT_BADBIOSTABLE;
-+ ATOM_INTEGRATED_SYSTEM_INFO_V1_8 *info_v8;
-+ uint32_t i;
-+
-+ info_v8 = GET_IMAGE(ATOM_INTEGRATED_SYSTEM_INFO_V1_8,
-+ bp->master_data_tbl->ListOfDataTables.IntegratedSystemInfo);
-+
-+ if (info_v8 != NULL) {
-+ info->boot_up_engine_clock =
-+ le32_to_cpu(info_v8->ulBootUpEngineClock) * 10;
-+ info->dentist_vco_freq =
-+ le32_to_cpu(info_v8->ulDentistVCOFreq) * 10;
-+ info->boot_up_uma_clock =
-+ le32_to_cpu(info_v8->ulBootUpUMAClock) * 10;
-+
-+ for (i = 0; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) {
-+ /* Convert [10KHz] into [KHz] */
-+ info->disp_clk_voltage[i].max_supported_clk =
-+ le32_to_cpu(info_v8->sDISPCLK_Voltage[i].
-+ ulMaximumSupportedCLK) * 10;
-+ info->disp_clk_voltage[i].voltage_index =
-+ le32_to_cpu(info_v8->sDISPCLK_Voltage[i].ulVoltageIndex);
-+ }
-+
-+ info->boot_up_req_display_vector =
-+ le32_to_cpu(info_v8->ulBootUpReqDisplayVector);
-+ info->gpu_cap_info =
-+ le32_to_cpu(info_v8->ulGPUCapInfo);
-+
-+ /*
-+ * system_config: Bit[0] = 0 : PCIE power gating disabled
-+ * = 1 : PCIE power gating enabled
-+ * Bit[1] = 0 : DDR-PLL shut down disabled
-+ * = 1 : DDR-PLL shut down enabled
-+ * Bit[2] = 0 : DDR-PLL power down disabled
-+ * = 1 : DDR-PLL power down enabled
-+ */
-+ info->system_config = le32_to_cpu(info_v8->ulSystemConfig);
-+ info->cpu_cap_info = le32_to_cpu(info_v8->ulCPUCapInfo);
-+ info->boot_up_nb_voltage =
-+ le16_to_cpu(info_v8->usBootUpNBVoltage);
-+ info->ext_disp_conn_info_offset =
-+ le16_to_cpu(info_v8->usExtDispConnInfoOffset);
-+ info->memory_type = info_v8->ucMemoryType;
-+ info->ma_channel_number = info_v8->ucUMAChannelNumber;
-+ info->gmc_restore_reset_time =
-+ le32_to_cpu(info_v8->ulGMCRestoreResetTime);
-+
-+ info->minimum_n_clk =
-+ le32_to_cpu(info_v8->ulNbpStateNClkFreq[0]);
-+ for (i = 1; i < 4; ++i)
-+ info->minimum_n_clk =
-+ info->minimum_n_clk < le32_to_cpu(info_v8->ulNbpStateNClkFreq[i]) ?
-+ info->minimum_n_clk : le32_to_cpu(info_v8->ulNbpStateNClkFreq[i]);
-+
-+ info->idle_n_clk = le32_to_cpu(info_v8->ulIdleNClk);
-+ info->ddr_dll_power_up_time =
-+ le32_to_cpu(info_v8->ulDDR_DLL_PowerUpTime);
-+ info->ddr_pll_power_up_time =
-+ le32_to_cpu(info_v8->ulDDR_PLL_PowerUpTime);
-+ info->pcie_clk_ss_type = le16_to_cpu(info_v8->usPCIEClkSSType);
-+ info->lvds_ss_percentage =
-+ le16_to_cpu(info_v8->usLvdsSSPercentage);
-+ info->lvds_sspread_rate_in_10hz =
-+ le16_to_cpu(info_v8->usLvdsSSpreadRateIn10Hz);
-+ info->hdmi_ss_percentage =
-+ le16_to_cpu(info_v8->usHDMISSPercentage);
-+ info->hdmi_sspread_rate_in_10hz =
-+ le16_to_cpu(info_v8->usHDMISSpreadRateIn10Hz);
-+ info->dvi_ss_percentage =
-+ le16_to_cpu(info_v8->usDVISSPercentage);
-+ info->dvi_sspread_rate_in_10_hz =
-+ le16_to_cpu(info_v8->usDVISSpreadRateIn10Hz);
-+
-+ info->max_lvds_pclk_freq_in_single_link =
-+ le16_to_cpu(info_v8->usMaxLVDSPclkFreqInSingleLink);
-+ info->lvds_misc = info_v8->ucLvdsMisc;
-+ info->lvds_pwr_on_seq_dig_on_to_de_in_4ms =
-+ info_v8->ucLVDSPwrOnSeqDIGONtoDE_in4Ms;
-+ info->lvds_pwr_on_seq_de_to_vary_bl_in_4ms =
-+ info_v8->ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms;
-+ info->lvds_pwr_on_seq_vary_bl_to_blon_in_4ms =
-+ info_v8->ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms;
-+ info->lvds_pwr_off_seq_vary_bl_to_de_in4ms =
-+ info_v8->ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms;
-+ info->lvds_pwr_off_seq_de_to_dig_on_in4ms =
-+ info_v8->ucLVDSPwrOffSeqDEtoDIGON_in4Ms;
-+ info->lvds_pwr_off_seq_blon_to_vary_bl_in_4ms =
-+ info_v8->ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms;
-+ info->lvds_off_to_on_delay_in_4ms =
-+ info_v8->ucLVDSOffToOnDelay_in4Ms;
-+ info->lvds_bit_depth_control_val =
-+ le32_to_cpu(info_v8->ulLCDBitDepthControlVal);
-+
-+ for (i = 0; i < NUMBER_OF_AVAILABLE_SCLK; ++i) {
-+ /* Convert [10KHz] into [KHz] */
-+ info->avail_s_clk[i].supported_s_clk =
-+ le32_to_cpu(info_v8->sAvail_SCLK[i].ulSupportedSCLK) * 10;
-+ info->avail_s_clk[i].voltage_index =
-+ le16_to_cpu(info_v8->sAvail_SCLK[i].usVoltageIndex);
-+ info->avail_s_clk[i].voltage_id =
-+ le16_to_cpu(info_v8->sAvail_SCLK[i].usVoltageID);
-+ }
-+
-+ for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) {
-+ info->ext_disp_conn_info.gu_id[i] =
-+ info_v8->sExtDispConnInfo.ucGuid[i];
-+ }
-+
-+ for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; ++i) {
-+ info->ext_disp_conn_info.path[i].device_connector_id =
-+ object_id_from_bios_object_id(
-+ le16_to_cpu(info_v8->sExtDispConnInfo.sPath[i].usDeviceConnector));
-+
-+ info->ext_disp_conn_info.path[i].ext_encoder_obj_id =
-+ object_id_from_bios_object_id(
-+ le16_to_cpu(info_v8->sExtDispConnInfo.sPath[i].usExtEncoderObjId));
-+
-+ info->ext_disp_conn_info.path[i].device_tag =
-+ le16_to_cpu(info_v8->sExtDispConnInfo.sPath[i].usDeviceTag);
-+ info->ext_disp_conn_info.path[i].device_acpi_enum =
-+ le16_to_cpu(info_v8->sExtDispConnInfo.sPath[i].usDeviceACPIEnum);
-+ info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index =
-+ info_v8->sExtDispConnInfo.sPath[i].ucExtAUXDDCLutIndex;
-+ info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index =
-+ info_v8->sExtDispConnInfo.sPath[i].ucExtHPDPINLutIndex;
-+ info->ext_disp_conn_info.path[i].channel_mapping.raw =
-+ info_v8->sExtDispConnInfo.sPath[i].ucChannelMapping;
-+ }
-+ info->ext_disp_conn_info.checksum =
-+ info_v8->sExtDispConnInfo.ucChecksum;
-+
-+ result = BP_RESULT_OK;
-+ }
-+
-+ return result;
-+}
-+
-+/*
-+ * get_integrated_info_v8
-+ *
-+ * @brief
-+ * Get V8 integrated BIOS information
-+ *
-+ * @param
-+ * bios_parser *bp - [in]BIOS parser handler to get master data table
-+ * integrated_info *info - [out] store and output integrated info
-+ *
-+ * @return
-+ * enum bp_result - BP_RESULT_OK if information is available,
-+ * BP_RESULT_BADBIOSTABLE otherwise.
-+ */
-+static enum bp_result get_integrated_info_v9(
-+ struct bios_parser *bp,
-+ struct integrated_info *info)
-+{
-+ enum bp_result result = BP_RESULT_BADBIOSTABLE;
-+ ATOM_INTEGRATED_SYSTEM_INFO_V1_9 *info_v9;
-+ uint32_t i;
-+
-+ info_v9 = GET_IMAGE(ATOM_INTEGRATED_SYSTEM_INFO_V1_9,
-+ bp->master_data_tbl->ListOfDataTables.IntegratedSystemInfo);
-+
-+ if (info_v9 != NULL) {
-+ info->boot_up_engine_clock =
-+ le32_to_cpu(info_v9->ulBootUpEngineClock) * 10;
-+ info->dentist_vco_freq =
-+ le32_to_cpu(info_v9->ulDentistVCOFreq) * 10;
-+ info->boot_up_uma_clock =
-+ le32_to_cpu(info_v9->ulBootUpUMAClock) * 10;
-+
-+ for (i = 0; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) {
-+ /* Convert [10KHz] into [KHz] */
-+ info->disp_clk_voltage[i].max_supported_clk =
-+ le32_to_cpu(info_v9->sDISPCLK_Voltage[i].ulMaximumSupportedCLK) * 10;
-+ info->disp_clk_voltage[i].voltage_index =
-+ le32_to_cpu(info_v9->sDISPCLK_Voltage[i].ulVoltageIndex);
-+ }
-+
-+ info->boot_up_req_display_vector =
-+ le32_to_cpu(info_v9->ulBootUpReqDisplayVector);
-+ info->gpu_cap_info = le32_to_cpu(info_v9->ulGPUCapInfo);
-+
-+ /*
-+ * system_config: Bit[0] = 0 : PCIE power gating disabled
-+ * = 1 : PCIE power gating enabled
-+ * Bit[1] = 0 : DDR-PLL shut down disabled
-+ * = 1 : DDR-PLL shut down enabled
-+ * Bit[2] = 0 : DDR-PLL power down disabled
-+ * = 1 : DDR-PLL power down enabled
-+ */
-+ info->system_config = le32_to_cpu(info_v9->ulSystemConfig);
-+ info->cpu_cap_info = le32_to_cpu(info_v9->ulCPUCapInfo);
-+ info->boot_up_nb_voltage =
-+ le16_to_cpu(info_v9->usBootUpNBVoltage);
-+ info->ext_disp_conn_info_offset =
-+ le16_to_cpu(info_v9->usExtDispConnInfoOffset);
-+ info->memory_type = info_v9->ucMemoryType;
-+ info->ma_channel_number = info_v9->ucUMAChannelNumber;
-+ info->gmc_restore_reset_time =
-+ le32_to_cpu(info_v9->ulGMCRestoreResetTime);
-+
-+ info->minimum_n_clk =
-+ le32_to_cpu(info_v9->ulNbpStateNClkFreq[0]);
-+ for (i = 1; i < 4; ++i)
-+ info->minimum_n_clk =
-+ info->minimum_n_clk < le32_to_cpu(info_v9->ulNbpStateNClkFreq[i]) ?
-+ info->minimum_n_clk : le32_to_cpu(info_v9->ulNbpStateNClkFreq[i]);
-+
-+ info->idle_n_clk = le32_to_cpu(info_v9->ulIdleNClk);
-+ info->ddr_dll_power_up_time =
-+ le32_to_cpu(info_v9->ulDDR_DLL_PowerUpTime);
-+ info->ddr_pll_power_up_time =
-+ le32_to_cpu(info_v9->ulDDR_PLL_PowerUpTime);
-+ info->pcie_clk_ss_type = le16_to_cpu(info_v9->usPCIEClkSSType);
-+ info->lvds_ss_percentage =
-+ le16_to_cpu(info_v9->usLvdsSSPercentage);
-+ info->lvds_sspread_rate_in_10hz =
-+ le16_to_cpu(info_v9->usLvdsSSpreadRateIn10Hz);
-+ info->hdmi_ss_percentage =
-+ le16_to_cpu(info_v9->usHDMISSPercentage);
-+ info->hdmi_sspread_rate_in_10hz =
-+ le16_to_cpu(info_v9->usHDMISSpreadRateIn10Hz);
-+ info->dvi_ss_percentage =
-+ le16_to_cpu(info_v9->usDVISSPercentage);
-+ info->dvi_sspread_rate_in_10_hz =
-+ le16_to_cpu(info_v9->usDVISSpreadRateIn10Hz);
-+
-+ info->max_lvds_pclk_freq_in_single_link =
-+ le16_to_cpu(info_v9->usMaxLVDSPclkFreqInSingleLink);
-+ info->lvds_misc = info_v9->ucLvdsMisc;
-+ info->lvds_pwr_on_seq_dig_on_to_de_in_4ms =
-+ info_v9->ucLVDSPwrOnSeqDIGONtoDE_in4Ms;
-+ info->lvds_pwr_on_seq_de_to_vary_bl_in_4ms =
-+ info_v9->ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms;
-+ info->lvds_pwr_on_seq_vary_bl_to_blon_in_4ms =
-+ info_v9->ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms;
-+ info->lvds_pwr_off_seq_vary_bl_to_de_in4ms =
-+ info_v9->ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms;
-+ info->lvds_pwr_off_seq_de_to_dig_on_in4ms =
-+ info_v9->ucLVDSPwrOffSeqDEtoDIGON_in4Ms;
-+ info->lvds_pwr_off_seq_blon_to_vary_bl_in_4ms =
-+ info_v9->ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms;
-+ info->lvds_off_to_on_delay_in_4ms =
-+ info_v9->ucLVDSOffToOnDelay_in4Ms;
-+ info->lvds_bit_depth_control_val =
-+ le32_to_cpu(info_v9->ulLCDBitDepthControlVal);
-+
-+ for (i = 0; i < NUMBER_OF_AVAILABLE_SCLK; ++i) {
-+ /* Convert [10KHz] into [KHz] */
-+ info->avail_s_clk[i].supported_s_clk =
-+ le32_to_cpu(info_v9->sAvail_SCLK[i].ulSupportedSCLK) * 10;
-+ info->avail_s_clk[i].voltage_index =
-+ le16_to_cpu(info_v9->sAvail_SCLK[i].usVoltageIndex);
-+ info->avail_s_clk[i].voltage_id =
-+ le16_to_cpu(info_v9->sAvail_SCLK[i].usVoltageID);
-+ }
-+
-+ for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) {
-+ info->ext_disp_conn_info.gu_id[i] =
-+ info_v9->sExtDispConnInfo.ucGuid[i];
-+ }
-+
-+ for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; ++i) {
-+ info->ext_disp_conn_info.path[i].device_connector_id =
-+ object_id_from_bios_object_id(
-+ le16_to_cpu(info_v9->sExtDispConnInfo.sPath[i].usDeviceConnector));
-+
-+ info->ext_disp_conn_info.path[i].ext_encoder_obj_id =
-+ object_id_from_bios_object_id(
-+ le16_to_cpu(info_v9->sExtDispConnInfo.sPath[i].usExtEncoderObjId));
-+
-+ info->ext_disp_conn_info.path[i].device_tag =
-+ le16_to_cpu(info_v9->sExtDispConnInfo.sPath[i].usDeviceTag);
-+ info->ext_disp_conn_info.path[i].device_acpi_enum =
-+ le16_to_cpu(info_v9->sExtDispConnInfo.sPath[i].usDeviceACPIEnum);
-+ info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index =
-+ info_v9->sExtDispConnInfo.sPath[i].ucExtAUXDDCLutIndex;
-+ info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index =
-+ info_v9->sExtDispConnInfo.sPath[i].ucExtHPDPINLutIndex;
-+ info->ext_disp_conn_info.path[i].channel_mapping.raw =
-+ info_v9->sExtDispConnInfo.sPath[i].ucChannelMapping;
-+ }
-+ info->ext_disp_conn_info.checksum =
-+ info_v9->sExtDispConnInfo.ucChecksum;
-+
-+ result = BP_RESULT_OK;
-+ }
-+
-+ return result;
-+}
-+
-+/*
-+ * construct_integrated_info
-+ *
-+ * @brief
-+ * Get integrated BIOS information based on table revision
-+ *
-+ * @param
-+ * bios_parser *bp - [in]BIOS parser handler to get master data table
-+ * integrated_info *info - [out] store and output integrated info
-+ *
-+ * @return
-+ * enum bp_result - BP_RESULT_OK if information is available,
-+ * BP_RESULT_BADBIOSTABLE otherwise.
-+ */
-+static enum bp_result construct_integrated_info(
-+ struct bios_parser *bp,
-+ struct integrated_info *info)
-+{
-+ enum bp_result result = BP_RESULT_BADBIOSTABLE;
-+
-+ ATOM_COMMON_TABLE_HEADER *header;
-+ struct atom_data_revision revision;
-+
-+ if (info != NULL &&
-+ bp->master_data_tbl->ListOfDataTables.IntegratedSystemInfo) {
-+ header = GET_IMAGE(ATOM_COMMON_TABLE_HEADER,
-+ bp->master_data_tbl->ListOfDataTables.IntegratedSystemInfo);
-+
-+ get_atom_data_table_revision(header, &revision);
-+
-+ /* Don't need to check major revision as they are all 1 */
-+ switch (revision.minor) {
-+ case 8:
-+ result = get_integrated_info_v8(bp, info);
-+ break;
-+ case 9:
-+ result = get_integrated_info_v9(bp, info);
-+ break;
-+ default:
-+ return result;
-+
-+ }
-+ }
-+
-+ /* Sort voltage table from low to high*/
-+ if (result == BP_RESULT_OK) {
-+ struct clock_voltage_caps temp = {0, 0};
-+ uint32_t i;
-+ uint32_t j;
-+
-+ for (i = 1; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) {
-+ for (j = i; j > 0; --j) {
-+ if (
-+ info->disp_clk_voltage[j].max_supported_clk <
-+ info->disp_clk_voltage[j-1].max_supported_clk) {
-+ /* swap j and j - 1*/
-+ temp = info->disp_clk_voltage[j-1];
-+ info->disp_clk_voltage[j-1] =
-+ info->disp_clk_voltage[j];
-+ info->disp_clk_voltage[j] = temp;
-+ }
-+ }
-+ }
-+
-+ }
-+
-+ return result;
-+}
-+
-+/*
-+ * dal_bios_parser_create_integrated_info
-+ *
-+ * @brief
-+ * Create integrated info
-+ *
-+ * @param
-+ * bios_parser *bp - [in] BIOS parser handler
-+ *
-+ * @return
-+ * struct integrated_info * - pointer to the newly created integrated info
-+ */
-+struct integrated_info *dal_bios_parser_create_integrated_info(
-+ struct bios_parser *bp)
-+{
-+ struct integrated_info *info = NULL;
-+
-+ info = dc_service_alloc(bp->ctx, sizeof(struct integrated_info));
-+
-+ if (info == NULL) {
-+ ASSERT_CRITICAL(0);
-+ return NULL;
-+ }
-+
-+ if (construct_integrated_info(bp, info) == BP_RESULT_OK)
-+ return info;
-+
-+ dc_service_free(bp->ctx, info);
-+
-+ return NULL;
-+}
-+
-+/*
-+ * dal_bios_parser_destroy_integrated_info
-+ *
-+ * @brief
-+ * Destroy provided integrated info
-+ *
-+ * @param
-+ * struct integrated_info **info - [in] info to be destroied
-+ */
-+void dal_bios_parser_destroy_integrated_info(struct dc_context *ctx, struct integrated_info **info)
-+{
-+ if (info == NULL) {
-+ ASSERT_CRITICAL(0);
-+ return;
-+ }
-+
-+ if (*info != NULL) {
-+ dc_service_free(ctx, *info);
-+ *info = NULL;
-+ }
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.h b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.h
-new file mode 100644
-index 0000000..db169f1
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.h
-@@ -0,0 +1,78 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_BIOS_PARSER_H__
-+#define __DAL_BIOS_PARSER_H__
-+
-+#include "bios_parser_helper.h"
-+
-+struct atom_data_revision {
-+ uint32_t major;
-+ uint32_t minor;
-+};
-+
-+struct object_info_table {
-+ struct atom_data_revision revision;
-+ union {
-+ ATOM_OBJECT_HEADER *v1_1;
-+ ATOM_OBJECT_HEADER_V3 *v1_3;
-+ };
-+};
-+
-+enum spread_spectrum_id {
-+ SS_ID_UNKNOWN = 0,
-+ SS_ID_DP1 = 0xf1,
-+ SS_ID_DP2 = 0xf2,
-+ SS_ID_LVLINK_2700MHZ = 0xf3,
-+ SS_ID_LVLINK_1620MHZ = 0xf4
-+};
-+
-+struct bios_parser {
-+ struct dc_context *ctx;
-+ struct adapter_service *as;
-+
-+ struct object_info_table object_info_tbl;
-+ uint32_t object_info_tbl_offset;
-+ ATOM_MASTER_DATA_TABLE *master_data_tbl;
-+
-+ uint8_t *bios;
-+ uint32_t bios_size;
-+
-+#if defined(CONFIG_DRM_AMD_DAL_VBIOS_PRESENT)
-+ const struct bios_parser_helper *bios_helper;
-+ struct vbios_helper_data vbios_helper_data;
-+#endif /* CONFIG_DRM_AMD_DAL_VBIOS_PRESENT */
-+
-+ const struct command_table_helper *cmd_helper;
-+ struct cmd_tbl cmd_tbl;
-+
-+ uint8_t *bios_local_image;
-+ enum lcd_scale lcd_scale;
-+
-+ bool remap_device_tags;
-+ bool headless_no_opm;
-+};
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.c b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.c
-new file mode 100644
-index 0000000..0089800
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.c
-@@ -0,0 +1,193 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+
-+#include "atom.h"
-+
-+#include "include/bios_parser_types.h"
-+#include "include/adapter_service_types.h"
-+#include "bios_parser_helper.h"
-+#include "command_table_helper.h"
-+#include "command_table.h"
-+#include "bios_parser.h"
-+
-+bool dal_bios_parser_init_bios_helper(
-+ struct bios_parser *bp,
-+ enum dce_version version)
-+{
-+ switch (version) {
-+
-+#if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
-+ case DCE_VERSION_11_0:
-+ bp->bios_helper = dal_bios_parser_helper_dce110_get_table();
-+ return true;
-+
-+#endif
-+ default:
-+ BREAK_TO_DEBUGGER();
-+ return false;
-+ }
-+}
-+
-+bool dal_bios_parser_is_lid_open(
-+ struct bios_parser *bp)
-+{
-+ const struct graphics_object_id encoder = dal_graphics_object_id_init(
-+ ENCODER_ID_INTERNAL_UNIPHY,
-+ ENUM_ID_UNKNOWN,
-+ OBJECT_TYPE_UNKNOWN);
-+ const struct graphics_object_id connector = dal_graphics_object_id_init(
-+ CONNECTOR_ID_LVDS,
-+ ENUM_ID_UNKNOWN,
-+ OBJECT_TYPE_UNKNOWN);
-+
-+ enum signal_type signal;
-+
-+ /* check if VBIOS reported LCD as connected */
-+ signal = bp->bios_helper->detect_sink(bp->ctx,
-+ encoder, connector, SIGNAL_TYPE_LVDS);
-+
-+ if (signal == SIGNAL_TYPE_NONE)
-+ return false;
-+
-+ return bp->bios_helper->is_lid_open(bp->ctx);
-+}
-+
-+bool dal_bios_parser_is_lid_status_changed(
-+ struct bios_parser *bp)
-+{
-+ return bp->bios_helper->is_lid_status_changed(
-+ bp->ctx);
-+}
-+
-+bool dal_bios_parser_is_display_config_changed(
-+ struct bios_parser *bp)
-+{
-+ return bp->bios_helper->is_display_config_changed(
-+ bp->ctx);
-+}
-+
-+/**
-+* dal_bios_parser_set_scratch_lcd_scale
-+*
-+* @brief
-+* update VBIOS scratch pad registers about LCD scale
-+*
-+* @param
-+* bool - to set to full panel mode or aspect-ratio mode
-+*/
-+void dal_bios_parser_set_scratch_lcd_scale(
-+ struct bios_parser *bp,
-+ enum lcd_scale scale)
-+{
-+ bp->bios_helper->set_scratch_lcd_scale(
-+ bp->ctx, scale);
-+}
-+
-+/**
-+* dal_bios_parser_get_scratch_lcd_scale
-+*
-+* @brief
-+* get LCD Scale Mode from VBIOS scratch register
-+*
-+* @param
-+* NONE
-+*/
-+enum lcd_scale dal_bios_parser_get_scratch_lcd_scale(
-+ struct bios_parser *bp)
-+{
-+ return bp->bios_helper->get_scratch_lcd_scale(
-+ bp->ctx);
-+}
-+
-+void dal_bios_parser_get_bios_event_info(
-+ struct bios_parser *bp,
-+ struct bios_event_info *info)
-+{
-+ bp->bios_helper->get_bios_event_info(
-+ bp->ctx, info);
-+}
-+
-+/* ABM related */
-+
-+void dal_bios_parser_update_requested_backlight_level(
-+ struct bios_parser *bp,
-+ uint32_t backlight_8bit)
-+{
-+ bp->bios_helper->update_requested_backlight_level(
-+ bp->ctx,
-+ backlight_8bit);
-+}
-+
-+uint32_t dal_bios_parser_get_requested_backlight_level(
-+ struct bios_parser *bp)
-+{
-+ return bp->bios_helper->get_requested_backlight_level(
-+ bp->ctx);
-+}
-+
-+void dal_bios_parser_take_backlight_control(
-+ struct bios_parser *bp,
-+ bool cntl)
-+{
-+ bp->bios_helper->take_backlight_control(
-+ bp->ctx, cntl);
-+}
-+
-+/**
-+ * dal_bios_parser_is_active_display
-+ * Check video bios active display.
-+ */
-+bool dal_bios_parser_is_active_display(
-+ struct bios_parser *bp,
-+ enum signal_type signal,
-+ const struct connector_device_tag_info *device_tag)
-+{
-+ return bp->bios_helper->is_active_display(
-+ bp->ctx, signal, device_tag);
-+}
-+
-+/**
-+ * dal_bios_parser_get_embedded_display_controller_id
-+ * Get controller ID for embedded display from scratch registers
-+ */
-+enum controller_id dal_bios_parser_get_embedded_display_controller_id(
-+ struct bios_parser *bp)
-+{
-+ return bp->bios_helper->get_embedded_display_controller_id(
-+ bp->ctx);
-+}
-+
-+/**
-+ * dal_bios_parser_get_embedded_display_refresh_rate
-+ * Get refresh rate for embedded display from scratch registers
-+ */
-+uint32_t dal_bios_parser_get_embedded_display_refresh_rate(
-+ struct bios_parser *bp)
-+{
-+ return bp->bios_helper->get_embedded_display_refresh_rate(
-+ bp->ctx);
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.h b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.h
-new file mode 100644
-index 0000000..d0e9de9
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.h
-@@ -0,0 +1,108 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_BIOS_PARSER_HELPER_H__
-+#define __DAL_BIOS_PARSER_HELPER_H__
-+
-+#if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
-+#include "dce110/bios_parser_helper_dce110.h"
-+#endif
-+
-+struct bios_parser;
-+
-+struct vbios_helper_data {
-+ uint32_t active;
-+ uint32_t requested;
-+};
-+
-+struct bios_parser_helper {
-+ enum signal_type (*detect_sink)(
-+ struct dc_context *ctx,
-+ struct graphics_object_id encoder,
-+ struct graphics_object_id connector,
-+ enum signal_type signal);
-+ bool (*is_lid_open)(
-+ struct dc_context *ctx);
-+ bool (*is_lid_status_changed)(
-+ struct dc_context *ctx);
-+ bool (*is_display_config_changed)(
-+ struct dc_context *ctx);
-+ void (*set_scratch_acc_mode_change)(
-+ struct dc_context *ctx);
-+ bool (*is_accelerated_mode)(
-+ struct dc_context *ctx);
-+ void (*set_scratch_critical_state)(
-+ struct dc_context *ctx,
-+ bool state);
-+ void (*prepare_scratch_active_and_requested)(
-+ struct dc_context *ctx,
-+ struct vbios_helper_data *data,
-+ enum controller_id id, enum signal_type s,
-+ const struct connector_device_tag_info *dev_tag);
-+ void (*set_scratch_active_and_requested)(
-+ struct dc_context *ctx,
-+ struct vbios_helper_data *d);
-+ void (*set_scratch_connected)(
-+ struct dc_context *ctx,
-+ struct graphics_object_id id,
-+ bool connected,
-+ const struct connector_device_tag_info *device_tag);
-+ void (*set_scratch_lcd_scale)(
-+ struct dc_context *ctx,
-+ enum lcd_scale lcd_scale_request);
-+ enum lcd_scale (*get_scratch_lcd_scale)(
-+ struct dc_context *ctx);
-+ uint32_t (*fmt_control)(
-+ struct dc_context *ctx,
-+ enum controller_id id, uint32_t *value);
-+ uint32_t (*fmt_bit_depth_control)(
-+ struct dc_context *ctx,
-+ enum controller_id id,
-+ uint32_t *value);
-+ void (*get_bios_event_info)(
-+ struct dc_context *ctx,
-+ struct bios_event_info *info);
-+ void (*take_backlight_control)(
-+ struct dc_context *ctx, bool control);
-+ uint32_t (*get_requested_backlight_level)(
-+ struct dc_context *ctx);
-+ void (*update_requested_backlight_level)(
-+ struct dc_context *ctx,
-+ uint32_t backlight_8bit);
-+ bool (*is_active_display)(
-+ struct dc_context *ctx,
-+ enum signal_type signal,
-+ const struct connector_device_tag_info *dev_tag);
-+ enum controller_id (*get_embedded_display_controller_id)(
-+ struct dc_context *ctx);
-+ uint32_t (*get_embedded_display_refresh_rate)(
-+ struct dc_context *ctx);
-+};
-+
-+bool dal_bios_parser_init_bios_helper(
-+ struct bios_parser *bp,
-+ enum dce_version ver);
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/command_table.c b/drivers/gpu/drm/amd/dal/dc/bios/command_table.c
-new file mode 100644
-index 0000000..a807ab6
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/command_table.c
-@@ -0,0 +1,2616 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+
-+#include "atom.h"
-+
-+#include "include/bios_parser_interface.h"
-+
-+#include "command_table.h"
-+#include "command_table_helper.h"
-+#include "bios_parser_helper.h"
-+#include "bios_parser.h"
-+
-+#define EXEC_BIOS_CMD_TABLE(command, params)\
-+ (cgs_atom_exec_cmd_table(bp->ctx->cgs_device, \
-+ GetIndexIntoMasterTable(COMMAND, command), \
-+ &params) == 0)
-+
-+#define BIOS_CMD_TABLE_REVISION(command, frev, crev)\
-+ cgs_atom_get_cmd_table_revs(bp->ctx->cgs_device, \
-+ GetIndexIntoMasterTable(COMMAND, command), &frev, &crev)
-+
-+#define BIOS_CMD_TABLE_PARA_REVISION(command)\
-+ dal_bios_cmd_table_para_revision(bp->ctx, \
-+ GetIndexIntoMasterTable(COMMAND, command))
-+
-+
-+static void init_dig_encoder_control(struct bios_parser *bp);
-+static void init_dvo_encoder_control(struct bios_parser *bp);
-+static void init_transmitter_control(struct bios_parser *bp);
-+static void init_set_pixel_clock(struct bios_parser *bp);
-+static void init_enable_spread_spectrum_on_ppll(struct bios_parser *bp);
-+static void init_adjust_display_pll(struct bios_parser *bp);
-+static void init_dac_encoder_control(struct bios_parser *bp);
-+static void init_dac_output_control(struct bios_parser *bp);
-+static void init_dac_load_detection(struct bios_parser *bp);
-+static void init_blank_crtc(struct bios_parser *bp);
-+static void init_set_crtc_timing(struct bios_parser *bp);
-+static void init_set_crtc_overscan(struct bios_parser *bp);
-+static void init_select_crtc_source(struct bios_parser *bp);
-+static void init_enable_crtc(struct bios_parser *bp);
-+static void init_enable_crtc_mem_req(struct bios_parser *bp);
-+static void init_compute_memore_engine_pll(struct bios_parser *bp);
-+static void init_external_encoder_control(struct bios_parser *bp);
-+static void init_enable_disp_power_gating(struct bios_parser *bp);
-+static void init_program_clock(struct bios_parser *bp);
-+
-+void dal_bios_parser_init_cmd_tbl(struct bios_parser *bp)
-+{
-+ init_dig_encoder_control(bp);
-+ init_dvo_encoder_control(bp);
-+ init_transmitter_control(bp);
-+ init_set_pixel_clock(bp);
-+ init_enable_spread_spectrum_on_ppll(bp);
-+ init_adjust_display_pll(bp);
-+ init_dac_encoder_control(bp);
-+ init_dac_output_control(bp);
-+ init_dac_load_detection(bp);
-+ init_blank_crtc(bp);
-+ init_set_crtc_timing(bp);
-+ init_set_crtc_overscan(bp);
-+ init_select_crtc_source(bp);
-+ init_enable_crtc(bp);
-+ init_enable_crtc_mem_req(bp);
-+ init_program_clock(bp);
-+ init_compute_memore_engine_pll(bp);
-+ init_external_encoder_control(bp);
-+ init_enable_disp_power_gating(bp);
-+}
-+
-+/*******************************************************************************
-+********************************************************************************
-+**
-+** D I G E N C O D E R C O N T R O L
-+**
-+********************************************************************************
-+*******************************************************************************/
-+static enum bp_result encoder_control_digx_v3(
-+ struct bios_parser *bp,
-+ struct bp_encoder_control *cntl);
-+
-+static enum bp_result encoder_control_digx_v4(
-+ struct bios_parser *bp,
-+ struct bp_encoder_control *cntl);
-+static void init_encoder_control_dig_v1(struct bios_parser *bp);
-+
-+static void init_dig_encoder_control(struct bios_parser *bp)
-+{
-+ uint32_t version =
-+ BIOS_CMD_TABLE_PARA_REVISION(DIGxEncoderControl);
-+
-+ switch (version) {
-+ case 4:
-+ bp->cmd_tbl.dig_encoder_control = encoder_control_digx_v4;
-+ break;
-+ case 2:
-+ bp->cmd_tbl.dig_encoder_control = encoder_control_digx_v3;
-+ break;
-+ default:
-+ init_encoder_control_dig_v1(bp);
-+ break;
-+ }
-+}
-+
-+static enum bp_result encoder_control_dig_v1(
-+ struct bios_parser *bp,
-+ struct bp_encoder_control *cntl);
-+static enum bp_result encoder_control_dig1_v1(
-+ struct bios_parser *bp,
-+ struct bp_encoder_control *cntl);
-+static enum bp_result encoder_control_dig2_v1(
-+ struct bios_parser *bp,
-+ struct bp_encoder_control *cntl);
-+
-+static void init_encoder_control_dig_v1(struct bios_parser *bp)
-+{
-+ struct cmd_tbl *cmd_tbl = &bp->cmd_tbl;
-+
-+ if (1 == BIOS_CMD_TABLE_PARA_REVISION(DIG1EncoderControl))
-+ cmd_tbl->encoder_control_dig1 = encoder_control_dig1_v1;
-+ else
-+ cmd_tbl->encoder_control_dig1 = NULL;
-+
-+ if (1 == BIOS_CMD_TABLE_PARA_REVISION(DIG2EncoderControl))
-+ cmd_tbl->encoder_control_dig2 = encoder_control_dig2_v1;
-+ else
-+ cmd_tbl->encoder_control_dig2 = NULL;
-+
-+ cmd_tbl->dig_encoder_control = encoder_control_dig_v1;
-+}
-+
-+static enum bp_result encoder_control_dig_v1(
-+ struct bios_parser *bp,
-+ struct bp_encoder_control *cntl)
-+{
-+ enum bp_result result = BP_RESULT_FAILURE;
-+ struct cmd_tbl *cmd_tbl = &bp->cmd_tbl;
-+
-+ if (cntl != NULL)
-+ switch (cntl->engine_id) {
-+ case ENGINE_ID_DIGA:
-+ if (cmd_tbl->encoder_control_dig1 != NULL)
-+ result =
-+ cmd_tbl->encoder_control_dig1(bp, cntl);
-+ break;
-+ case ENGINE_ID_DIGB:
-+ if (cmd_tbl->encoder_control_dig2 != NULL)
-+ result =
-+ cmd_tbl->encoder_control_dig2(bp, cntl);
-+ break;
-+
-+ default:
-+ break;
-+ }
-+
-+ return result;
-+}
-+
-+static enum bp_result encoder_control_dig1_v1(
-+ struct bios_parser *bp,
-+ struct bp_encoder_control *cntl)
-+{
-+ enum bp_result result = BP_RESULT_FAILURE;
-+ DIG_ENCODER_CONTROL_PARAMETERS_V2 params = {0};
-+
-+ bp->cmd_helper->assign_control_parameter(bp->cmd_helper, cntl, &params);
-+
-+ if (EXEC_BIOS_CMD_TABLE(DIG1EncoderControl, params))
-+ result = BP_RESULT_OK;
-+
-+ return result;
-+}
-+
-+static enum bp_result encoder_control_dig2_v1(
-+ struct bios_parser *bp,
-+ struct bp_encoder_control *cntl)
-+{
-+ enum bp_result result = BP_RESULT_FAILURE;
-+ DIG_ENCODER_CONTROL_PARAMETERS_V2 params = {0};
-+
-+ bp->cmd_helper->assign_control_parameter(bp->cmd_helper, cntl, &params);
-+
-+ if (EXEC_BIOS_CMD_TABLE(DIG2EncoderControl, params))
-+ result = BP_RESULT_OK;
-+
-+ return result;
-+}
-+
-+static enum bp_result encoder_control_digx_v3(
-+ struct bios_parser *bp,
-+ struct bp_encoder_control *cntl)
-+{
-+ enum bp_result result = BP_RESULT_FAILURE;
-+ DIG_ENCODER_CONTROL_PARAMETERS_V3 params = {0};
-+
-+ if (LANE_COUNT_FOUR < cntl->lanes_number)
-+ params.acConfig.ucDPLinkRate = 1; /* dual link 2.7GHz */
-+ else
-+ params.acConfig.ucDPLinkRate = 0; /* single link 1.62GHz */
-+
-+ params.acConfig.ucDigSel = (uint8_t)(cntl->engine_id);
-+
-+ /* We need to convert from KHz units into 10KHz units */
-+ params.ucAction = bp->cmd_helper->encoder_action_to_atom(cntl->action);
-+ params.usPixelClock = cpu_to_le16((uint16_t)(cntl->pixel_clock / 10));
-+ params.ucEncoderMode =
-+ (uint8_t)bp->cmd_helper->encoder_mode_bp_to_atom(
-+ cntl->signal,
-+ cntl->enable_dp_audio);
-+ params.ucLaneNum = (uint8_t)(cntl->lanes_number);
-+
-+ if (cntl->signal == SIGNAL_TYPE_HDMI_TYPE_A)
-+ switch (cntl->color_depth) {
-+ case COLOR_DEPTH_101010:
-+ params.usPixelClock =
-+ cpu_to_le16((le32_to_cpu(params.usPixelClock) * 30) / 24);
-+ break;
-+ case COLOR_DEPTH_121212:
-+ params.usPixelClock =
-+ cpu_to_le16((le32_to_cpu(params.usPixelClock) * 36) / 24);
-+ break;
-+ case COLOR_DEPTH_161616:
-+ params.usPixelClock =
-+ cpu_to_le16((le32_to_cpu(params.usPixelClock) * 48) / 24);
-+ break;
-+ default:
-+ break;
-+ }
-+
-+ if (EXEC_BIOS_CMD_TABLE(DIGxEncoderControl, params))
-+ result = BP_RESULT_OK;
-+
-+ return result;
-+}
-+
-+static enum bp_result encoder_control_digx_v4(
-+ struct bios_parser *bp,
-+ struct bp_encoder_control *cntl)
-+{
-+ enum bp_result result = BP_RESULT_FAILURE;
-+ DIG_ENCODER_CONTROL_PARAMETERS_V4 params = {0};
-+
-+ if (LANE_COUNT_FOUR < cntl->lanes_number)
-+ params.acConfig.ucDPLinkRate = 1; /* dual link 2.7GHz */
-+ else
-+ params.acConfig.ucDPLinkRate = 0; /* single link 1.62GHz */
-+
-+
-+ params.acConfig.ucDigSel = (uint8_t)(cntl->engine_id);
-+
-+ /* We need to convert from KHz units into 10KHz units */
-+ params.ucAction = bp->cmd_helper->encoder_action_to_atom(cntl->action);
-+ params.usPixelClock = cpu_to_le16((uint16_t)(cntl->pixel_clock / 10));
-+ params.ucEncoderMode =
-+ (uint8_t)(bp->cmd_helper->encoder_mode_bp_to_atom(
-+ cntl->signal,
-+ cntl->enable_dp_audio));
-+ params.ucLaneNum = (uint8_t)(cntl->lanes_number);
-+
-+ if (cntl->signal == SIGNAL_TYPE_HDMI_TYPE_A)
-+ switch (cntl->color_depth) {
-+ case COLOR_DEPTH_101010:
-+ params.usPixelClock =
-+ cpu_to_le16((le32_to_cpu(params.usPixelClock) * 30) / 24);
-+ break;
-+ case COLOR_DEPTH_121212:
-+ params.usPixelClock =
-+ cpu_to_le16((le32_to_cpu(params.usPixelClock) * 36) / 24);
-+ break;
-+ case COLOR_DEPTH_161616:
-+ params.usPixelClock =
-+ cpu_to_le16((le32_to_cpu(params.usPixelClock) * 48) / 24);
-+ break;
-+ default:
-+ break;
-+ }
-+
-+ if (EXEC_BIOS_CMD_TABLE(DIGxEncoderControl, params))
-+ result = BP_RESULT_OK;
-+
-+ return result;
-+}
-+
-+/*******************************************************************************
-+********************************************************************************
-+**
-+** DVO ENCODER CONTROL
-+**
-+********************************************************************************
-+*******************************************************************************/
-+
-+static enum bp_result dvo_encoder_control_v3(
-+ struct bios_parser *bp,
-+ struct bp_dvo_encoder_control *cntl);
-+
-+static void init_dvo_encoder_control(struct bios_parser *bp)
-+{
-+ switch (BIOS_CMD_TABLE_PARA_REVISION(DVOEncoderControl)) {
-+ case 3:
-+ bp->cmd_tbl.dvo_encoder_control = dvo_encoder_control_v3;
-+ break;
-+ default:
-+ bp->cmd_tbl.dvo_encoder_control = NULL;
-+ break;
-+ }
-+}
-+
-+static enum bp_result dvo_encoder_control_v3(
-+ struct bios_parser *bp,
-+ struct bp_dvo_encoder_control *cntl)
-+{
-+ enum bp_result result = BP_RESULT_FAILURE;
-+ DVO_ENCODER_CONTROL_PARAMETERS_V3 params;
-+ uint8_t config = 0;
-+
-+ if (cntl->memory_rate == DVO_ENCODER_MEMORY_RATE_SDR)
-+ config |= DVO_ENCODER_CONFIG_SDR_SPEED;
-+
-+ switch (cntl->interface_width) {
-+ case DVO_ENCODER_INTERFACE_WIDTH_FULL24BIT:
-+ config |= DVO_ENCODER_CONFIG_24BIT;
-+ break;
-+ case DVO_ENCODER_INTERFACE_WIDTH_HIGH12BIT:
-+ config |= DVO_ENCODER_CONFIG_UPPER12BIT;
-+ break;
-+ default:
-+ config |= DVO_ENCODER_CONFIG_LOW12BIT;
-+ break;
-+ }
-+
-+ /* We need to convert from KHz units into 10KHz units */
-+ dc_service_memset(&params, 0, sizeof(params));
-+ params.ucAction = (uint8_t) cntl->action;
-+ params.usPixelClock = cpu_to_le16((uint16_t) (cntl->pixel_clock / 10));
-+ params.ucDVOConfig = config;
-+
-+ if (EXEC_BIOS_CMD_TABLE(DVOEncoderControl, params))
-+ result = BP_RESULT_OK;
-+
-+ return result;
-+}
-+
-+/*******************************************************************************
-+********************************************************************************
-+**
-+** TRANSMITTER CONTROL
-+**
-+********************************************************************************
-+*******************************************************************************/
-+
-+static enum bp_result transmitter_control_v2(
-+ struct bios_parser *bp,
-+ struct bp_transmitter_control *cntl);
-+static enum bp_result transmitter_control_v3(
-+ struct bios_parser *bp,
-+ struct bp_transmitter_control *cntl);
-+static enum bp_result transmitter_control_v4(
-+ struct bios_parser *bp,
-+ struct bp_transmitter_control *cntl);
-+static enum bp_result transmitter_control_v1_5(
-+ struct bios_parser *bp,
-+ struct bp_transmitter_control *cntl);
-+
-+static void init_transmitter_control(struct bios_parser *bp)
-+{
-+ uint8_t frev;
-+ uint8_t crev;
-+
-+ if (BIOS_CMD_TABLE_REVISION(UNIPHYTransmitterControl,
-+ frev, crev) != 0)
-+ BREAK_TO_DEBUGGER();
-+ switch (crev) {
-+ case 2:
-+ bp->cmd_tbl.transmitter_control = transmitter_control_v2;
-+ break;
-+ case 3:
-+ bp->cmd_tbl.transmitter_control = transmitter_control_v3;
-+ break;
-+ case 4:
-+ bp->cmd_tbl.transmitter_control = transmitter_control_v4;
-+ break;
-+ case 5:
-+ bp->cmd_tbl.transmitter_control = transmitter_control_v1_5;
-+ break;
-+ default:
-+ bp->cmd_tbl.transmitter_control = NULL;
-+ break;
-+ }
-+}
-+
-+static enum bp_result transmitter_control_v2(
-+ struct bios_parser *bp,
-+ struct bp_transmitter_control *cntl)
-+{
-+ enum bp_result result = BP_RESULT_FAILURE;
-+ DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 params;
-+ enum connector_id connector_id =
-+ dal_graphics_object_id_get_connector_id(cntl->connector_obj_id);
-+
-+ dc_service_memset(&params, 0, sizeof(params));
-+
-+ switch (cntl->transmitter) {
-+ case TRANSMITTER_UNIPHY_A:
-+ case TRANSMITTER_UNIPHY_B:
-+ case TRANSMITTER_UNIPHY_C:
-+ case TRANSMITTER_UNIPHY_D:
-+ case TRANSMITTER_UNIPHY_E:
-+ case TRANSMITTER_UNIPHY_F:
-+ case TRANSMITTER_TRAVIS_LCD:
-+ break;
-+ default:
-+ return BP_RESULT_BADINPUT;
-+ }
-+
-+ switch (cntl->action) {
-+ case TRANSMITTER_CONTROL_INIT:
-+ if ((CONNECTOR_ID_DUAL_LINK_DVII == connector_id) ||
-+ (CONNECTOR_ID_DUAL_LINK_DVID == connector_id))
-+ /* on INIT this bit should be set according to the
-+ * phisycal connector
-+ * Bit0: dual link connector flag
-+ * =0 connector is single link connector
-+ * =1 connector is dual link connector
-+ */
-+ params.acConfig.fDualLinkConnector = 1;
-+
-+ /* connector object id */
-+ params.usInitInfo =
-+ cpu_to_le16((uint8_t)cntl->connector_obj_id.id);
-+ break;
-+ case TRANSMITTER_CONTROL_SET_VOLTAGE_AND_PREEMPASIS:
-+ /* votage swing and pre-emphsis */
-+ params.asMode.ucLaneSel = (uint8_t)cntl->lane_select;
-+ params.asMode.ucLaneSet = (uint8_t)cntl->lane_settings;
-+ break;
-+ default:
-+ /* if dual-link */
-+ if (LANE_COUNT_FOUR < cntl->lanes_number) {
-+ /* on ENABLE/DISABLE this bit should be set according to
-+ * actual timing (number of lanes)
-+ * Bit0: dual link connector flag
-+ * =0 connector is single link connector
-+ * =1 connector is dual link connector
-+ */
-+ params.acConfig.fDualLinkConnector = 1;
-+
-+ /* link rate, half for dual link
-+ * We need to convert from KHz units into 20KHz units
-+ */
-+ params.usPixelClock =
-+ cpu_to_le16((uint16_t)(cntl->pixel_clock / 20));
-+ } else
-+ /* link rate, half for dual link
-+ * We need to convert from KHz units into 10KHz units
-+ */
-+ params.usPixelClock =
-+ cpu_to_le16((uint16_t)(cntl->pixel_clock / 10));
-+ break;
-+ }
-+
-+ /* 00 - coherent mode
-+ * 01 - incoherent mode
-+ */
-+
-+ params.acConfig.fCoherentMode = cntl->coherent;
-+
-+ if ((TRANSMITTER_UNIPHY_B == cntl->transmitter)
-+ || (TRANSMITTER_UNIPHY_D == cntl->transmitter)
-+ || (TRANSMITTER_UNIPHY_F == cntl->transmitter))
-+ /* Bit2: Transmitter Link selection
-+ * =0 when bit0=0, single link A/C/E, when bit0=1,
-+ * master link A/C/E
-+ * =1 when bit0=0, single link B/D/F, when bit0=1,
-+ * master link B/D/F
-+ */
-+ params.acConfig.ucLinkSel = 1;
-+
-+ if (ENGINE_ID_DIGB == cntl->engine_id)
-+ /* Bit3: Transmitter data source selection
-+ * =0 DIGA is data source.
-+ * =1 DIGB is data source.
-+ * This bit is only useful when ucAction= ATOM_ENABLE
-+ */
-+ params.acConfig.ucEncoderSel = 1;
-+
-+ if (CONNECTOR_ID_DISPLAY_PORT == connector_id)
-+ /* Bit4: DP connector flag
-+ * =0 connector is none-DP connector
-+ * =1 connector is DP connector
-+ */
-+ params.acConfig.fDPConnector = 1;
-+
-+ /* Bit[7:6]: Transmitter selection
-+ * =0 UNIPHY_ENCODER: UNIPHYA/B
-+ * =1 UNIPHY1_ENCODER: UNIPHYC/D
-+ * =2 UNIPHY2_ENCODER: UNIPHYE/F
-+ * =3 reserved
-+ */
-+ params.acConfig.ucTransmitterSel =
-+ (uint8_t)bp->cmd_helper->transmitter_bp_to_atom(
-+ cntl->transmitter);
-+
-+ params.ucAction = (uint8_t)cntl->action;
-+
-+ if (EXEC_BIOS_CMD_TABLE(UNIPHYTransmitterControl, params))
-+ result = BP_RESULT_OK;
-+
-+ return result;
-+}
-+
-+static enum bp_result transmitter_control_v3(
-+ struct bios_parser *bp,
-+ struct bp_transmitter_control *cntl)
-+{
-+ enum bp_result result = BP_RESULT_FAILURE;
-+ DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 params;
-+ uint32_t pll_id;
-+ enum connector_id conn_id =
-+ dal_graphics_object_id_get_connector_id(cntl->connector_obj_id);
-+ const struct command_table_helper *cmd = bp->cmd_helper;
-+ bool dual_link_conn = (CONNECTOR_ID_DUAL_LINK_DVII == conn_id)
-+ || (CONNECTOR_ID_DUAL_LINK_DVID == conn_id);
-+
-+ dc_service_memset(&params, 0, sizeof(params));
-+
-+ switch (cntl->transmitter) {
-+ case TRANSMITTER_UNIPHY_A:
-+ case TRANSMITTER_UNIPHY_B:
-+ case TRANSMITTER_UNIPHY_C:
-+ case TRANSMITTER_UNIPHY_D:
-+ case TRANSMITTER_UNIPHY_E:
-+ case TRANSMITTER_UNIPHY_F:
-+ case TRANSMITTER_TRAVIS_LCD:
-+ break;
-+ default:
-+ return BP_RESULT_BADINPUT;
-+ }
-+
-+ if (!cmd->clock_source_id_to_atom(cntl->pll_id, &pll_id))
-+ return BP_RESULT_BADINPUT;
-+
-+ /* fill information based on the action */
-+ switch (cntl->action) {
-+ case TRANSMITTER_CONTROL_INIT:
-+ if (dual_link_conn) {
-+ /* on INIT this bit should be set according to the
-+ * phisycal connector
-+ * Bit0: dual link connector flag
-+ * =0 connector is single link connector
-+ * =1 connector is dual link connector
-+ */
-+ params.acConfig.fDualLinkConnector = 1;
-+ }
-+
-+ /* connector object id */
-+ params.usInitInfo =
-+ cpu_to_le16((uint8_t)(cntl->connector_obj_id.id));
-+ break;
-+ case TRANSMITTER_CONTROL_SET_VOLTAGE_AND_PREEMPASIS:
-+ /* votage swing and pre-emphsis */
-+ params.asMode.ucLaneSel = (uint8_t)cntl->lane_select;
-+ params.asMode.ucLaneSet = (uint8_t)cntl->lane_settings;
-+ break;
-+ default:
-+ if (dual_link_conn && cntl->multi_path)
-+ /* on ENABLE/DISABLE this bit should be set according to
-+ * actual timing (number of lanes)
-+ * Bit0: dual link connector flag
-+ * =0 connector is single link connector
-+ * =1 connector is dual link connector
-+ */
-+ params.acConfig.fDualLinkConnector = 1;
-+
-+ /* if dual-link */
-+ if (LANE_COUNT_FOUR < cntl->lanes_number) {
-+ /* on ENABLE/DISABLE this bit should be set according to
-+ * actual timing (number of lanes)
-+ * Bit0: dual link connector flag
-+ * =0 connector is single link connector
-+ * =1 connector is dual link connector
-+ */
-+ params.acConfig.fDualLinkConnector = 1;
-+
-+ /* link rate, half for dual link
-+ * We need to convert from KHz units into 20KHz units
-+ */
-+ params.usPixelClock =
-+ cpu_to_le16((uint16_t)(cntl->pixel_clock / 20));
-+ } else {
-+ /* link rate, half for dual link
-+ * We need to convert from KHz units into 10KHz units
-+ */
-+ params.usPixelClock =
-+ cpu_to_le16((uint16_t)(cntl->pixel_clock / 10));
-+ if (cntl->signal == SIGNAL_TYPE_HDMI_TYPE_A)
-+ switch (cntl->color_depth) {
-+ case COLOR_DEPTH_101010:
-+ params.usPixelClock =
-+ cpu_to_le16((le16_to_cpu(params.usPixelClock) * 30) / 24);
-+ break;
-+ case COLOR_DEPTH_121212:
-+ params.usPixelClock =
-+ cpu_to_le16((le16_to_cpu(params.usPixelClock) * 36) / 24);
-+ break;
-+ case COLOR_DEPTH_161616:
-+ params.usPixelClock =
-+ cpu_to_le16((le16_to_cpu(params.usPixelClock) * 48) / 24);
-+ break;
-+ default:
-+ break;
-+ }
-+ }
-+ break;
-+ }
-+
-+ /* 00 - coherent mode
-+ * 01 - incoherent mode
-+ */
-+
-+ params.acConfig.fCoherentMode = cntl->coherent;
-+
-+ if ((TRANSMITTER_UNIPHY_B == cntl->transmitter)
-+ || (TRANSMITTER_UNIPHY_D == cntl->transmitter)
-+ || (TRANSMITTER_UNIPHY_F == cntl->transmitter))
-+ /* Bit2: Transmitter Link selection
-+ * =0 when bit0=0, single link A/C/E, when bit0=1,
-+ * master link A/C/E
-+ * =1 when bit0=0, single link B/D/F, when bit0=1,
-+ * master link B/D/F
-+ */
-+ params.acConfig.ucLinkSel = 1;
-+
-+ if (ENGINE_ID_DIGB == cntl->engine_id)
-+ /* Bit3: Transmitter data source selection
-+ * =0 DIGA is data source.
-+ * =1 DIGB is data source.
-+ * This bit is only useful when ucAction= ATOM_ENABLE
-+ */
-+ params.acConfig.ucEncoderSel = 1;
-+
-+ /* Bit[7:6]: Transmitter selection
-+ * =0 UNIPHY_ENCODER: UNIPHYA/B
-+ * =1 UNIPHY1_ENCODER: UNIPHYC/D
-+ * =2 UNIPHY2_ENCODER: UNIPHYE/F
-+ * =3 reserved
-+ */
-+ params.acConfig.ucTransmitterSel =
-+ (uint8_t)cmd->transmitter_bp_to_atom(cntl->transmitter);
-+
-+ params.ucLaneNum = (uint8_t)cntl->lanes_number;
-+
-+ params.acConfig.ucRefClkSource = (uint8_t)pll_id;
-+
-+ params.ucAction = (uint8_t)cntl->action;
-+
-+ if (EXEC_BIOS_CMD_TABLE(UNIPHYTransmitterControl, params))
-+ result = BP_RESULT_OK;
-+
-+ return result;
-+}
-+
-+static enum bp_result transmitter_control_v4(
-+ struct bios_parser *bp,
-+ struct bp_transmitter_control *cntl)
-+{
-+ enum bp_result result = BP_RESULT_FAILURE;
-+ DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 params;
-+ uint32_t ref_clk_src_id;
-+ enum connector_id conn_id =
-+ dal_graphics_object_id_get_connector_id(cntl->connector_obj_id);
-+ const struct command_table_helper *cmd = bp->cmd_helper;
-+
-+ dc_service_memset(&params, 0, sizeof(params));
-+
-+ switch (cntl->transmitter) {
-+ case TRANSMITTER_UNIPHY_A:
-+ case TRANSMITTER_UNIPHY_B:
-+ case TRANSMITTER_UNIPHY_C:
-+ case TRANSMITTER_UNIPHY_D:
-+ case TRANSMITTER_UNIPHY_E:
-+ case TRANSMITTER_UNIPHY_F:
-+ case TRANSMITTER_TRAVIS_LCD:
-+ break;
-+ default:
-+ return BP_RESULT_BADINPUT;
-+ }
-+
-+ if (!cmd->clock_source_id_to_ref_clk_src(cntl->pll_id, &ref_clk_src_id))
-+ return BP_RESULT_BADINPUT;
-+
-+ switch (cntl->action) {
-+ case TRANSMITTER_CONTROL_INIT:
-+ {
-+ if ((CONNECTOR_ID_DUAL_LINK_DVII == conn_id) ||
-+ (CONNECTOR_ID_DUAL_LINK_DVID == conn_id))
-+ /* on INIT this bit should be set according to the
-+ * phisycal connector
-+ * Bit0: dual link connector flag
-+ * =0 connector is single link connector
-+ * =1 connector is dual link connector
-+ */
-+ params.acConfig.fDualLinkConnector = 1;
-+
-+ /* connector object id */
-+ params.usInitInfo =
-+ cpu_to_le16((uint8_t)(cntl->connector_obj_id.id));
-+ }
-+ break;
-+ case TRANSMITTER_CONTROL_SET_VOLTAGE_AND_PREEMPASIS:
-+ /* votage swing and pre-emphsis */
-+ params.asMode.ucLaneSel = (uint8_t)(cntl->lane_select);
-+ params.asMode.ucLaneSet = (uint8_t)(cntl->lane_settings);
-+ break;
-+ default:
-+ if ((CONNECTOR_ID_DUAL_LINK_DVII == conn_id) ||
-+ (CONNECTOR_ID_DUAL_LINK_DVID == conn_id))
-+ /* on ENABLE/DISABLE this bit should be set according to
-+ * actual timing (number of lanes)
-+ * Bit0: dual link connector flag
-+ * =0 connector is single link connector
-+ * =1 connector is dual link connector
-+ */
-+ params.acConfig.fDualLinkConnector = 1;
-+
-+ /* if dual-link */
-+ if (LANE_COUNT_FOUR < cntl->lanes_number)
-+ /* link rate, half for dual link
-+ * We need to convert from KHz units into 20KHz units
-+ */
-+ params.usPixelClock =
-+ cpu_to_le16((uint16_t)(cntl->pixel_clock / 20));
-+ else {
-+ /* link rate, half for dual link
-+ * We need to convert from KHz units into 10KHz units
-+ */
-+ params.usPixelClock =
-+ cpu_to_le16((uint16_t)(cntl->pixel_clock / 10));
-+
-+ if (cntl->signal == SIGNAL_TYPE_HDMI_TYPE_A)
-+ switch (cntl->color_depth) {
-+ case COLOR_DEPTH_101010:
-+ params.usPixelClock =
-+ cpu_to_le16((le16_to_cpu(params.usPixelClock) * 30) / 24);
-+ break;
-+ case COLOR_DEPTH_121212:
-+ params.usPixelClock =
-+ cpu_to_le16((le16_to_cpu(params.usPixelClock) * 36) / 24);
-+ break;
-+ case COLOR_DEPTH_161616:
-+ params.usPixelClock =
-+ cpu_to_le16((le16_to_cpu(params.usPixelClock) * 48) / 24);
-+ break;
-+ default:
-+ break;
-+ }
-+ }
-+ break;
-+ }
-+
-+ /* 00 - coherent mode
-+ * 01 - incoherent mode
-+ */
-+
-+ params.acConfig.fCoherentMode = cntl->coherent;
-+
-+ if ((TRANSMITTER_UNIPHY_B == cntl->transmitter)
-+ || (TRANSMITTER_UNIPHY_D == cntl->transmitter)
-+ || (TRANSMITTER_UNIPHY_F == cntl->transmitter))
-+ /* Bit2: Transmitter Link selection
-+ * =0 when bit0=0, single link A/C/E, when bit0=1,
-+ * master link A/C/E
-+ * =1 when bit0=0, single link B/D/F, when bit0=1,
-+ * master link B/D/F
-+ */
-+ params.acConfig.ucLinkSel = 1;
-+
-+ if (ENGINE_ID_DIGB == cntl->engine_id)
-+ /* Bit3: Transmitter data source selection
-+ * =0 DIGA is data source.
-+ * =1 DIGB is data source.
-+ * This bit is only useful when ucAction= ATOM_ENABLE
-+ */
-+ params.acConfig.ucEncoderSel = 1;
-+
-+ /* Bit[7:6]: Transmitter selection
-+ * =0 UNIPHY_ENCODER: UNIPHYA/B
-+ * =1 UNIPHY1_ENCODER: UNIPHYC/D
-+ * =2 UNIPHY2_ENCODER: UNIPHYE/F
-+ * =3 reserved
-+ */
-+ params.acConfig.ucTransmitterSel =
-+ (uint8_t)(cmd->transmitter_bp_to_atom(cntl->transmitter));
-+ params.ucLaneNum = (uint8_t)(cntl->lanes_number);
-+ params.acConfig.ucRefClkSource = (uint8_t)(ref_clk_src_id);
-+ params.ucAction = (uint8_t)(cntl->action);
-+
-+ if (EXEC_BIOS_CMD_TABLE(UNIPHYTransmitterControl, params))
-+ result = BP_RESULT_OK;
-+
-+ return result;
-+}
-+
-+static enum bp_result transmitter_control_v1_5(
-+ struct bios_parser *bp,
-+ struct bp_transmitter_control *cntl)
-+{
-+ enum bp_result result = BP_RESULT_FAILURE;
-+ const struct command_table_helper *cmd = bp->cmd_helper;
-+ DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 params;
-+
-+ dc_service_memset(&params, 0, sizeof(params));
-+ params.ucPhyId = cmd->phy_id_to_atom(cntl->transmitter);
-+ params.ucAction = (uint8_t)cntl->action;
-+ params.ucLaneNum = (uint8_t)cntl->lanes_number;
-+ params.ucConnObjId = (uint8_t)cntl->connector_obj_id.id;
-+
-+ params.ucDigMode =
-+ cmd->signal_type_to_atom_dig_mode(cntl->signal);
-+ params.asConfig.ucPhyClkSrcId =
-+ cmd->clock_source_id_to_atom_phy_clk_src_id(cntl->pll_id);
-+ /* 00 - coherent mode */
-+ params.asConfig.ucCoherentMode = cntl->coherent;
-+ params.asConfig.ucHPDSel =
-+ cmd->hpd_sel_to_atom(cntl->hpd_sel);
-+ params.ucDigEncoderSel =
-+ cmd->dig_encoder_sel_to_atom(cntl->engine_id);
-+ params.ucDPLaneSet = (uint8_t) cntl->lane_settings;
-+ params.usSymClock = cpu_to_le16((uint16_t) (cntl->pixel_clock / 10));
-+ /*
-+ * In SI/TN case, caller have to set usPixelClock as following:
-+ * DP mode: usPixelClock = DP_LINK_CLOCK/10
-+ * (DP_LINK_CLOCK = 1.62GHz, 2.7GHz, 5.4GHz)
-+ * DVI single link mode: usPixelClock = pixel clock
-+ * DVI dual link mode: usPixelClock = pixel clock
-+ * HDMI mode: usPixelClock = pixel clock * deep_color_ratio
-+ * (=1: 8bpp, =1.25: 10bpp, =1.5:12bpp, =2: 16bpp)
-+ * LVDS mode: usPixelClock = pixel clock
-+ */
-+ switch (cntl->signal) {
-+ case SIGNAL_TYPE_HDMI_TYPE_A:
-+ switch (cntl->color_depth) {
-+ case COLOR_DEPTH_101010:
-+ params.usSymClock =
-+ cpu_to_le16((le16_to_cpu(params.usSymClock) * 30) / 24);
-+ break;
-+ case COLOR_DEPTH_121212:
-+ params.usSymClock =
-+ cpu_to_le16((le16_to_cpu(params.usSymClock) * 36) / 24);
-+ break;
-+ case COLOR_DEPTH_161616:
-+ params.usSymClock =
-+ cpu_to_le16((le16_to_cpu(params.usSymClock) * 48) / 24);
-+ break;
-+ default:
-+ break;
-+ }
-+ break;
-+ default:
-+ break;
-+ }
-+
-+ if (EXEC_BIOS_CMD_TABLE(UNIPHYTransmitterControl, params))
-+ result = BP_RESULT_OK;
-+
-+ return result;
-+}
-+
-+/*******************************************************************************
-+********************************************************************************
-+**
-+** SET PIXEL CLOCK
-+**
-+********************************************************************************
-+*******************************************************************************/
-+
-+static enum bp_result set_pixel_clock_v3(
-+ struct bios_parser *bp,
-+ struct bp_pixel_clock_parameters *bp_params);
-+static enum bp_result set_pixel_clock_v5(
-+ struct bios_parser *bp,
-+ struct bp_pixel_clock_parameters *bp_params);
-+static enum bp_result set_pixel_clock_v6(
-+ struct bios_parser *bp,
-+ struct bp_pixel_clock_parameters *bp_params);
-+
-+static void init_set_pixel_clock(struct bios_parser *bp)
-+{
-+ switch (BIOS_CMD_TABLE_PARA_REVISION(SetPixelClock)) {
-+ case 3:
-+ bp->cmd_tbl.set_pixel_clock = set_pixel_clock_v3;
-+ break;
-+ case 5:
-+ bp->cmd_tbl.set_pixel_clock = set_pixel_clock_v5;
-+ break;
-+ case 6:
-+ bp->cmd_tbl.set_pixel_clock = set_pixel_clock_v6;
-+ break;
-+ default:
-+ bp->cmd_tbl.set_pixel_clock = NULL;
-+ break;
-+ }
-+}
-+
-+static enum bp_result set_pixel_clock_v3(
-+ struct bios_parser *bp,
-+ struct bp_pixel_clock_parameters *bp_params)
-+{
-+ enum bp_result result = BP_RESULT_FAILURE;
-+ PIXEL_CLOCK_PARAMETERS_V3 *params;
-+ SET_PIXEL_CLOCK_PS_ALLOCATION allocation;
-+
-+ dc_service_memset(&allocation, 0, sizeof(allocation));
-+
-+ if (CLOCK_SOURCE_ID_PLL1 == bp_params->pll_id)
-+ allocation.sPCLKInput.ucPpll = ATOM_PPLL1;
-+ else if (CLOCK_SOURCE_ID_PLL2 == bp_params->pll_id)
-+ allocation.sPCLKInput.ucPpll = ATOM_PPLL2;
-+ else
-+ return BP_RESULT_BADINPUT;
-+
-+ allocation.sPCLKInput.usRefDiv =
-+ cpu_to_le16((uint16_t)bp_params->reference_divider);
-+ allocation.sPCLKInput.usFbDiv =
-+ cpu_to_le16((uint16_t)bp_params->feedback_divider);
-+ allocation.sPCLKInput.ucFracFbDiv =
-+ (uint8_t)bp_params->fractional_feedback_divider;
-+ allocation.sPCLKInput.ucPostDiv =
-+ (uint8_t)bp_params->pixel_clock_post_divider;
-+
-+ /* We need to convert from KHz units into 10KHz units */
-+ allocation.sPCLKInput.usPixelClock =
-+ cpu_to_le16((uint16_t)(bp_params->target_pixel_clock / 10));
-+
-+ params = (PIXEL_CLOCK_PARAMETERS_V3 *)&allocation.sPCLKInput;
-+ params->ucTransmitterId =
-+ bp->cmd_helper->encoder_id_to_atom(
-+ dal_graphics_object_id_get_encoder_id(
-+ bp_params->encoder_object_id));
-+ params->ucEncoderMode =
-+ (uint8_t)(bp->cmd_helper->encoder_mode_bp_to_atom(
-+ bp_params->signal_type, false));
-+
-+ if (bp_params->flags.FORCE_PROGRAMMING_OF_PLL)
-+ params->ucMiscInfo |= PIXEL_CLOCK_MISC_FORCE_PROG_PPLL;
-+
-+ if (bp_params->flags.USE_E_CLOCK_AS_SOURCE_FOR_D_CLOCK)
-+ params->ucMiscInfo |= PIXEL_CLOCK_MISC_USE_ENGINE_FOR_DISPCLK;
-+
-+ if (CONTROLLER_ID_D1 != bp_params->controller_id)
-+ params->ucMiscInfo |= PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2;
-+
-+ if (EXEC_BIOS_CMD_TABLE(SetPixelClock, allocation))
-+ result = BP_RESULT_OK;
-+
-+ return result;
-+}
-+
-+#ifndef SET_PIXEL_CLOCK_PS_ALLOCATION_V5
-+/* video bios did not define this: */
-+typedef struct _SET_PIXEL_CLOCK_PS_ALLOCATION_V5 {
-+ PIXEL_CLOCK_PARAMETERS_V5 sPCLKInput;
-+ /* Caller doesn't need to init this portion */
-+ ENABLE_SPREAD_SPECTRUM_ON_PPLL sReserved;
-+} SET_PIXEL_CLOCK_PS_ALLOCATION_V5;
-+#endif
-+
-+#ifndef SET_PIXEL_CLOCK_PS_ALLOCATION_V6
-+/* video bios did not define this: */
-+typedef struct _SET_PIXEL_CLOCK_PS_ALLOCATION_V6 {
-+ PIXEL_CLOCK_PARAMETERS_V6 sPCLKInput;
-+ /* Caller doesn't need to init this portion */
-+ ENABLE_SPREAD_SPECTRUM_ON_PPLL sReserved;
-+} SET_PIXEL_CLOCK_PS_ALLOCATION_V6;
-+#endif
-+
-+static enum bp_result set_pixel_clock_v5(
-+ struct bios_parser *bp,
-+ struct bp_pixel_clock_parameters *bp_params)
-+{
-+ enum bp_result result = BP_RESULT_FAILURE;
-+ SET_PIXEL_CLOCK_PS_ALLOCATION_V5 clk;
-+ uint8_t controller_id;
-+ uint32_t pll_id;
-+
-+ dc_service_memset(&clk, 0, sizeof(clk));
-+
-+ if (bp->cmd_helper->clock_source_id_to_atom(bp_params->pll_id, &pll_id)
-+ && bp->cmd_helper->controller_id_to_atom(
-+ bp_params->controller_id, &controller_id)) {
-+ clk.sPCLKInput.ucCRTC = controller_id;
-+ clk.sPCLKInput.ucPpll = (uint8_t)pll_id;
-+ clk.sPCLKInput.ucRefDiv =
-+ (uint8_t)(bp_params->reference_divider);
-+ clk.sPCLKInput.usFbDiv =
-+ cpu_to_le16((uint16_t)(bp_params->feedback_divider));
-+ clk.sPCLKInput.ulFbDivDecFrac =
-+ cpu_to_le32(bp_params->fractional_feedback_divider);
-+ clk.sPCLKInput.ucPostDiv =
-+ (uint8_t)(bp_params->pixel_clock_post_divider);
-+ clk.sPCLKInput.ucTransmitterID =
-+ bp->cmd_helper->encoder_id_to_atom(
-+ dal_graphics_object_id_get_encoder_id(
-+ bp_params->encoder_object_id));
-+ clk.sPCLKInput.ucEncoderMode =
-+ (uint8_t)bp->cmd_helper->encoder_mode_bp_to_atom(
-+ bp_params->signal_type, false);
-+
-+ /* We need to convert from KHz units into 10KHz units */
-+ clk.sPCLKInput.usPixelClock =
-+ cpu_to_le16((uint16_t)(bp_params->target_pixel_clock / 10));
-+
-+ if (bp_params->flags.FORCE_PROGRAMMING_OF_PLL)
-+ clk.sPCLKInput.ucMiscInfo |=
-+ PIXEL_CLOCK_MISC_FORCE_PROG_PPLL;
-+
-+ if (bp_params->flags.SET_EXTERNAL_REF_DIV_SRC)
-+ clk.sPCLKInput.ucMiscInfo |=
-+ PIXEL_CLOCK_MISC_REF_DIV_SRC;
-+
-+ /* clkV5.ucMiscInfo bit[3:2]= HDMI panel bit depth: =0: 24bpp
-+ * =1:30bpp, =2:32bpp
-+ * driver choose program it itself, i.e. here we program it
-+ * to 888 by default.
-+ */
-+
-+ if (EXEC_BIOS_CMD_TABLE(SetPixelClock, clk))
-+ result = BP_RESULT_OK;
-+ }
-+
-+ return result;
-+}
-+
-+static enum bp_result set_pixel_clock_v6(
-+ struct bios_parser *bp,
-+ struct bp_pixel_clock_parameters *bp_params)
-+{
-+ enum bp_result result = BP_RESULT_FAILURE;
-+ SET_PIXEL_CLOCK_PS_ALLOCATION_V6 clk;
-+ uint8_t controller_id;
-+ uint32_t pll_id;
-+
-+ dc_service_memset(&clk, 0, sizeof(clk));
-+
-+ if (bp->cmd_helper->clock_source_id_to_atom(bp_params->pll_id, &pll_id)
-+ && bp->cmd_helper->controller_id_to_atom(
-+ bp_params->controller_id, &controller_id)) {
-+ /* Note: VBIOS still wants to use ucCRTC name which is now
-+ * 1 byte in ULONG
-+ *typedef struct _CRTC_PIXEL_CLOCK_FREQ
-+ *{
-+ * target the pixel clock to drive the CRTC timing.
-+ * ULONG ulPixelClock:24;
-+ * 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to
-+ * previous version.
-+ * ATOM_CRTC1~6, indicate the CRTC controller to
-+ * ULONG ucCRTC:8;
-+ * drive the pixel clock. not used for DCPLL case.
-+ *}CRTC_PIXEL_CLOCK_FREQ;
-+ *union
-+ *{
-+ * pixel clock and CRTC id frequency
-+ * CRTC_PIXEL_CLOCK_FREQ ulCrtcPclkFreq;
-+ * ULONG ulDispEngClkFreq; dispclk frequency
-+ *};
-+ */
-+ clk.sPCLKInput.ulCrtcPclkFreq.ucCRTC = controller_id;
-+ clk.sPCLKInput.ucPpll = (uint8_t) pll_id;
-+ clk.sPCLKInput.ucRefDiv =
-+ (uint8_t) bp_params->reference_divider;
-+ clk.sPCLKInput.usFbDiv =
-+ cpu_to_le16((uint16_t) bp_params->feedback_divider);
-+ clk.sPCLKInput.ulFbDivDecFrac =
-+ cpu_to_le32(bp_params->fractional_feedback_divider);
-+ clk.sPCLKInput.ucPostDiv =
-+ (uint8_t) bp_params->pixel_clock_post_divider;
-+ clk.sPCLKInput.ucTransmitterID =
-+ bp->cmd_helper->encoder_id_to_atom(
-+ dal_graphics_object_id_get_encoder_id(
-+ bp_params->encoder_object_id));
-+ clk.sPCLKInput.ucEncoderMode =
-+ (uint8_t) bp->cmd_helper->encoder_mode_bp_to_atom(
-+ bp_params->signal_type, false);
-+
-+ /* We need to convert from KHz units into 10KHz units */
-+ clk.sPCLKInput.ulCrtcPclkFreq.ulPixelClock =
-+ cpu_to_le32(bp_params->target_pixel_clock / 10);
-+
-+ if (bp_params->flags.FORCE_PROGRAMMING_OF_PLL) {
-+ clk.sPCLKInput.ucMiscInfo |=
-+ PIXEL_CLOCK_V6_MISC_FORCE_PROG_PPLL;
-+ }
-+
-+ if (bp_params->flags.SET_EXTERNAL_REF_DIV_SRC) {
-+ clk.sPCLKInput.ucMiscInfo |=
-+ PIXEL_CLOCK_V6_MISC_REF_DIV_SRC;
-+ }
-+
-+ /* clkV6.ucMiscInfo bit[3:2]= HDMI panel bit depth: =0:
-+ * 24bpp =1:30bpp, =2:32bpp
-+ * driver choose program it itself, i.e. here we pass required
-+ * target rate that includes deep color.
-+ */
-+
-+ if (EXEC_BIOS_CMD_TABLE(SetPixelClock, clk))
-+ result = BP_RESULT_OK;
-+ }
-+
-+ return result;
-+}
-+
-+/*******************************************************************************
-+********************************************************************************
-+**
-+** ENABLE PIXEL CLOCK SS
-+**
-+********************************************************************************
-+*******************************************************************************/
-+static enum bp_result enable_spread_spectrum_on_ppll_v1(
-+ struct bios_parser *bp,
-+ struct bp_spread_spectrum_parameters *bp_params,
-+ bool enable);
-+static enum bp_result enable_spread_spectrum_on_ppll_v2(
-+ struct bios_parser *bp,
-+ struct bp_spread_spectrum_parameters *bp_params,
-+ bool enable);
-+static enum bp_result enable_spread_spectrum_on_ppll_v3(
-+ struct bios_parser *bp,
-+ struct bp_spread_spectrum_parameters *bp_params,
-+ bool enable);
-+
-+static void init_enable_spread_spectrum_on_ppll(struct bios_parser *bp)
-+{
-+ switch (BIOS_CMD_TABLE_PARA_REVISION(EnableSpreadSpectrumOnPPLL)) {
-+ case 1:
-+ bp->cmd_tbl.enable_spread_spectrum_on_ppll =
-+ enable_spread_spectrum_on_ppll_v1;
-+ break;
-+ case 2:
-+ bp->cmd_tbl.enable_spread_spectrum_on_ppll =
-+ enable_spread_spectrum_on_ppll_v2;
-+ break;
-+ case 3:
-+ bp->cmd_tbl.enable_spread_spectrum_on_ppll =
-+ enable_spread_spectrum_on_ppll_v3;
-+ break;
-+ default:
-+ bp->cmd_tbl.enable_spread_spectrum_on_ppll = NULL;
-+ break;
-+ }
-+}
-+
-+static enum bp_result enable_spread_spectrum_on_ppll_v1(
-+ struct bios_parser *bp,
-+ struct bp_spread_spectrum_parameters *bp_params,
-+ bool enable)
-+{
-+ enum bp_result result = BP_RESULT_FAILURE;
-+ ENABLE_SPREAD_SPECTRUM_ON_PPLL params;
-+
-+ dc_service_memset(&params, 0, sizeof(params));
-+
-+ if ((enable == true) && (bp_params->percentage > 0))
-+ params.ucEnable = ATOM_ENABLE;
-+ else
-+ params.ucEnable = ATOM_DISABLE;
-+
-+ params.usSpreadSpectrumPercentage =
-+ cpu_to_le16((uint16_t)bp_params->percentage);
-+ params.ucSpreadSpectrumStep =
-+ (uint8_t)bp_params->ver1.step;
-+ params.ucSpreadSpectrumDelay =
-+ (uint8_t)bp_params->ver1.delay;
-+ /* convert back to unit of 10KHz */
-+ params.ucSpreadSpectrumRange =
-+ (uint8_t)(bp_params->ver1.range / 10000);
-+
-+ if (bp_params->flags.EXTERNAL_SS)
-+ params.ucSpreadSpectrumType |= ATOM_EXTERNAL_SS_MASK;
-+
-+ if (bp_params->flags.CENTER_SPREAD)
-+ params.ucSpreadSpectrumType |= ATOM_SS_CENTRE_SPREAD_MODE;
-+
-+ if (bp_params->pll_id == CLOCK_SOURCE_ID_PLL1)
-+ params.ucPpll = ATOM_PPLL1;
-+ else if (bp_params->pll_id == CLOCK_SOURCE_ID_PLL2)
-+ params.ucPpll = ATOM_PPLL2;
-+ else
-+ BREAK_TO_DEBUGGER(); /* Unexpected PLL value!! */
-+
-+ if (EXEC_BIOS_CMD_TABLE(EnableSpreadSpectrumOnPPLL, params))
-+ result = BP_RESULT_OK;
-+
-+ return result;
-+}
-+
-+static enum bp_result enable_spread_spectrum_on_ppll_v2(
-+ struct bios_parser *bp,
-+ struct bp_spread_spectrum_parameters *bp_params,
-+ bool enable)
-+{
-+ enum bp_result result = BP_RESULT_FAILURE;
-+ ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 params;
-+
-+ dc_service_memset(&params, 0, sizeof(params));
-+
-+ if (bp_params->pll_id == CLOCK_SOURCE_ID_PLL1)
-+ params.ucSpreadSpectrumType = ATOM_PPLL_SS_TYPE_V2_P1PLL;
-+ else if (bp_params->pll_id == CLOCK_SOURCE_ID_PLL2)
-+ params.ucSpreadSpectrumType = ATOM_PPLL_SS_TYPE_V2_P2PLL;
-+ else
-+ BREAK_TO_DEBUGGER(); /* Unexpected PLL value!! */
-+
-+ if ((enable == true) && (bp_params->percentage > 0)) {
-+ params.ucEnable = ATOM_ENABLE;
-+
-+ params.usSpreadSpectrumPercentage =
-+ cpu_to_le16((uint16_t)(bp_params->percentage));
-+ params.usSpreadSpectrumStep =
-+ cpu_to_le16((uint16_t)(bp_params->ds.ds_frac_size));
-+
-+ if (bp_params->flags.EXTERNAL_SS)
-+ params.ucSpreadSpectrumType |=
-+ ATOM_PPLL_SS_TYPE_V2_EXT_SPREAD;
-+
-+ if (bp_params->flags.CENTER_SPREAD)
-+ params.ucSpreadSpectrumType |=
-+ ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD;
-+
-+ /* Both amounts need to be left shifted first before bit
-+ * comparison. Otherwise, the result will always be zero here
-+ */
-+ params.usSpreadSpectrumAmount = cpu_to_le16((uint16_t)(
-+ ((bp_params->ds.feedback_amount <<
-+ ATOM_PPLL_SS_AMOUNT_V2_FBDIV_SHIFT) &
-+ ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK) |
-+ ((bp_params->ds.nfrac_amount <<
-+ ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) &
-+ ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK)));
-+ } else
-+ params.ucEnable = ATOM_DISABLE;
-+
-+ if (EXEC_BIOS_CMD_TABLE(EnableSpreadSpectrumOnPPLL, params))
-+ result = BP_RESULT_OK;
-+
-+ return result;
-+}
-+
-+static enum bp_result enable_spread_spectrum_on_ppll_v3(
-+ struct bios_parser *bp,
-+ struct bp_spread_spectrum_parameters *bp_params,
-+ bool enable)
-+{
-+ enum bp_result result = BP_RESULT_FAILURE;
-+ ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 params;
-+
-+ dc_service_memset(&params, 0, sizeof(params));
-+
-+ switch (bp_params->pll_id) {
-+ case CLOCK_SOURCE_ID_PLL0:
-+ /* ATOM_PPLL_SS_TYPE_V3_P0PLL; this is pixel clock only,
-+ * not for SI display clock.
-+ */
-+ params.ucSpreadSpectrumType = ATOM_PPLL_SS_TYPE_V3_DCPLL;
-+ break;
-+ case CLOCK_SOURCE_ID_PLL1:
-+ params.ucSpreadSpectrumType = ATOM_PPLL_SS_TYPE_V3_P1PLL;
-+ break;
-+
-+ case CLOCK_SOURCE_ID_PLL2:
-+ params.ucSpreadSpectrumType = ATOM_PPLL_SS_TYPE_V3_P2PLL;
-+ break;
-+
-+ case CLOCK_SOURCE_ID_DCPLL:
-+ params.ucSpreadSpectrumType = ATOM_PPLL_SS_TYPE_V3_DCPLL;
-+ break;
-+
-+ default:
-+ BREAK_TO_DEBUGGER();
-+ /* Unexpected PLL value!! */
-+ return result;
-+ }
-+
-+ if (enable == true) {
-+ params.ucEnable = ATOM_ENABLE;
-+
-+ params.usSpreadSpectrumAmountFrac =
-+ cpu_to_le16((uint16_t)(bp_params->ds_frac_amount));
-+ params.usSpreadSpectrumStep =
-+ cpu_to_le16((uint16_t)(bp_params->ds.ds_frac_size));
-+
-+ if (bp_params->flags.EXTERNAL_SS)
-+ params.ucSpreadSpectrumType |=
-+ ATOM_PPLL_SS_TYPE_V3_EXT_SPREAD;
-+ if (bp_params->flags.CENTER_SPREAD)
-+ params.ucSpreadSpectrumType |=
-+ ATOM_PPLL_SS_TYPE_V3_CENTRE_SPREAD;
-+
-+ /* Both amounts need to be left shifted first before bit
-+ * comparison. Otherwise, the result will always be zero here
-+ */
-+ params.usSpreadSpectrumAmount = cpu_to_le16((uint16_t)(
-+ ((bp_params->ds.feedback_amount <<
-+ ATOM_PPLL_SS_AMOUNT_V3_FBDIV_SHIFT) &
-+ ATOM_PPLL_SS_AMOUNT_V3_FBDIV_MASK) |
-+ ((bp_params->ds.nfrac_amount <<
-+ ATOM_PPLL_SS_AMOUNT_V3_NFRAC_SHIFT) &
-+ ATOM_PPLL_SS_AMOUNT_V3_NFRAC_MASK)));
-+ } else
-+ params.ucEnable = ATOM_DISABLE;
-+
-+ if (EXEC_BIOS_CMD_TABLE(EnableSpreadSpectrumOnPPLL, params))
-+ result = BP_RESULT_OK;
-+
-+ return result;
-+}
-+
-+/*******************************************************************************
-+********************************************************************************
-+**
-+** ADJUST DISPLAY PLL
-+**
-+********************************************************************************
-+*******************************************************************************/
-+
-+static enum bp_result adjust_display_pll_v2(
-+ struct bios_parser *bp,
-+ struct bp_adjust_pixel_clock_parameters *bp_params);
-+static enum bp_result adjust_display_pll_v3(
-+ struct bios_parser *bp,
-+ struct bp_adjust_pixel_clock_parameters *bp_params);
-+
-+static void init_adjust_display_pll(struct bios_parser *bp)
-+{
-+ switch (BIOS_CMD_TABLE_PARA_REVISION(AdjustDisplayPll)) {
-+ case 2:
-+ bp->cmd_tbl.adjust_display_pll = adjust_display_pll_v2;
-+ break;
-+ case 3:
-+ bp->cmd_tbl.adjust_display_pll = adjust_display_pll_v3;
-+ break;
-+ default:
-+ bp->cmd_tbl.adjust_display_pll = NULL;
-+ break;
-+ }
-+}
-+
-+static bool adjust_display_pll_bug_patch(ADJUST_DISPLAY_PLL_PARAMETERS *params)
-+{
-+ /* vbios bug: pixel clock should not be doubled for DVO with 24bit
-+ * interface */
-+ if ((params->ucTransmitterID == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
-+ && (params->ucDVOConfig == DVO_ENCODER_CONFIG_24BIT))
-+ /* the current pixel clock is good. no adjustment is required */
-+ return true;
-+ return false;
-+}
-+
-+static enum bp_result adjust_display_pll_v2(
-+ struct bios_parser *bp,
-+ struct bp_adjust_pixel_clock_parameters *bp_params)
-+{
-+ enum bp_result result = BP_RESULT_FAILURE;
-+ ADJUST_DISPLAY_PLL_PS_ALLOCATION params = { 0 };
-+
-+ /* We need to convert from KHz units into 10KHz units and then convert
-+ * output pixel clock back 10KHz-->KHz */
-+ uint32_t pixel_clock_10KHz_in = bp_params->pixel_clock / 10;
-+
-+ params.usPixelClock = cpu_to_le16((uint16_t)(pixel_clock_10KHz_in));
-+ params.ucTransmitterID =
-+ bp->cmd_helper->encoder_id_to_atom(
-+ dal_graphics_object_id_get_encoder_id(
-+ bp_params->encoder_object_id));
-+ params.ucEncodeMode =
-+ (uint8_t)bp->cmd_helper->encoder_mode_bp_to_atom(
-+ bp_params->signal_type, false);
-+ params.ucDVOConfig = (uint8_t)(bp_params->dvo_config);
-+
-+ if (adjust_display_pll_bug_patch(&params)
-+ || EXEC_BIOS_CMD_TABLE(AdjustDisplayPll, params)) {
-+ /* Convert output pixel clock back 10KHz-->KHz: multiply
-+ * original pixel clock in KHz by ratio
-+ * [output pxlClk/input pxlClk] */
-+ uint64_t pixel_clock_10KHz_out =
-+ le16_to_cpu((uint64_t)params.usPixelClock);
-+ uint64_t pixel_clock = (uint64_t)bp_params->pixel_clock;
-+
-+ bp_params->adjusted_pixel_clock =
-+ div_u64(pixel_clock * pixel_clock_10KHz_out,
-+ pixel_clock_10KHz_in);
-+ result = BP_RESULT_OK;
-+ }
-+
-+ return result;
-+}
-+
-+static enum bp_result adjust_display_pll_v3(
-+ struct bios_parser *bp,
-+ struct bp_adjust_pixel_clock_parameters *bp_params)
-+{
-+ enum bp_result result = BP_RESULT_FAILURE;
-+ ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 params;
-+ uint32_t pixel_clk_10_kHz_in = bp_params->pixel_clock / 10;
-+
-+ dc_service_memset(&params, 0, sizeof(params));
-+
-+ /* We need to convert from KHz units into 10KHz units and then convert
-+ * output pixel clock back 10KHz-->KHz */
-+ params.sInput.usPixelClock = cpu_to_le16((uint16_t)pixel_clk_10_kHz_in);
-+ params.sInput.ucTransmitterID =
-+ bp->cmd_helper->encoder_id_to_atom(
-+ dal_graphics_object_id_get_encoder_id(
-+ bp_params->encoder_object_id));
-+ params.sInput.ucEncodeMode =
-+ (uint8_t)bp->cmd_helper->encoder_mode_bp_to_atom(
-+ bp_params->signal_type, false);
-+
-+ if (DISP_PLL_CONFIG_DVO_DDR_MODE_LOW_12BIT ==
-+ bp_params->display_pll_config)
-+ params.sInput.ucDispPllConfig =
-+ DISPPLL_CONFIG_DVO_DDR_SPEED |
-+ DISPPLL_CONFIG_DVO_LOW12BIT;
-+ else if (DISP_PLL_CONFIG_DVO_DDR_MODE_UPPER_12BIT ==
-+ bp_params->display_pll_config)
-+ params.sInput.ucDispPllConfig =
-+ DISPPLL_CONFIG_DVO_DDR_SPEED |
-+ DISPPLL_CONFIG_DVO_UPPER12BIT;
-+ else if (DISP_PLL_CONFIG_DVO_DDR_MODE_24BIT ==
-+ bp_params->display_pll_config)
-+ params.sInput.ucDispPllConfig =
-+ DISPPLL_CONFIG_DVO_DDR_SPEED | DISPPLL_CONFIG_DVO_24BIT;
-+ else
-+ /* this does not mean anything here */
-+ params.sInput.ucDispPllConfig =
-+ (uint8_t)(bp_params->display_pll_config);
-+
-+ if (bp_params->ss_enable == true)
-+ params.sInput.ucDispPllConfig |= DISPPLL_CONFIG_SS_ENABLE;
-+
-+ if (bp_params->signal_type == SIGNAL_TYPE_DVI_DUAL_LINK)
-+ params.sInput.ucDispPllConfig |= DISPPLL_CONFIG_DUAL_LINK;
-+
-+ if (EXEC_BIOS_CMD_TABLE(AdjustDisplayPll, params)) {
-+ /* Convert output pixel clock back 10KHz-->KHz: multiply
-+ * original pixel clock in KHz by ratio
-+ * [output pxlClk/input pxlClk] */
-+ uint64_t pixel_clk_10_khz_out =
-+ (uint64_t)le32_to_cpu(params.sOutput.ulDispPllFreq);
-+ uint64_t pixel_clk = (uint64_t)bp_params->pixel_clock;
-+
-+ if (pixel_clk_10_kHz_in != 0) {
-+ bp_params->adjusted_pixel_clock =
-+ div_u64(pixel_clk * pixel_clk_10_khz_out,
-+ pixel_clk_10_kHz_in);
-+ } else {
-+ bp_params->adjusted_pixel_clock = 0;
-+ BREAK_TO_DEBUGGER();
-+ }
-+
-+ bp_params->reference_divider = params.sOutput.ucRefDiv;
-+ bp_params->pixel_clock_post_divider = params.sOutput.ucPostDiv;
-+
-+ result = BP_RESULT_OK;
-+ }
-+
-+ return result;
-+}
-+
-+/*******************************************************************************
-+********************************************************************************
-+**
-+** DAC ENCODER CONTROL
-+**
-+********************************************************************************
-+*******************************************************************************/
-+
-+static enum bp_result dac1_encoder_control_v1(
-+ struct bios_parser *bp,
-+ bool enable,
-+ uint32_t pixel_clock,
-+ uint8_t dac_standard);
-+static enum bp_result dac2_encoder_control_v1(
-+ struct bios_parser *bp,
-+ bool enable,
-+ uint32_t pixel_clock,
-+ uint8_t dac_standard);
-+
-+static void init_dac_encoder_control(struct bios_parser *bp)
-+{
-+ switch (BIOS_CMD_TABLE_PARA_REVISION(DAC1EncoderControl)) {
-+ case 1:
-+ bp->cmd_tbl.dac1_encoder_control = dac1_encoder_control_v1;
-+ break;
-+ default:
-+ bp->cmd_tbl.dac1_encoder_control = NULL;
-+ break;
-+ }
-+ switch (BIOS_CMD_TABLE_PARA_REVISION(DAC2EncoderControl)) {
-+ case 1:
-+ bp->cmd_tbl.dac2_encoder_control = dac2_encoder_control_v1;
-+ break;
-+ default:
-+ bp->cmd_tbl.dac2_encoder_control = NULL;
-+ break;
-+ }
-+}
-+
-+static void dac_encoder_control_prepare_params(
-+ DAC_ENCODER_CONTROL_PS_ALLOCATION *params,
-+ bool enable,
-+ uint32_t pixel_clock,
-+ uint8_t dac_standard)
-+{
-+ params->ucDacStandard = dac_standard;
-+ if (enable)
-+ params->ucAction = ATOM_ENABLE;
-+ else
-+ params->ucAction = ATOM_DISABLE;
-+
-+ /* We need to convert from KHz units into 10KHz units
-+ * it looks as if the TvControl do not care about pixel clock
-+ */
-+ params->usPixelClock = cpu_to_le16((uint16_t)(pixel_clock / 10));
-+}
-+
-+static enum bp_result dac1_encoder_control_v1(
-+ struct bios_parser *bp,
-+ bool enable,
-+ uint32_t pixel_clock,
-+ uint8_t dac_standard)
-+{
-+ enum bp_result result = BP_RESULT_FAILURE;
-+ DAC_ENCODER_CONTROL_PS_ALLOCATION params;
-+
-+ dac_encoder_control_prepare_params(
-+ &params,
-+ enable,
-+ pixel_clock,
-+ dac_standard);
-+
-+ if (EXEC_BIOS_CMD_TABLE(DAC1EncoderControl, params))
-+ result = BP_RESULT_OK;
-+
-+ return result;
-+}
-+
-+static enum bp_result dac2_encoder_control_v1(
-+ struct bios_parser *bp,
-+ bool enable,
-+ uint32_t pixel_clock,
-+ uint8_t dac_standard)
-+{
-+ enum bp_result result = BP_RESULT_FAILURE;
-+ DAC_ENCODER_CONTROL_PS_ALLOCATION params;
-+
-+ dac_encoder_control_prepare_params(
-+ &params,
-+ enable,
-+ pixel_clock,
-+ dac_standard);
-+
-+ if (EXEC_BIOS_CMD_TABLE(DAC2EncoderControl, params))
-+ result = BP_RESULT_OK;
-+
-+ return result;
-+}
-+
-+/*******************************************************************************
-+********************************************************************************
-+**
-+** DAC OUTPUT CONTROL
-+**
-+********************************************************************************
-+*******************************************************************************/
-+static enum bp_result dac1_output_control_v1(
-+ struct bios_parser *bp,
-+ bool enable);
-+static enum bp_result dac2_output_control_v1(
-+ struct bios_parser *bp,
-+ bool enable);
-+
-+static void init_dac_output_control(struct bios_parser *bp)
-+{
-+ switch (BIOS_CMD_TABLE_PARA_REVISION(DAC1OutputControl)) {
-+ case 1:
-+ bp->cmd_tbl.dac1_output_control = dac1_output_control_v1;
-+ break;
-+ default:
-+ bp->cmd_tbl.dac1_output_control = NULL;
-+ break;
-+ }
-+ switch (BIOS_CMD_TABLE_PARA_REVISION(DAC2OutputControl)) {
-+ case 1:
-+ bp->cmd_tbl.dac2_output_control = dac2_output_control_v1;
-+ break;
-+ default:
-+ bp->cmd_tbl.dac2_output_control = NULL;
-+ break;
-+ }
-+}
-+
-+static enum bp_result dac1_output_control_v1(
-+ struct bios_parser *bp, bool enable)
-+{
-+ enum bp_result result = BP_RESULT_FAILURE;
-+ DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION params;
-+
-+ if (enable)
-+ params.ucAction = ATOM_ENABLE;
-+ else
-+ params.ucAction = ATOM_DISABLE;
-+
-+ if (EXEC_BIOS_CMD_TABLE(DAC1OutputControl, params))
-+ result = BP_RESULT_OK;
-+
-+ return result;
-+}
-+
-+static enum bp_result dac2_output_control_v1(
-+ struct bios_parser *bp, bool enable)
-+{
-+ enum bp_result result = BP_RESULT_FAILURE;
-+ DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION params;
-+
-+ if (enable)
-+ params.ucAction = ATOM_ENABLE;
-+ else
-+ params.ucAction = ATOM_DISABLE;
-+
-+ if (EXEC_BIOS_CMD_TABLE(DAC2OutputControl, params))
-+ result = BP_RESULT_OK;
-+
-+ return result;
-+}
-+
-+/*******************************************************************************
-+********************************************************************************
-+**
-+** DAC LOAD DETECTION
-+**
-+********************************************************************************
-+*******************************************************************************/
-+
-+static enum signal_type dac_load_detection_v3(
-+ struct bios_parser *bp,
-+ struct graphics_object_id encoder,
-+ struct graphics_object_id connector,
-+ enum signal_type display_signal);
-+
-+static void init_dac_load_detection(struct bios_parser *bp)
-+{
-+ switch (BIOS_CMD_TABLE_PARA_REVISION(DAC_LoadDetection)) {
-+ case 3:
-+ bp->cmd_tbl.dac_load_detection = dac_load_detection_v3;
-+ break;
-+ default:
-+ bp->cmd_tbl.dac_load_detection = NULL;
-+ break;
-+ }
-+}
-+
-+static enum signal_type dac_load_detection_v3(
-+ struct bios_parser *bp,
-+ struct graphics_object_id encoder,
-+ struct graphics_object_id connector,
-+ enum signal_type display_signal)
-+{
-+ DAC_LOAD_DETECTION_PS_ALLOCATION params;
-+ enum signal_type signal = SIGNAL_TYPE_NONE;
-+
-+ dc_service_memset(&params, 0, sizeof(params));
-+
-+ /* load detection is cupported for CRT, TV and CV */
-+ switch (display_signal) {
-+ case SIGNAL_TYPE_RGB:
-+ switch (dal_graphics_object_id_get_encoder_id(encoder)) {
-+ case ENCODER_ID_INTERNAL_DAC1:
-+ case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
-+ params.sDacload.usDeviceID =
-+ cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
-+ break;
-+ case ENCODER_ID_INTERNAL_DAC2:
-+ case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
-+ params.sDacload.usDeviceID =
-+ cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
-+ break;
-+ default:
-+ break;
-+ }
-+ break;
-+ default:
-+ return signal;
-+ }
-+
-+ /* set the encoder to detect on */
-+ switch (dal_graphics_object_id_get_encoder_id(encoder)) {
-+ case ENCODER_ID_INTERNAL_DAC1:
-+ case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
-+ params.sDacload.ucDacType = ATOM_DAC_A;
-+ break;
-+ case ENCODER_ID_INTERNAL_DAC2:
-+ case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
-+ params.sDacload.ucDacType = ATOM_DAC_B;
-+ break;
-+ case ENCODER_ID_EXTERNAL_CH7303:
-+ params.sDacload.ucDacType = ATOM_EXT_DAC;
-+ break;
-+ default:
-+ return signal;
-+ }
-+
-+ if (!EXEC_BIOS_CMD_TABLE(DAC_LoadDetection, params))
-+ return signal;
-+#if defined(CONFIG_DRM_AMD_DAL_VBIOS_PRESENT)
-+ signal = bp->bios_helper->detect_sink(
-+ bp->ctx,
-+ encoder,
-+ connector,
-+ display_signal);
-+#else
-+ BREAK_TO_DEBUGGER(); /* VBios is needed */
-+#endif
-+
-+ return signal;
-+}
-+
-+/*******************************************************************************
-+********************************************************************************
-+**
-+** BLANK CRTC
-+**
-+********************************************************************************
-+*******************************************************************************/
-+
-+static enum bp_result blank_crtc_v1(
-+ struct bios_parser *bp,
-+ struct bp_blank_crtc_parameters *bp_params,
-+ bool blank);
-+
-+static void init_blank_crtc(struct bios_parser *bp)
-+{
-+ switch (BIOS_CMD_TABLE_PARA_REVISION(BlankCRTC)) {
-+ case 1:
-+ bp->cmd_tbl.blank_crtc = blank_crtc_v1;
-+ break;
-+ default:
-+ bp->cmd_tbl.blank_crtc = NULL;
-+ break;
-+ }
-+}
-+
-+static enum bp_result blank_crtc_v1(
-+ struct bios_parser *bp,
-+ struct bp_blank_crtc_parameters *bp_params,
-+ bool blank)
-+{
-+ enum bp_result result = BP_RESULT_FAILURE;
-+ BLANK_CRTC_PARAMETERS params = {0};
-+ uint8_t atom_controller_id;
-+
-+ if (bp->cmd_helper->controller_id_to_atom(bp_params->controller_id,
-+ &atom_controller_id)) {
-+ params.ucCRTC = (uint8_t)atom_controller_id;
-+
-+ if (blank)
-+ params.ucBlanking = ATOM_BLANKING;
-+ else
-+ params.ucBlanking = ATOM_BLANKING_OFF;
-+ params.usBlackColorRCr =
-+ cpu_to_le16((uint16_t)bp_params->black_color_rcr);
-+ params.usBlackColorGY =
-+ cpu_to_le16((uint16_t)bp_params->black_color_gy);
-+ params.usBlackColorBCb =
-+ cpu_to_le16((uint16_t)bp_params->black_color_bcb);
-+
-+ if (EXEC_BIOS_CMD_TABLE(BlankCRTC, params))
-+ result = BP_RESULT_OK;
-+ } else
-+ /* Not support more than two CRTC as current ASIC, update this
-+ * if needed.
-+ */
-+ result = BP_RESULT_BADINPUT;
-+
-+ return result;
-+}
-+
-+/*******************************************************************************
-+********************************************************************************
-+**
-+** SET CRTC TIMING
-+**
-+********************************************************************************
-+*******************************************************************************/
-+
-+static enum bp_result set_crtc_using_dtd_timing_v3(
-+ struct bios_parser *bp,
-+ struct bp_hw_crtc_timing_parameters *bp_params);
-+static enum bp_result set_crtc_timing_v1(
-+ struct bios_parser *bp,
-+ struct bp_hw_crtc_timing_parameters *bp_params);
-+
-+static void init_set_crtc_timing(struct bios_parser *bp)
-+{
-+ uint32_t dtd_version =
-+ BIOS_CMD_TABLE_PARA_REVISION(SetCRTC_UsingDTDTiming);
-+ if (dtd_version > 2)
-+ switch (dtd_version) {
-+ case 3:
-+ bp->cmd_tbl.set_crtc_timing =
-+ set_crtc_using_dtd_timing_v3;
-+ break;
-+ default:
-+ bp->cmd_tbl.set_crtc_timing = NULL;
-+ break;
-+ }
-+ else
-+ switch (BIOS_CMD_TABLE_PARA_REVISION(SetCRTC_Timing)) {
-+ case 1:
-+ bp->cmd_tbl.set_crtc_timing = set_crtc_timing_v1;
-+ break;
-+ default:
-+ bp->cmd_tbl.set_crtc_timing = NULL;
-+ break;
-+ }
-+}
-+
-+static enum bp_result set_crtc_timing_v1(
-+ struct bios_parser *bp,
-+ struct bp_hw_crtc_timing_parameters *bp_params)
-+{
-+ enum bp_result result = BP_RESULT_FAILURE;
-+ SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION params = {0};
-+ uint8_t atom_controller_id;
-+
-+ if (bp->cmd_helper->controller_id_to_atom(
-+ bp_params->controller_id, &atom_controller_id))
-+ params.ucCRTC = atom_controller_id;
-+
-+ params.usH_Total = cpu_to_le16((uint16_t)(bp_params->h_total));
-+ params.usH_Disp = cpu_to_le16((uint16_t)(bp_params->h_addressable));
-+ params.usH_SyncStart = cpu_to_le16((uint16_t)(bp_params->h_sync_start));
-+ params.usH_SyncWidth = cpu_to_le16((uint16_t)(bp_params->h_sync_width));
-+ params.usV_Total = cpu_to_le16((uint16_t)(bp_params->v_total));
-+ params.usV_Disp = cpu_to_le16((uint16_t)(bp_params->v_addressable));
-+ params.usV_SyncStart =
-+ cpu_to_le16((uint16_t)(bp_params->v_sync_start));
-+ params.usV_SyncWidth =
-+ cpu_to_le16((uint16_t)(bp_params->v_sync_width));
-+
-+
-+ /* VBIOS does not expect any value except zero into this call, for
-+ * underscan use another entry ProgramOverscan call but when mode
-+ * 1776x1000 with the overscan 72x44 .e.i. 1920x1080 @30 DAL2 is ok,
-+ * but when same ,but 60 Hz there is corruption
-+ * DAL1 does not allow the mode 1776x1000@60
-+ */
-+ params.ucOverscanRight = (uint8_t)bp_params->h_overscan_right;
-+ params.ucOverscanLeft = (uint8_t)bp_params->h_overscan_left;
-+ params.ucOverscanBottom = (uint8_t)bp_params->v_overscan_bottom;
-+ params.ucOverscanTop = (uint8_t)bp_params->v_overscan_top;
-+
-+ if (0 == bp_params->flags.HSYNC_POSITIVE_POLARITY)
-+ params.susModeMiscInfo.usAccess =
-+ cpu_to_le16(le16_to_cpu(params.susModeMiscInfo.usAccess) | ATOM_HSYNC_POLARITY);
-+
-+ if (0 == bp_params->flags.VSYNC_POSITIVE_POLARITY)
-+ params.susModeMiscInfo.usAccess =
-+ cpu_to_le16(le16_to_cpu(params.susModeMiscInfo.usAccess) | ATOM_VSYNC_POLARITY);
-+
-+ if (bp_params->flags.INTERLACE) {
-+ params.susModeMiscInfo.usAccess =
-+ cpu_to_le16(le16_to_cpu(params.susModeMiscInfo.usAccess) | ATOM_INTERLACE);
-+
-+ /* original DAL code has this condition to apply tis for
-+ * non-TV/CV only due to complex MV testing for possible
-+ * impact
-+ * if (pACParameters->signal != SignalType_YPbPr &&
-+ * pACParameters->signal != SignalType_Composite &&
-+ * pACParameters->signal != SignalType_SVideo)
-+ */
-+ /* HW will deduct 0.5 line from 2nd feild.
-+ * i.e. for 1080i, it is 2 lines for 1st field, 2.5
-+ * lines for the 2nd feild. we need input as 5 instead
-+ * of 4, but it is 4 either from Edid data
-+ * (spec CEA 861) or CEA timing table.
-+ */
-+ params.usV_SyncStart =
-+ cpu_to_le16((uint16_t)(bp_params->v_sync_start + 1));
-+ }
-+
-+ if (bp_params->flags.HORZ_COUNT_BY_TWO)
-+ params.susModeMiscInfo.usAccess =
-+ cpu_to_le16(le16_to_cpu(params.susModeMiscInfo.usAccess) | ATOM_DOUBLE_CLOCK_MODE);
-+
-+ if (EXEC_BIOS_CMD_TABLE(SetCRTC_Timing, params))
-+ result = BP_RESULT_OK;
-+
-+ return result;
-+}
-+
-+static enum bp_result set_crtc_using_dtd_timing_v3(
-+ struct bios_parser *bp,
-+ struct bp_hw_crtc_timing_parameters *bp_params)
-+{
-+ enum bp_result result = BP_RESULT_FAILURE;
-+ SET_CRTC_USING_DTD_TIMING_PARAMETERS params = {0};
-+ uint8_t atom_controller_id;
-+
-+ if (bp->cmd_helper->controller_id_to_atom(
-+ bp_params->controller_id, &atom_controller_id))
-+ params.ucCRTC = atom_controller_id;
-+
-+ /* bios usH_Size wants h addressable size */
-+ params.usH_Size = cpu_to_le16((uint16_t)bp_params->h_addressable);
-+ /* bios usH_Blanking_Time wants borders included in blanking */
-+ params.usH_Blanking_Time =
-+ cpu_to_le16((uint16_t)(bp_params->h_total - bp_params->h_addressable));
-+ /* bios usV_Size wants v addressable size */
-+ params.usV_Size = cpu_to_le16((uint16_t)bp_params->v_addressable);
-+ /* bios usV_Blanking_Time wants borders included in blanking */
-+ params.usV_Blanking_Time =
-+ cpu_to_le16((uint16_t)(bp_params->v_total - bp_params->v_addressable));
-+ /* bios usHSyncOffset is the offset from the end of h addressable,
-+ * our horizontalSyncStart is the offset from the beginning
-+ * of h addressable */
-+ params.usH_SyncOffset =
-+ cpu_to_le16((uint16_t)(bp_params->h_sync_start - bp_params->h_addressable));
-+ params.usH_SyncWidth = cpu_to_le16((uint16_t)bp_params->h_sync_width);
-+ /* bios usHSyncOffset is the offset from the end of v addressable,
-+ * our verticalSyncStart is the offset from the beginning of
-+ * v addressable */
-+ params.usV_SyncOffset =
-+ cpu_to_le16((uint16_t)(bp_params->v_sync_start - bp_params->v_addressable));
-+ params.usV_SyncWidth = cpu_to_le16((uint16_t)bp_params->v_sync_width);
-+
-+ /* we assume that overscan from original timing does not get bigger
-+ * than 255
-+ * we will program all the borders in the Set CRTC Overscan call below
-+ */
-+
-+ if (0 == bp_params->flags.HSYNC_POSITIVE_POLARITY)
-+ params.susModeMiscInfo.usAccess =
-+ cpu_to_le16(le16_to_cpu(params.susModeMiscInfo.usAccess) | ATOM_HSYNC_POLARITY);
-+
-+ if (0 == bp_params->flags.VSYNC_POSITIVE_POLARITY)
-+ params.susModeMiscInfo.usAccess =
-+ cpu_to_le16(le16_to_cpu(params.susModeMiscInfo.usAccess) | ATOM_VSYNC_POLARITY);
-+
-+
-+ if (bp_params->flags.INTERLACE) {
-+ params.susModeMiscInfo.usAccess =
-+ cpu_to_le16(le16_to_cpu(params.susModeMiscInfo.usAccess) | ATOM_INTERLACE);
-+
-+ /* original DAL code has this condition to apply this
-+ * for non-TV/CV only
-+ * due to complex MV testing for possible impact
-+ * if ( pACParameters->signal != SignalType_YPbPr &&
-+ * pACParameters->signal != SignalType_Composite &&
-+ * pACParameters->signal != SignalType_SVideo)
-+ */
-+ {
-+ /* HW will deduct 0.5 line from 2nd feild.
-+ * i.e. for 1080i, it is 2 lines for 1st field,
-+ * 2.5 lines for the 2nd feild. we need input as 5
-+ * instead of 4.
-+ * but it is 4 either from Edid data (spec CEA 861)
-+ * or CEA timing table.
-+ */
-+ params.usV_SyncOffset =
-+ cpu_to_le16(le16_to_cpu(params.usV_SyncOffset) + 1);
-+
-+ }
-+ }
-+
-+ if (bp_params->flags.HORZ_COUNT_BY_TWO)
-+ params.susModeMiscInfo.usAccess =
-+ cpu_to_le16(le16_to_cpu(params.susModeMiscInfo.usAccess) | ATOM_DOUBLE_CLOCK_MODE);
-+
-+ if (EXEC_BIOS_CMD_TABLE(SetCRTC_UsingDTDTiming, params))
-+ result = BP_RESULT_OK;
-+
-+ return result;
-+}
-+
-+/*******************************************************************************
-+********************************************************************************
-+**
-+** SET CRTC OVERSCAN
-+**
-+********************************************************************************
-+*******************************************************************************/
-+
-+static enum bp_result set_crtc_overscan_v1(
-+ struct bios_parser *bp,
-+ struct bp_hw_crtc_overscan_parameters *bp_params);
-+
-+static void init_set_crtc_overscan(struct bios_parser *bp)
-+{
-+ switch (BIOS_CMD_TABLE_PARA_REVISION(SetCRTC_OverScan)) {
-+ case 1:
-+ bp->cmd_tbl.set_crtc_overscan = set_crtc_overscan_v1;
-+ break;
-+ default:
-+ bp->cmd_tbl.set_crtc_overscan = NULL;
-+ break;
-+ }
-+}
-+
-+static enum bp_result set_crtc_overscan_v1(
-+ struct bios_parser *bp,
-+ struct bp_hw_crtc_overscan_parameters *bp_params)
-+{
-+ enum bp_result result = BP_RESULT_FAILURE;
-+ SET_CRTC_OVERSCAN_PARAMETERS params = {0};
-+ uint8_t atom_controller_id;
-+
-+ if (bp->cmd_helper->controller_id_to_atom(
-+ bp_params->controller_id, &atom_controller_id))
-+ params.ucCRTC = atom_controller_id;
-+ else
-+ return BP_RESULT_BADINPUT;
-+
-+ params.usOverscanRight =
-+ cpu_to_le16((uint16_t)bp_params->h_overscan_right);
-+ params.usOverscanLeft =
-+ cpu_to_le16((uint16_t)bp_params->h_overscan_left);
-+ params.usOverscanBottom =
-+ cpu_to_le16((uint16_t)bp_params->v_overscan_bottom);
-+ params.usOverscanTop =
-+ cpu_to_le16((uint16_t)bp_params->v_overscan_top);
-+
-+ if (EXEC_BIOS_CMD_TABLE(SetCRTC_OverScan, params))
-+ result = BP_RESULT_OK;
-+
-+ return result;
-+}
-+
-+/*******************************************************************************
-+********************************************************************************
-+**
-+** SELECT CRTC SOURCE
-+**
-+********************************************************************************
-+*******************************************************************************/
-+
-+static enum bp_result select_crtc_source_v2(
-+ struct bios_parser *bp,
-+ struct bp_crtc_source_select *bp_params);
-+static enum bp_result select_crtc_source_v3(
-+ struct bios_parser *bp,
-+ struct bp_crtc_source_select *bp_params);
-+
-+static void init_select_crtc_source(struct bios_parser *bp)
-+{
-+ switch (BIOS_CMD_TABLE_PARA_REVISION(SelectCRTC_Source)) {
-+ case 2:
-+ bp->cmd_tbl.select_crtc_source = select_crtc_source_v2;
-+ break;
-+ case 3:
-+ bp->cmd_tbl.select_crtc_source = select_crtc_source_v3;
-+ break;
-+ default:
-+ bp->cmd_tbl.select_crtc_source = NULL;
-+ break;
-+ }
-+}
-+
-+static enum bp_result select_crtc_source_v2(
-+ struct bios_parser *bp,
-+ struct bp_crtc_source_select *bp_params)
-+{
-+ enum bp_result result = BP_RESULT_FAILURE;
-+ SELECT_CRTC_SOURCE_PARAMETERS_V2 params;
-+ uint8_t atom_controller_id;
-+ uint32_t atom_engine_id;
-+ enum signal_type s = bp_params->signal;
-+
-+ dc_service_memset(&params, 0, sizeof(params));
-+
-+ /* set controller id */
-+ if (bp->cmd_helper->controller_id_to_atom(
-+ bp_params->controller_id, &atom_controller_id))
-+ params.ucCRTC = atom_controller_id;
-+ else
-+ return BP_RESULT_FAILURE;
-+
-+ /* set encoder id */
-+ if (bp->cmd_helper->engine_bp_to_atom(
-+ bp_params->engine_id, &atom_engine_id))
-+ params.ucEncoderID = (uint8_t)atom_engine_id;
-+ else
-+ return BP_RESULT_FAILURE;
-+
-+ if (SIGNAL_TYPE_EDP == s ||
-+ (SIGNAL_TYPE_DISPLAY_PORT == s &&
-+ SIGNAL_TYPE_LVDS == bp_params->sink_signal))
-+ s = SIGNAL_TYPE_LVDS;
-+
-+ params.ucEncodeMode =
-+ (uint8_t)bp->cmd_helper->encoder_mode_bp_to_atom(
-+ s, bp_params->enable_dp_audio);
-+
-+ if (EXEC_BIOS_CMD_TABLE(SelectCRTC_Source, params))
-+ result = BP_RESULT_OK;
-+
-+ return result;
-+}
-+
-+static enum bp_result select_crtc_source_v3(
-+ struct bios_parser *bp,
-+ struct bp_crtc_source_select *bp_params)
-+{
-+ bool result = BP_RESULT_FAILURE;
-+ SELECT_CRTC_SOURCE_PARAMETERS_V3 params;
-+ uint8_t atom_controller_id;
-+ uint32_t atom_engine_id;
-+ enum signal_type s = bp_params->signal;
-+
-+ dc_service_memset(&params, 0, sizeof(params));
-+
-+ if (bp->cmd_helper->controller_id_to_atom(bp_params->controller_id,
-+ &atom_controller_id))
-+ params.ucCRTC = atom_controller_id;
-+ else
-+ return result;
-+
-+ if (bp->cmd_helper->engine_bp_to_atom(bp_params->engine_id,
-+ &atom_engine_id))
-+ params.ucEncoderID = (uint8_t)atom_engine_id;
-+ else
-+ return result;
-+
-+ if (SIGNAL_TYPE_EDP == s ||
-+ (SIGNAL_TYPE_DISPLAY_PORT == s &&
-+ SIGNAL_TYPE_LVDS == bp_params->sink_signal))
-+ s = SIGNAL_TYPE_LVDS;
-+
-+ params.ucEncodeMode =
-+ bp->cmd_helper->encoder_mode_bp_to_atom(
-+ s, bp_params->enable_dp_audio);
-+ /* Needed for VBIOS Random Spatial Dithering feature */
-+ params.ucDstBpc = (uint8_t)(bp_params->display_output_bit_depth);
-+
-+ if (EXEC_BIOS_CMD_TABLE(SelectCRTC_Source, params))
-+ result = BP_RESULT_OK;
-+
-+ return result;
-+}
-+
-+/*******************************************************************************
-+********************************************************************************
-+**
-+** ENABLE CRTC
-+**
-+********************************************************************************
-+*******************************************************************************/
-+
-+static enum bp_result enable_crtc_v1(
-+ struct bios_parser *bp,
-+ enum controller_id controller_id,
-+ bool enable);
-+
-+static void init_enable_crtc(struct bios_parser *bp)
-+{
-+ switch (BIOS_CMD_TABLE_PARA_REVISION(EnableCRTC)) {
-+ case 1:
-+ bp->cmd_tbl.enable_crtc = enable_crtc_v1;
-+ break;
-+ default:
-+ bp->cmd_tbl.enable_crtc = NULL;
-+ break;
-+ }
-+}
-+
-+static enum bp_result enable_crtc_v1(
-+ struct bios_parser *bp,
-+ enum controller_id controller_id,
-+ bool enable)
-+{
-+ bool result = BP_RESULT_FAILURE;
-+ ENABLE_CRTC_PARAMETERS params = {0};
-+ uint8_t id;
-+
-+ if (bp->cmd_helper->controller_id_to_atom(controller_id, &id))
-+ params.ucCRTC = id;
-+ else
-+ return BP_RESULT_BADINPUT;
-+
-+ if (enable)
-+ params.ucEnable = ATOM_ENABLE;
-+ else
-+ params.ucEnable = ATOM_DISABLE;
-+
-+ if (EXEC_BIOS_CMD_TABLE(EnableCRTC, params))
-+ result = BP_RESULT_OK;
-+
-+ return result;
-+}
-+
-+/*******************************************************************************
-+********************************************************************************
-+**
-+** ENABLE CRTC MEM REQ
-+**
-+********************************************************************************
-+*******************************************************************************/
-+
-+static enum bp_result enable_crtc_mem_req_v1(
-+ struct bios_parser *bp,
-+ enum controller_id controller_id,
-+ bool enable);
-+
-+static void init_enable_crtc_mem_req(struct bios_parser *bp)
-+{
-+ switch (BIOS_CMD_TABLE_PARA_REVISION(EnableCRTCMemReq)) {
-+ case 1:
-+ bp->cmd_tbl.enable_crtc_mem_req = enable_crtc_mem_req_v1;
-+ break;
-+ default:
-+ bp->cmd_tbl.enable_crtc_mem_req = NULL;
-+ break;
-+ }
-+}
-+
-+static enum bp_result enable_crtc_mem_req_v1(
-+ struct bios_parser *bp,
-+ enum controller_id controller_id,
-+ bool enable)
-+{
-+ bool result = BP_RESULT_BADINPUT;
-+ ENABLE_CRTC_PARAMETERS params = {0};
-+ uint8_t id;
-+
-+ if (bp->cmd_helper->controller_id_to_atom(controller_id, &id)) {
-+ params.ucCRTC = id;
-+
-+ if (enable)
-+ params.ucEnable = ATOM_ENABLE;
-+ else
-+ params.ucEnable = ATOM_DISABLE;
-+
-+ if (EXEC_BIOS_CMD_TABLE(EnableCRTCMemReq, params))
-+ result = BP_RESULT_OK;
-+ else
-+ result = BP_RESULT_FAILURE;
-+ }
-+
-+ return result;
-+}
-+
-+/*******************************************************************************
-+********************************************************************************
-+**
-+** DISPLAY PLL
-+**
-+********************************************************************************
-+*******************************************************************************/
-+
-+static enum bp_result program_clock_v5(
-+ struct bios_parser *bp,
-+ struct bp_pixel_clock_parameters *bp_params);
-+static enum bp_result program_clock_v6(
-+ struct bios_parser *bp,
-+ struct bp_pixel_clock_parameters *bp_params);
-+
-+static void init_program_clock(struct bios_parser *bp)
-+{
-+ switch (BIOS_CMD_TABLE_PARA_REVISION(SetPixelClock)) {
-+ case 5:
-+ bp->cmd_tbl.program_clock = program_clock_v5;
-+ break;
-+ case 6:
-+ bp->cmd_tbl.program_clock = program_clock_v6;
-+ break;
-+ default:
-+ bp->cmd_tbl.program_clock = NULL;
-+ break;
-+ }
-+}
-+
-+static enum bp_result program_clock_v5(
-+ struct bios_parser *bp,
-+ struct bp_pixel_clock_parameters *bp_params)
-+{
-+ enum bp_result result = BP_RESULT_FAILURE;
-+
-+ SET_PIXEL_CLOCK_PS_ALLOCATION_V5 params;
-+ uint32_t atom_pll_id;
-+
-+ dc_service_memset(&params, 0, sizeof(params));
-+ if (!bp->cmd_helper->clock_source_id_to_atom(
-+ bp_params->pll_id, &atom_pll_id)) {
-+ BREAK_TO_DEBUGGER(); /* Invalid Inpute!! */
-+ return BP_RESULT_BADINPUT;
-+ }
-+
-+ /* We need to convert from KHz units into 10KHz units */
-+ params.sPCLKInput.ucPpll = (uint8_t) atom_pll_id;
-+ params.sPCLKInput.usPixelClock =
-+ cpu_to_le16((uint16_t) (bp_params->target_pixel_clock / 10));
-+ params.sPCLKInput.ucCRTC = (uint8_t) ATOM_CRTC_INVALID;
-+
-+ if (bp_params->flags.SET_EXTERNAL_REF_DIV_SRC)
-+ params.sPCLKInput.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC;
-+
-+ if (EXEC_BIOS_CMD_TABLE(SetPixelClock, params))
-+ result = BP_RESULT_OK;
-+
-+ return result;
-+}
-+
-+static enum bp_result program_clock_v6(
-+ struct bios_parser *bp,
-+ struct bp_pixel_clock_parameters *bp_params)
-+{
-+ enum bp_result result = BP_RESULT_FAILURE;
-+
-+ SET_PIXEL_CLOCK_PS_ALLOCATION_V6 params;
-+ uint32_t atom_pll_id;
-+
-+ dc_service_memset(&params, 0, sizeof(params));
-+
-+ if (!bp->cmd_helper->clock_source_id_to_atom(
-+ bp_params->pll_id, &atom_pll_id)) {
-+ BREAK_TO_DEBUGGER(); /*Invalid Input!!*/
-+ return BP_RESULT_BADINPUT;
-+ }
-+
-+ /* We need to convert from KHz units into 10KHz units */
-+ params.sPCLKInput.ucPpll = (uint8_t)atom_pll_id;
-+ params.sPCLKInput.ulDispEngClkFreq =
-+ cpu_to_le32(bp_params->target_pixel_clock / 10);
-+
-+ if (bp_params->flags.SET_EXTERNAL_REF_DIV_SRC)
-+ params.sPCLKInput.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC;
-+
-+ if (EXEC_BIOS_CMD_TABLE(SetPixelClock, params)) {
-+ /* True display clock is returned by VBIOS if DFS bypass
-+ * is enabled. */
-+ bp_params->dfs_bypass_display_clock =
-+ (uint32_t)(le32_to_cpu(params.sPCLKInput.ulDispEngClkFreq) * 10);
-+ result = BP_RESULT_OK;
-+ }
-+
-+ return result;
-+}
-+
-+/*******************************************************************************
-+********************************************************************************
-+**
-+** COMPUTE MEMORY ENGINE PLL
-+**
-+********************************************************************************
-+*******************************************************************************/
-+
-+static enum bp_result compute_memore_engine_pll_v4(
-+ struct bios_parser *bp,
-+ struct bp_display_clock_parameters *bp_params);
-+
-+static void init_compute_memore_engine_pll(struct bios_parser *bp)
-+{
-+ switch (BIOS_CMD_TABLE_PARA_REVISION(ComputeMemoryEnginePLL)) {
-+ case 4:
-+ bp->cmd_tbl.compute_memore_engine_pll =
-+ compute_memore_engine_pll_v4;
-+ break;
-+ default:
-+ bp->cmd_tbl.compute_memore_engine_pll = NULL;
-+ break;
-+ }
-+}
-+
-+static enum bp_result compute_memore_engine_pll_v4(
-+ struct bios_parser *bp,
-+ struct bp_display_clock_parameters *bp_params)
-+{
-+ enum bp_result result = BP_RESULT_FAILURE;
-+ COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 params;
-+
-+ dc_service_memset(&params, 0, sizeof(params));
-+
-+ params.ulClock = cpu_to_le32(bp_params->target_display_clock / 10);
-+
-+ /* Initialize this to the target clock in case this call fails */
-+ bp_params->actual_display_clock = bp_params->target_display_clock;
-+
-+ if (EXEC_BIOS_CMD_TABLE(ComputeMemoryEnginePLL, params)) {
-+ /* Convert from 10KHz units back to KHz */
-+ bp_params->actual_display_clock =
-+ le32_to_cpu(params.ulClock) * 10;
-+ bp_params->actual_post_divider_id = params.ucPostDiv;
-+ result = BP_RESULT_OK;
-+ }
-+
-+ return result;
-+}
-+
-+/*******************************************************************************
-+********************************************************************************
-+**
-+** EXTERNAL ENCODER CONTROL
-+**
-+********************************************************************************
-+*******************************************************************************/
-+
-+static enum bp_result external_encoder_control_v3(
-+ struct bios_parser *bp,
-+ struct bp_external_encoder_control *cntl);
-+
-+static void init_external_encoder_control(
-+ struct bios_parser *bp)
-+{
-+ switch (BIOS_CMD_TABLE_PARA_REVISION(ExternalEncoderControl)) {
-+ case 3:
-+ bp->cmd_tbl.external_encoder_control =
-+ external_encoder_control_v3;
-+ break;
-+ default:
-+ bp->cmd_tbl.external_encoder_control = NULL;
-+ break;
-+ }
-+}
-+
-+static enum bp_result external_encoder_control_v3(
-+ struct bios_parser *bp,
-+ struct bp_external_encoder_control *cntl)
-+{
-+ enum bp_result result = BP_RESULT_FAILURE;
-+
-+ /* we need use _PS_Alloc struct */
-+ EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 params;
-+ EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3 *cntl_params;
-+ struct graphics_object_id encoder;
-+ bool is_input_signal_dp = false;
-+
-+ dc_service_memset(&params, 0, sizeof(params));
-+
-+ cntl_params = &params.sExtEncoder;
-+
-+ encoder = cntl->encoder_id;
-+
-+ /* check if encoder supports external encoder control table */
-+ switch (dal_graphics_object_id_get_encoder_id(encoder)) {
-+ case ENCODER_ID_EXTERNAL_NUTMEG:
-+ case ENCODER_ID_EXTERNAL_TRAVIS:
-+ is_input_signal_dp = true;
-+ break;
-+
-+ default:
-+ BREAK_TO_DEBUGGER();
-+ return BP_RESULT_BADINPUT;
-+ }
-+
-+ /* Fill information based on the action
-+ *
-+ * Bit[6:4]: indicate external encoder, applied to all functions.
-+ * =0: external encoder1, mapped to external encoder enum id1
-+ * =1: external encoder2, mapped to external encoder enum id2
-+ *
-+ * enum ObjectEnumId
-+ * {
-+ * EnumId_Unknown = 0,
-+ * EnumId_1,
-+ * EnumId_2,
-+ * };
-+ */
-+ cntl_params->ucConfig = (uint8_t)((encoder.enum_id - 1) << 4);
-+
-+ switch (cntl->action) {
-+ case EXTERNAL_ENCODER_CONTROL_INIT:
-+ /* output display connector type. Only valid in encoder
-+ * initialization */
-+ cntl_params->usConnectorId =
-+ cpu_to_le16((uint16_t)cntl->connector_obj_id.id);
-+ break;
-+ case EXTERNAL_ENCODER_CONTROL_SETUP:
-+ /* EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3 pixel clock unit in
-+ * 10KHz
-+ * output display device pixel clock frequency in unit of 10KHz.
-+ * Only valid in setup and enableoutput
-+ */
-+ cntl_params->usPixelClock =
-+ cpu_to_le16((uint16_t)(cntl->pixel_clock / 10));
-+ /* Indicate display output signal type drive by external
-+ * encoder, only valid in setup and enableoutput */
-+ cntl_params->ucEncoderMode =
-+ (uint8_t)bp->cmd_helper->encoder_mode_bp_to_atom(
-+ cntl->signal, false);
-+
-+ if (is_input_signal_dp) {
-+ /* Bit[0]: indicate link rate, =1: 2.7Ghz, =0: 1.62Ghz,
-+ * only valid in encoder setup with DP mode. */
-+ if (LINK_RATE_HIGH == cntl->link_rate)
-+ cntl_params->ucConfig |= 1;
-+ /* output color depth Indicate encoder data bpc format
-+ * in DP mode, only valid in encoder setup in DP mode.
-+ */
-+ cntl_params->ucBitPerColor =
-+ (uint8_t)(cntl->color_depth);
-+ }
-+ /* Indicate how many lanes used by external encoder, only valid
-+ * in encoder setup and enableoutput. */
-+ cntl_params->ucLaneNum = (uint8_t)(cntl->lanes_number);
-+ break;
-+ case EXTERNAL_ENCODER_CONTROL_ENABLE:
-+ cntl_params->usPixelClock =
-+ cpu_to_le16((uint16_t)(cntl->pixel_clock / 10));
-+ cntl_params->ucEncoderMode =
-+ (uint8_t)bp->cmd_helper->encoder_mode_bp_to_atom(
-+ cntl->signal, false);
-+ cntl_params->ucLaneNum = (uint8_t)cntl->lanes_number;
-+ break;
-+ default:
-+ break;
-+ }
-+
-+ cntl_params->ucAction = (uint8_t)cntl->action;
-+
-+ if (EXEC_BIOS_CMD_TABLE(ExternalEncoderControl, params))
-+ result = BP_RESULT_OK;
-+
-+ if (EXTERNAL_ENCODER_CONTROL_DAC_LOAD_DETECT == cntl->action) {
-+#if defined(CONFIG_DRM_AMD_DAL_VBIOS_PRESENT)
-+ if (BP_RESULT_OK == result)
-+ /* get VBIOS result from scratch register.
-+ * ExternalEncoderControl runs detection and save result
-+ * in BIOS scratch registers. */
-+ cntl->signal = bp->bios_helper->detect_sink(
-+ bp->ctx,
-+ encoder,
-+ cntl->connector_obj_id,
-+ cntl->signal);
-+ else/* BIOS table does not work. */
-+#endif
-+ {
-+ BREAK_TO_DEBUGGER(); /* VBios is needed */
-+ cntl->signal = SIGNAL_TYPE_NONE;
-+ }
-+ }
-+
-+ return result;
-+}
-+
-+/*******************************************************************************
-+********************************************************************************
-+**
-+** ENABLE DISPLAY POWER GATING
-+**
-+********************************************************************************
-+*******************************************************************************/
-+
-+static enum bp_result enable_disp_power_gating_v2_1(
-+ struct bios_parser *bp,
-+ enum controller_id crtc_id,
-+ enum bp_pipe_control_action action);
-+
-+static void init_enable_disp_power_gating(
-+ struct bios_parser *bp)
-+{
-+ switch (BIOS_CMD_TABLE_PARA_REVISION(EnableDispPowerGating)) {
-+ case 1:
-+ bp->cmd_tbl.enable_disp_power_gating =
-+ enable_disp_power_gating_v2_1;
-+ break;
-+ default:
-+ bp->cmd_tbl.enable_disp_power_gating = NULL;
-+ break;
-+ }
-+}
-+
-+static enum bp_result enable_disp_power_gating_v2_1(
-+ struct bios_parser *bp,
-+ enum controller_id crtc_id,
-+ enum bp_pipe_control_action action)
-+{
-+ enum bp_result result = BP_RESULT_FAILURE;
-+
-+ ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 params = {0};
-+ uint8_t atom_crtc_id;
-+
-+ if (bp->cmd_helper->controller_id_to_atom(crtc_id, &atom_crtc_id))
-+ params.ucDispPipeId = atom_crtc_id;
-+ else
-+ return BP_RESULT_BADINPUT;
-+
-+ params.ucEnable =
-+ bp->cmd_helper->disp_power_gating_action_to_atom(action);
-+
-+ if (EXEC_BIOS_CMD_TABLE(EnableDispPowerGating, params))
-+ result = BP_RESULT_OK;
-+
-+ return result;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/command_table.h b/drivers/gpu/drm/amd/dal/dc/bios/command_table.h
-new file mode 100644
-index 0000000..814d31f
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/command_table.h
-@@ -0,0 +1,117 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and